PLL102-03 PLL | Alldatasheet

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Technical content

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 1

FEATURES

Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spec- trum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation). Zero input - output delay. Less than 700 ps device - device skew. Less than 250 ps skew between outputs. Less than 150 ps cycle - cycle jitter. Output Enable function tri-state outputs. 3.3V operation. Available in 8-Pin 150mil SOIC GREEN package.

DESCRIPTION

The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC pack- age. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew be- tween the input and output is less than ±350 ps, the device acts as a zero delay buffer. PIN CONFIGURATION Remark If REF clock is stopped for more than 10us after it has already been provided to the chip, and after power-up, the output clocks will disappear. In that instance, a full power-up reset is required in order to reactivate the output clocks. BLOCK DIAGRAM PLL REF CLKOUT CLK1 CLK2 CLK3 CLK4 REF CLK2 CLK1 GND CLKOUT CLK4 VDD CLK3 PLL102-03

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 2 PIN DESCRIPTIONS Name Number Type I Input reference frequency. Spread spectrum modulation on this signal will be passed to the output (up to 100kHz SST modulation). CLK22 O Buffered clock output. CLK12 O Buffered clock output. GND P Ground. CLK32 O Buffered clock output. VDD P 3.3V Power Supply. CLK42 O Buffered clock output. CLKOUT2 O Buffered clock output. Internal feed back on this pin. Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 Ambient Operating Temperature* TA -40 Junction Temperature TJ 125 Lead Temperature (soldering, 10s) 260 ESD Protection, Human Body Model kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con- ditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Voltage VDD 2.97 3.63 V Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V Input Low Current IIL VIN = 0V 50.0 µA Input High Current IIH VIN = VDD 0.10 100.0 µA Output Low Voltage VOL IOL = 50mA 0.25 0.4 V Output High Voltage VOH IOH = 50mA 2.4 2.9 V Power Down Supply Current IDD REF = 0MHz 0.3 50.0 µA Supply Current IDD Unloaded outputs at 133MHz, SEL inputs at VDD or GND mA

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 3 3. Switching Characteristics PARAMETERS SYMBOL MIN. TYP. MAX. UNITS Output Frequency 180 MHz Duty Cycle ( t2 ÷ t1 ) Dt1 Measured at 1.4V, CL=30pF 40.0 50.0 60.0 Duty Cycle ( t2 ÷ t1 ) Dt2 Measured at 1.4V 45.0 50.0 55.0 Rise Time Tr Measured between 0.8V and 2.0V, CL=30pF 1.2 1.5 ns Fall Time Tf Measured between 2.0V and 0.8V, CL=30pF 1.2 1.5 ns Output to Output Skew Tskew All outputs equally loaded, CL=20pF 250 ps Delay, REF Rising Edge to CLKOUT Rising Edge Tdelay Measured at 1.4V ±350 ps Device to Device Skew Tdsk-dsk Measured at VDD/2 on the CLKOUT pins of devices 700 ps Cycle to Cycle Jitter Tcyc-cyc Measured at 133MHz, loaded outputs 150 ps PLL Lock Time Tlock Stable power supply, valid clock presented on REF pin 1.0 ms Jitter; Absolute Jitter Tjabs At 10,000 cycles, CL=30pF 100 ps Jitter; 1-sigma Tj1-s At 10,000 cycles, CL=30pF ps SWITCHING WAVEFORMS Duty Cycle Timing 1.4V 1.4V 1.4V Output - Output Skew 1.4V 1.4V TSKEW Output Output

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 4 SWITCHING WAVE FORMS All Outputs Rise/Fall Time 0.8V 2.0V Output tr tf 2.0V 0.8V 3.3V Input to Output Propagation Delay Input Output VDD/2 Tdelay VDD/2 Device to Device Skew Device1 CLKOUT Device2 CLKOUT VDD/2 Tdsk - dsk VDD/2

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 5 Output-Output Skew REF CLKOUT The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; if the CLK(0-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT. Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but difference loads cause them to have different rise times and different times crossing the measurement thresholds. CLK(1-4) Zero Delay REF CLKOUT CLK(1-4) Advanced REF CLKOUT CLK(1-4) Delayed REF input and all outputs loaded equally REF input and CLK(1-4) outputs loaded equally, with CLK(1-4) less loaded than CLKOUT. REF input and CLK(1-4) outputs loaded equally, with CLK(1-4) more loaded than CLKOUT.

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 6

PACKAGE INFORMATION

ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur- nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex- press written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL102-03 X X X X Part / Order Number Marking Package Option PLL102-03SC P102-03SC 8-Pin SOIC (Tube) PLL102-03SC-R P102-03SC 8-Pin SOIC (Tape and Reel) PLL102-03SCL P102-03SCL 8-Pin SOIC GREEN (Tube) PLL102-03SCL-R P102-03SCL 8-Pin SOIC GREEN (Tape and Reel) C L A

8 PIN Narrow SOIC ( mm )

Min. Max. A 1.55 1.73 0.15 0.18 B 0.35 0.49 C 0.19 0.25 D 4.80 4.98 E 3.81 3.99 H 5.84 6.20 L 0.41 0.89 e

1.27 BSC

E H D A e B PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE S= SOIC NONE=NORMAL PACKAGE L=GREEN PACKAGE NONE= TUBE R=TAPE AND REEL