N80C321-1

80C321 AMD | Alldatasheet

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CMOS Single-Chip Microcontroller FINAL DISTINCTIVE CHARACTERISTICS ‘© Software and pin-compatibie with 80C51 RAM ROM © Dedicated Watchdog Timer (bytes) __(bytes) —Robust: immune to software disables s0ca21 256 — —Flexible: user programmable trom 80C521 256 8k 128 microseconds to 4 seconds at 12 MHz 800541 256 16K © Dual Data Pointers 800521 = 800321 + 8K bytes ROM —Faster external memory access : © Sotwore Penet 80C541 = 80C321 + 16K bytes ROM GENERAL DESCRIPTION The 800521 Family (80521, 80C321, and 80C541) is a It is user programmable from 128 microseconds to 4 fully instruction-set-compatible and pin-compatibie en- seconds at 12 MHz. hancement of the industry-standard 80C51 architecture. ; ‘These products include a programmable Watchdog Timer The Dual Data Pointers structure speeds access to external mory by providing two identical 16-bit data pointers with ang Dual Data Pointers to enhance reliabilty and improve 2 Yatt 2aitching morhariem, This oveootnce's wedltonat Performance. ‘8051 limitation of only a single data pointer and can The 80C521, 800321, and 80Q541 include 256 bytes of _ improve performance of tasks such as block transfers by RAM. The 800521 has 8} chi Re over JO, moreutGliiitien consult tho Software the 80C541 has 16K byt ha Ro seo tape on-chip ROM. 4 Big in plastic DIP and 44- A dedicated Watchd. waszedded pi As. 52T2/B0C32T2, the hanced system relabil , PLE b ional supply connec- ESD, and software fai ti tions’ B, arid fareatly improve noise special software and electrical isolation features. For exam- tolerance over packages with a single Voc and Vss Pie, it cannot be disabled by potentially corrupted software. connection. . SIMPLIFIED BLOCK DIAGRAM recouency meen? counrens : (eee ‘ic : ] : | “Bammeee CS) rrocramunzio | | *eutconex : | contrat + Browaoncus : : | SHETER, Inrereuers I fi f : i renner conto ankives rs seein, sth AboaESS bata BUS amet 20 Ps ‘80007216 Bublicalion @ Rev Amendment ‘00136 c 70

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ORDERING INFORMATION

AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type ©. Device Number d. Speed Option @. Optional Processing L 4. OPTIONAL PROCESSING Blank = Standard processing 4. SPEED OPTION Blank = 0.1 to 12 MHz 1501 to 16 MAE ¢. DEVICE NUMBER/DESCRIPTION #00821 /800921 /80C841 CMOS Single-Chip Microcontroller b. PACKAGE TYPE P= 40.Pin Pastc DIP (PD 040) N= 44-Pin Plastic Leaded Chip Carrier (PL 044) &. TEMPERATURE RANGE Blank = Commercial (0 10, +70%C) {Industral (-40 to +85°C) Valid Combinations [vats combinations] Valid Combinations fist configurations planned to be Naild Combinations ‘supported in volume for this device. Consult the local AMD [eocser_ sales office to contirm availability of specific valid [eocser.1 | ‘combinations, to check on newly released valid combinations, ‘and to obtain additional data on AMD's standard miltary [eocszs grade products, [socsay [eocsayy | 8-4 80C521/80C321/80C541

Port 0 (Bidirectional, Open Drain) RST Reset (Input/Output, Active High) Port 0 is an open-drain bidirectional I/O port. Port O pins that A High on this pin (for two machine cycles while the have 18 written to them float, and in that state can be used ‘oscillator is running) resets the device. An internal diffused as high-impedance inputs. resistor to Vss permits power-on reset, using only an Port 0 is also the multiplexed Low-order address and data extemal capacitor to Voc. bus during accesses to external Program and Data Memory. Immediately prior to a Watchdog Reset or Software Reset, in this application it uses strong internal pullups when this pin is pulled High for one state time. The internal pull-up emitting 18. Port 0 also outputs the code bytes during can be overdriven by an external driver capable of sinking/ rogram verification in the 80C521. External pullups are sourcing 2.5 mA (see Figure 6 for possible circuit required during program verification. configurations). Port 1 (Bidirectional) ALE Address Latch Enable (Output, Active High) Port 1 is an 8-bit bidirectional I/O port with internal pullups. ‘Address Latch Enable is the output pulse for latching the The Port 1 output buffers can sink/source four LSTTL Low byte of the address during accesses to external inputs. Port 1 pins that have 1s written to them are pulled memory. High by the intemal pullups and can be used as inputs white in normal operation ALE is emitted at a constant rate of 1/6 in this state. As inputs, Port + pins that are externally being ‘the oscillator frequency, allowing use for external timing or pulled Low will source current (Ii, on the data sheet) clocking purposes. Note, however, that one ALE pulse is because of the internal pullups. skipped during each access to external Data Memory. Port 1 also receives the Low-order address bytes during BEEN rogram Store Enable (Output, Active Low) Program veriication. PSEN is the read strobe to external Program Memory. When Port 2 (Bidirectional) the 80C521_is executing code from external program Port 2 is an 8-bit bidirectional I/O port with internal pullups. memory, PSEN is activated twice each machine cyclo, The Port 2 output buffers can sink/source four LSTTL ‘except that two PSEN activations are skipped during each inputs. Port 2 pins having 1s written to them are pulled High access to external Data Memory. PSEN is not activated by the internal pullups and can be used as inputs while in during fetches from internal Program Memory. this state. As inputs, Port 2 pins externally being pulled Low ER External Access Enable (Input, Active Low) will source current (\\i_) because of the internal pullups. ER must be externally held Low to enable the device to Port 2 emits the High-order address byte during fetches fetch cade trom external Program Memory locations 0000H from external Program Memory and during accesses to to 1FFFH. It EA is held High, the device executes from external Data Memory that use 16-bit addresses (MOVX internal Program Memory unless the program counter @DPTR). In this application it uses strong internal pullups contains an address greater than 1FFFH. when emitting 1s. During accesses to external data memory ‘The 80C821 internal! ly latches the value of the EA pin at the that use @-bit addresses (MOVX @Ri), Port 2 emits the falling edge of the reset pulse on the AST pin during a contents of the P2 Special Function Register. Port 2 also Hardware or Power-on Reset. Once latched, the EA value receives the High-order address bits during ROM cannot be changed except by a Hardware reset verification, XTALy Crystal (Input) Port 3 (Bidirectional) Input to the inverting-oscillator amplifier, and input to the Port 9 is an 8-bit bidirectional I/O port with internal pullups. internal clock-generator circuits. ‘The Port 3 output buffers can sink/source four LSTTL inputs. Port 3 pins that have 1s written to them are pulled XTAL2 Crystal (Output) High by the internal pullups and can be used as inputs while Output from the inverting-oscillator ampifier. in this state. As inputs, Port 3 pins externally being pulled Voc Power Supply Low will source current (\\\\,) because of the pullups. ‘Supply voltage during normal, idle, and power-down Port 3 also serves the functions of various special features operations. as listed below. Vss_Circult Ground [Pao | RxD (eoral input por) [Pax | TD (serial output por) |__Pa2 | INTo (external interrupt 0) [P33 _| INT; (external interrupt 1) [Psa | To (Timer 0 external input) [Pas _| Ti (Timer 1 external input) |_Pas _ | WA (external Data Memory write strobe) AD (external Data Memory read strobe) 80C521/800321/80C541 8-5

Program Memory vpper 128 ys of RAM, and ihe 128 Speci Function Ragister (SFR) space. The lower 128 bytes of RAM can be The 800521 has 64K bytes of Program Memory space. The ccussed through efect adsressing (ve. MOV adr eat, oF lower BK bytes (addresses OO00H to TFFF) may reside on. indirect addressing (.¢., MOV @ Ri). The upper 128 bytes of chip. Instuctions residing at addresses beyond 1FFF wil avy (ications BOH through FFH) can ke accessed only aways be fetched externally, When the External Accoss (EA) through indract addressing, modes. The. Special Fonchon pin is held Low, all code-fetch operations take place externally gnstor space, while physteally distinct trom the upper. 128 to the Bocsz1. bytes of RAM, shares addresses with the upper 128 bytes of RAM. The SFR space may be accessed through direct Data Memory addressing modes only, tothe chp. The MOK inate are neo cece na, The ist 92 bytes of RAM contain four register barks, each of . cess which contains eight general-purpose registers. The next 16 extornal Data Memory bytes (ocatone 20H trough arr) contain 128 Grecty a The internal data memory comprises three physically distinct _dressable bit locations. The stack may be located anywhere in memory spaces. They are the lower 128 bytes of RAM, the the internal RAM space and may be up to 266 bytes in length. SPECIAL FUNCTION REGISTER MAP. Default After Power-On Reset eo | PO Pon 0 Tints er | sP Stack Pointer (00000111 82 | PL | Data Pointer Low ‘90000000 83 | OPH | Data Pointer High ‘00000000 +84 | DPL1 | Data Pointer Low 1 ‘00000000 +85 | DPHt | Data Pointer High 1 ‘00000000 +86 | OPS —_| Data Pointer Selection ‘00000000 87 | PCON | Power Control ‘0XXx0000 +88 | TCON | Timer/Counter Control ‘00000000 89 | TMOD | Timer/Counter Mode Control ‘90000000 ea | Tlo Timer/Gounter 0 Low Byte ‘90000000 sp | tu Timer/Gounter 1 Low Byte ‘90000000 sc | THO | Timer/Counter 0 High Byte ‘00000000 eo | THI Timer/Counter 1 High Byte 00000000 an) Port 4 snnititi +98 | SCON | Serial Control 00000000 99 | BUF | Serial Data Butter Indeterminate a0 | Pe Port 2 sntnitt ag [IE Interrupt Enable Control (0xx00000 +a | wos — | Watchdog Selection 00000000 +Aa | WOK — | Watchdog Key 00000000 B80 | Ps Port 3 anita es | iP Interrupt Priority Control Xxx00000 +0 | Psw — | Program Status Word 00000000 *€0 | Acc | Accumulator 00000000 Fo |B B Register 00000000 * Bit Addressabie * New SFRs defined on the 800521/80C921 86 80C521/80C321/80C541

Basic Timing Definitions Once enabled, One tou cannot be stopped ees " sates e types in Instructions in the 8051 family execute in either one, two, or SAOgbt BY ne of he four Reset ypas descr ed uns four machine cycles. A machine cycle comprises six state interval cannot be modified, The WOT, however, may be times with each state made up of two clock cycles; thus, @ Cleared by software at any time with the same sequence of machine cycle lasts 12 clock cycles. With an external oscila- two. write. operations. The clearing operation causes, the tor running at 12 MHz, a machine cycle lasts 1 us. At 16MHz, present count of the WOT to be set to zero, but it does not a machine cycle lasts 750 ns. stop the WOT from incrementing. Reset Operation If the count in the WDT ever reaches the pre-programmed ‘The 80C521/80C321 may be reset by four different methods: boneuhield wiwatenoog ow reson Ssaticrely svete (1) Power-On Reset, (2) Hardware Reset, (3) Watchdog Reset, error condition is discovered, software may intentionally gen- nd (4) Softwere Reset ‘erate an immediate reset via the WOT, using a special 1. Power-On Reset occurs when the RST pin is wired to Voc. «Sequence of write operations. This is a Software Reset. using an external capacitor, and Voc is activated. ‘A Watchdog Reset or Software Reset will set a special 2. Hardware Reset occurs when the oscillator is running and “cause” bit, allowing differentiation between these two Reset the RST pin is held High for two or more machine cycles. types and the Hardware or Power-On Reset types. Neither 3. Watchdog Reset occurs when the count value of the Warchded lees ae the forware i seeniier auemrlte Wetendog Timer Is allowed to exceed the hele baie value, pin to be pulled High during S2P1 and S2P2 of the first cycle of resulting in an overflow signal that resets the chip in Wo the two-cycle reset, providing a hardware indication that @ machine cycles. reset is imminent. 4. Software Reset occurs when the software writes a keyed sequence to the key register of the Watchdog Timer. This Wrvr' the ara ae folewer oon ne aesnoiated wi ihe causes a Watchdog Reset to be immediately generated. ‘After Power-On Reset, the SFRs have the values indicated in Welchdog Selection (WO5}— Addrees: A2 (Hex) the Special Function Register Map Section, and the contents Watchdog Key (WOK) — Address: AA (Hox) of the internal RAM are undefined. Hardware Reset is the . same as Power-On Reset except that the contents of the Watchdog Selection (WDS) — Address: AGH internal RAM are preserved. A Hardware Reset has priority The Watchdog Selection register allows the time interval of ‘over a Watchdog Reset or a Software Reset. The Watchdog _the WOT to be programmed and retains the cause of the most Reset puts the 80C521 into the same state as the Hardware recent reset. This register is Read/Write, but its contents Reset except that the Reset Cause (RC) bit in the Watchdog cannot be changed once the WOT has been enabled. Its Selection (WDS) register is set to a 1. The Software Reset is default value after a Hardware or Power-On Reset = OOH. Its functionally equivalent to the Watchdog Reset. default value after a Watchdog Reset or Software Re- set = 80H. This is the only register on the 80C521 whose Watchdog Timer initialization value differs between the two reset groups. ‘The Watchdog Timer (WOT) is a specially designed timer unit (uss) ass) that will reset the chip upon reaching a pre-programmed time interval, it operates independently of the two general purpose = LRC | - [ wv] - [ers] pre ers [ero | ‘imer/counters and is dedicated specifically to the watchdog 7 6 5 # 8 2 1 © function. The Watchdog Timer allows safe recovery from problems resulting from unexpected input conditions, external Bits 3-0 — Programmed Time (PT3-PTO) events, or programming anomalies. The value contained in these bits at the time the Watchdog The WOT is disabled following any reset. While disabled, the Timer is enabled determines the time interval of the WOT. The WOT time interval may be programmed, The WOT is enabled —_time interval is a multiple of the input clock period. The times by @ sequence of two write operations. are decoded in the following table. Programmable Watchdog Timing Intervals [ersero | i2mHz | 16 MHz | Clock Divide Ratio 0 0000 128 1 98 ua 1596 1 0001 256 is 192 is 2072 2 0010 512 1s 384 fs B14 3 oom 1.924 me 788 fs 12288 4.0100 2.048 me 1.536 ms 24576 5 0101 4.096 ms 3.072 ms 49152 6 0110 8.192 me 6144 me 98204 7 ont 16.384 ms 12.288 ms 196608 8 1000 22.768 me 24576 me 200216 9 1001 5'596 ms 49.152 ms 796432 A 1010 131.072 ms 98.304 ms 1572064 8 tor 262.144 ms 196.608 ms 3145728 1100 524.268 ms 209.216 me 6201456 D108 1.049 see 786.432 ms 12582812 E1110 2007 soe 1579 900 25105824 Fatt 4.194 see 31146 see 50391648 80€521/800321/80C541 87

TF the Programmed Time bits are read while the WOT is Gisabled, they will show the last value written. Once the WOT is enabled, these bits will show the programmed time of the <> WOT and cannot be modified. ase Bit 4 <7 Reserved. Will return an unidentified value when read. *E ~ Bit 5—Timer Verification (TV) rrouseroAoe This bit reflects Bit 11 of the internal counter within the Watchdog Timer. it will toggle every 4.096 ms at 12 MHz. This | “ bit is Read-only. = Bit 6 i O18 eevesoeecoeed : Reserved. Will return an unidentified value when read. [eats] | | Bit 7—Reset Cause (RC) | The Reset Cause bit indicates the cause of the last reset of | the 80C521. If a Power-On or Hardware Reset occurs, the bit rm : is set to a 0 by the reset circuitry. I a Watchdog or Software aes Reset occurs, the bitis set to a 1 by the reset circulty, Like the l : Programmed Time bits, this bit may not be modified once the | : WOT is enabled. Writing this bit does not affect any chip L : function, a Watchdog Key (WDK)— Address: AAH ‘4 . This register controls the enabling and clearing of the Watch- a] dog Timer. The writing of an ASH followed by the writing of a ens SAH to this register enables the WOT to begin incrementing 000220 It is not @ requirement that the writes be on consecutive instructions, thus interrupts do not have to be disabled. Once Figure 1. WOT Keyed Sequence Flowchart Wingo th came sone The cleerrn cuevaion causes The Keyed Sequence isin Stage t after al forms of reset, or the present count of the WOT to be cleared, but dose rot st following any Watchdog enable or clear operation. In Stage 1 the Wor tow radian ‘°P all values written to the WDK register are ignored except ASH. in tncremen in. ‘An ASH causes the Keyed Sequence to enter Stage 2. This is a Write-only rogster. Read operations are not defined Greg sta ge 2 is entered, the next write to the WOK-register and will not affect the WOT circuitry, prompts one of the foliowing actions: (1) If the next write is (uss) (ss) again an ASH, the Keyed Sequence remains in Stage 2; (2) If CLYETTETTIqT 4 the next write is a SAH, the WOT is enabled/cleared, and the ney eS Keyed Sequence reenters Stage 1; or, (2) If the next write is any other value, a Software Reset via the WOT is generated, The enabling/clearing operation of the Watchdog Timer is accomplished by writing a keyed sequence of values to the comple of Write Operations to WOK: WOK register. The Ke i sed of two wages ‘noe Figure ies Sequence is compo 1st 2nd Action Taken After Second Write 11 18 No action taken, Keyed Sequence sill in Stage 1 AS AS Keyed Sequence enters Stage 2 and remains there ‘AS 5A WOT is enabled/cleared, Sequence reonters Stage 1 AS _11__ Software Reset occurs via the WOT The two-stage feature, together with the Software Reset, greatly reduces the chance of an instruction sequence acci- dentally clearing the Watchdog Timer. Furthermore, while still allowing a Software Reset to be initiated, the two-stage feature reduces the chance of unintentionally generating a Software Feeset. 88 80C521/80C321/80C541

Software Reset two data pointers is currently selected. Three examples are as follows: A Software Reset may be accomplished through the Watch- dog Timer. If an ASH is written to the Watchdog Key (WDK) MOV DPH|R3__;Move the contents of Register 9 into register, followed by the write of a value other than ASH or OPH SAH, a Software Reset will be generated. This software- MOV A.OPL1 _;Movo the contents of DPL1 into the generated Watchdog Reset occurs regardless of whether or “poe ‘ ot the Watchdog Timer was previously enabled PUSH DPH1 —;Push the contents of DPH1 onto the After the second value is written to the WOK register, program stack execution continues for one machine cycle before the resot ‘operation begins. During S2P1 and S2P2 of this last machine The Dual Data Pointer structure saves both time and code cycle, the RST pin is pulled High (see Figure 6). The reset space by eliminating the need for frequent loading and ‘operation lasts two machine cycles and does not modify the unloading of a single data pointer. For instance, block move contents of the internal RAM. operations in external memory can be more efficiently imple- ‘The Software Reset is functionally equivalent to the Watchdog _-« mented by using DPTRO as the source address, and OPTA1 Reset. For instance, the Reset Cause bit in WS will be set to 8 the destination address. The Dual Data Pointer structure 1, indicating a Watchdog Reset occurred (see the Watchdog ‘enhances this operation considerably. Timer section for more details). Data Pointer Selection (DPS) — Address: 86H The following code may be used to generate a Software This register determines which of the two data pointers is Reset. currently selected. Once a data pointer is selected, the six MOV WDK,#ASH ; Write AS (Hex) to WOK PTR instructions refer only and always to that data pointer until another data pointer is selected. Upon reset, the default MOV WOK, # 11H; Write 11 (Hex) to WDK data pointer (OPTRO) will be selected, thus retaining compati- Software Reset generated via WOT bility with existing 8051-family devices. The switch between data pointers may be accomplished with a single cycle Dual Data Pointers instruction (such as: INC DPS or MOV DPS,A). The default ‘Tho Dual Data Pointer structure is the means by which the value at reset = OOH. This is a Read/Write register. 80C521 family may specify the address of an external Data Memory location. The Dual Data Pointer structure consists of ase) ase) two 16-bit registers that address external memory, and a LoTofolofof] of o Ise] single 8-bit register that allows the program code to selectively 765 a8 ‘switch between them. They are located in the Special Func- tion Register space at the following addresses: Bit 0— Select 0 (SELO) If this bit is 0, the original data pointer, DPTRO, is selected. If 82H Data Pointer Low OP) ) point 0 (OPTRO) this bit is 1, OPTRI is selected. This bit may be written by 83H Data Pointer High 40H) software at any time. When read, its current value is prosented. 64H Data Pointer Low 1 DPL1) esi Data igh 9 “pm Data Pointer + (OPTR1) Bits 7-1 0H Data Polar Beeston 08) Reserved. Will return 0 when read. Data Pointer 0 (OPTRO) is the original data pointer on the Data Pointer Low (DPL)— Address: 82H standard 80C51 (formerly referred to as DPTR). Data Pointer1 PL. is a Read/Write register thet contains the low byte of (OPTR1) is an additional data pointer with identical character- Data Pointer 0. it may be accessed at any time with an istics. Instructions that refer to DPTR refer to the data pointer _instruction that specifies a direct byte as a source of destina- that is currently selected in the Data Pointer Selection (DPS) _ tion. However, SELO in the DPS register must be set to 0 register. The six instructions that reference DPTR are as before any of the six explicit DPTR instructions will access this {ollows: register. The default at reset = OOH. INC DPTR :Increments the data pointer by 1 (use) (ss) #dataté 16-bit constant ee ae MOVC A, ;Move code byte relative to DPTR @A+DPTR to Ace Data Pointer High (OPH) — Address: 83H MOVX A, @DPTR ;Move external RAM (16-bit DPH is a Read/Write rogister that contains the high byte of address) to Acc Data Pointer 0. It may be accessed at any time with an MOVX @DPTR, A ;Move Acc to external RAM instruction that specifies a direct byte as a source or destina- (16-bit address) tion. However, SELO in the DPS register must be set to 0 UMP @A+DPTR Jump indirect relative to DPTR before any of the six explicit DPTR instructions will access this register. The default at reset = OOH. itis also possible to access each data pointer on a byte-by- (use) (ss) byte basis by specifying its low or high byte in an instruction that aocesses the Special Function Registers. hese nstwc- = L_[ [T_T TT TJ] ) tions can be executed at any time regardless of which of the 7 6 6 #4 8 @ 1 0 80C521/80C321/80C541 8-9

TABLE 1. PCON (Power Control Register) Power-Down Mode [PL [FOONe [igermase os Serrg meet | released until the oscillator has restarted and stabilized. preserved in its entirety: the Stack Pointer, Program Counter, in Figure 5. Activation of any enabled interrupt will cause PCON.0 tobe © Figure 5. PCON.O can also set or clear one or both flag bits. When idle PY Pa. Hardware Reset. ‘external memory access. than a reset, the Watchdog Timer will continue to run. the user's circuit does not force the input line High. TABLE 2. STATUS OF THE EXTERNAL PINS DURING IDLE AND POWER-DOWN MODES

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Voltage on Any Temperature (TA)..sesssessesseeessnnsssssssesseeO 10 +70°C Power Dissipation ...ccseccsesseresssneeeemsssseeeesnsB00 mW Industrial (1) Devices Stresses above those listed under ABSOLUTE MAXIMUM Sony vonage Wigs oe pase tes RATINGS may cause permanent davice failure. Functionality Ground (Vseh (OO) oovevsenererorn Ov ator these linits is not implied. Exposure 10 absolute eesssseneesunnssennnnneeusasnnnnessseess maximum ratings for extended periods may affect device Operating ranges define those limits between which the reliability. functionality of the device is guaranteed. DC CHARACTERISTICS over operating range Description Test Conditions [Vu [input Low Vortage (Except EA) wT nos Poe voo=o1 Tv [Vix | trput Low Votiage (EA) 0s P02 voo-08 |v | [Vin | taput High Votage (Except xTAL,, AST) [02 Voss] Voo+os TV [Vier [Input High Vottage oxtaby AS) Tar voc “T vocvos TV | [Vou | Output tow Vonage (Pons 12.9) tut ma Not TT oas | [Vou | Output tow Vottage (Pon ALE. PEER) o=a2ma Wow y [as [lon==60 wA Voom svetox [24 [|v Vou ‘Output High Voltage (Ports 1, 2, 3) [Tons =25 wk 078 Voo [dT [Ron==t0 nA voc | [low==800 WA Voces verox [ae [Tv Ee ee [ign ==80 uA Note 2) [0 voc [Tv [te | toaical Trp Curent (Pons 9.2.9) vmnoasy soa) [i | topical 1 to © Transiton Curent Pons 1.23) vwn2v eso ua [tu input Leakage Gurent Por 0, EA) O45 <Wn<Voc Tt ua [rast | Reset Putéown Resistor oso [Gio] Pin Copactiance eat Fron =t we Tawasre [oT oF | [ipo] PoworDown Curent TT Voo=2 to Sv mote gy so ua awrite dee oe [Fea vec | asv [sv Tssv [sv [sv [sev |

3.5 MHz 10 15 3

8.0 MHz 18 25 5

12 MHz 2 35 6

46 MHz 22 45 85

Notes: 1. Capacitive loading on ports may cause spurious noise pulses to be superimposed on the Vou of ALE and other ports. The noise is due to external bus capacitance discharging into the port pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may exceed (08 V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt- Trigger STROBE input. This note pertains to dual-line packages only. The additional Vcc and Vsg connections on the PLCC package from AMD removes this design consideration. 2. Capacitive loading on ports may cause the Vo} on ALE and PSEN to momentarily fail below the 0.9 Vcc specification when the address bits are stabilizing. This note pertains to dual-in-line packages only. The additional Vcc and Vsg connections on the PLCC package from AMD remove this design consideration. 3. Power-Down icc is measured with all output pins disconnected: EA = Port 0 = Vcc; XTAL2 NC; RST = Vgs 4. loc is measured with all output pins disconnected; XTAL; driven with TCLCH, TCHCL = 5 ns, Vi. = Vgs +0.5 V, Vid = Voo-0.5 V; XTAL2 NC; EA= RST = Port 0= Voc. Typical values are approximately 50% lower. icc would be slightly higher if @ crystal oscillator was used. 5. Idle icc is measured with all output pins disconnected; XTAL driven with TCLCH, TCHCL = 5 ns, Vi, = Vss + 0.5 V, Vin = Voc -0.5 V; XTAL2 NC; Port 0= Vcc; EA= AST = Vss, and the Watchdog Timer disabled. 80C521/80C321/80C541 8-13

SWITCHING CHARACTERISTICS over operating range (C. for Port 0, ALE and PSEN Outputs = 100 pF; Cy for All Other Outputs = 80 pF) Per] oem Ee]. Description [wn [max [ win, [wax [wn | mex. _| [wrest onctar Fogueney Tr [rent Pa Pie wean sae ref [ravi [acs Vaid to WE tow 8 peut | [Tuiax [Aarons Holt Ater AE Low ar [as | tc -as |) [rut TALE tow to Vaid owe |e aren 00] [Trae tow to PEW ow | ee [eur PSEN Pulse wien a [fas arccc-as | [| A == A a | tex [np nee Rat ater BER ef rena] [taverns 10 Vat natin [as [ata Jr = 08 | re | [“TPLAz | PREN Low wo Adress Ft [J | 0 |] 9 [“rRte RD Pate wean as as oreo] [wows [WR Pate wet ar [aan Foren cn=100 ro | [“Teioy [RD tow ie vako Dawn eres] oe] [anon [ont Hoe Aner RB oe A CP SS [mtv [Ate tow o vad owt or Fort 0] | tavov [across to Vas Data in [| a9 [ses] Tororo =08 | re | ["Tutwt [ALE tow to BO or WA tow | var] ass | ao | ooo | eu -@0 | avout +80-| re | [ravens vate to Read or wile Low [rao || a0a | reucr-1e0] [re [Town [oats vaid to WA tran [2 | | |] rac | [1] [rawr [Vat aia to Wete Won tar} aes | TY rrect reo] [re | a OS | rataz [RD tow w Assos Ro or [wt or Wi we Ate Wags ae eee ee 8-14 80C521/80C321/80C541

a ws su ——_ PEN rome ote, Pa DIX er) a External Program Memory Read Cycle ss Ms |) PSEN a nf ie) a TAVLL- TRHOZ re | mole porto enon & ev oo XX) { omn DY a vm External Data Memory Read Cycle 80C521/80C321/80C541 8-15

SWITCHING WAVEFORMS (continued) Twi AL PSER Wa wax TAVL Tavwi ———|4L roe etki [ener XX) wrozosse External Data Memory Write Cycle wsmucron | 0 foo foe f 3 fo 4 fos foe for foe | “UNAS LL re gS a en BS pe ee DE pe De pe Tov fe—el feresax | (OUTPUT DATA CED GED GD GED GD GCE, + #, were fo sae ray be reo WeUT Dara, C= >) DT ED CD) GD TD ED LD GD LS GD) t 7 ser cuean m wroa0es1 Shift Register Timing Waveforms 8-16 80C521/80C321/80C541

Description Min. TELL Csattor Feaverey a Tow [righ time | TOL [low tine as TeLcH a TCHOL [Fai times Noo-88 == EBT TES Tox — beh to. ToKe. Toc. weo20911 External Clock Drive Waveform SERIAL PORT TIMING—SHIFT REGISTER MODE Test Conditions: Ta = 0°C to 70°C; Veg =5 V +10%; Vsg = 0 V; Load Capacitance = 80 pF barameter Parameter [emis coe. | venvie once Symbol Deserption [win [wax [win] woe. THUX Serial Pon Clock Gycle Time [750] erate PSSSS~dCs Output Bala Sotip to Gock Aang Ege | «62 | [roveuct-ra] «dns | Output Oata Hols Afr Cock sng Edoe [8 | [atcuct-t7 [ie input Baia Hod Aer Gock Risng Gage To [| 0 | | 5 _| Glock Rising Edge to input Data vaid [| 4e2 | Tvorouct 1a] ns AC Testing Voc-08: OE VEE+OS Vioan +0 V Yeray Yioao ™s one 04s Vv. 2 ogo Yioan-01 V Voto V ‘wr020901 wFo20941 AC inputs dutig testing aro deven at Voc-05 for a loge tand 045 V for a} | For nming purposes a port pin no longer floating when a 100 mv change {ogi 6: Timing measurements ae made at Viv mn. for’ loge 1 and Vi. from load voltage occura. and Begs to oat when a 100 mv change tom max fora loge 0. the loaded Vow Vox low Sou oy # #20 mA Input/Output Waveform Float Waveform 80C521/80C321/80C541 8-17

INTERNAL | STATE 4 | STATE 5| STATE s| STATE ‘| STATE 2 STATE 3 | STATE ‘| STATE 5| Lock prleztprt pet prt pet pl pel ert pel est eel ert eel er | pe ae DULL ae a , en rr: en ere; Me THESE SIGNALS ARE NOT ACTIVATED DURING THE EXTERNAL PROGRAM MEMORY FETCH SN OF A MOVX INSTRUCTION rm SE p0-A0y ef L_fra oor} PrL_frorl fomL_froor] SAWeLeD SAMPLED SAMPLED FLoat = be Ftc be— toe Ce es READ CYOLE PCL OUT ('S PROGRAM MEMORY (S EXTERNAL) eon fox ‘AD -AD7 Woot re L_ WAMTE cyoLE wa JP our even F Procram MEMORY IS TERNAL) /#-—— ara ovr : POL OUT (F PROGRAM ee Se pees andi PORT OPERATION MOV PORT, SAC CCAS 01 Mov DEST, P1 (NCLUDES INTO, INT, TO. TH) SERIAL PORT SHET Lock ,_- SP PIN SAWPLED PN SAMPLED “] Txo (MODE 0) RXD SAMPLED XD SAMPLED wro20020 This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges fam 25 0125 ns, Ths propagation Slay i dependent on vaables such a tomperatre andi acing, Propagation als varies {rom output to output and component to component. Typically though (Ta = 25°C, fully loaded), RD and WA propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specications. 8-18 80C521/80C321/80C541

TABLE 3, 80C521/80C321/80C541 INSTRUCTION SET Instructions That Affect Flag Setting” Interrupt Response Time: To finish execution of current instruction, respond to the interrupt request and push the PC; Instruction Flag Instruction Flag to vector to the first instruction of the interrupt service program c ov ac c ov ac requires 38 to 81 oscillator periods (2.25 to 5.25 ys at 16 ‘ADD x xX xX CIRC ° MHz). ‘DDG x xX xX CALC x suBB xX X X ANG bit xX MUL o x ANL G/bit X ov o x ORL C, bit xX DA x ORL Cibit x “Note that operations on SFR byte address DOH or bit RRC x MOV C, bit x ‘addresses DO - D7H (i.e., the PSW or bits in the PSW) will also RLC x CINE x affect flag settings. seTBC Ot DATA TRANSFER LOGIC (Continued) [Woomonic __[Beseriton ___—_—([Bvte|ye|wnamentc [Description [yi ve| Mov ARn Move register to Accumulator 1 [1 [Ant drect data | AND immediate data to direct byte 2 MOV Advect | Move drect bye to Accumuator 2] 1 [oR Aan ‘OR regater to Accumulator + MOY A@Ri Move Indirect RAM to Accumulator 4 | 1 [ORL Aarect | OF direct te to Accumator 1 Mov Avaata — | Move immediate cata to Accumuator | 2 | 1 | ORL A@RL OR Indrect RAM to. Accumulator 1 Mov RRA Move Accumulator 10 register 4 | 1 [ORL Reda | OF immecite deta to Accumustor 1 MOV Andeoct | Move drect byle to regater 2 | 2 | ORL Grocta’ | OR Accumsstor to drect byte 1 MOV Rnedata | Move immediate data to register 2 | 4 [ORL drectedeta | OR immedi data to drect bre 2 MOV drectA | Move Accumulator to direct byte 2 | 1 |x Ann xouswe-OR regitor to Accumulator 5 MOV drecthin | Move repair to dract byte 2 | 2 | XRL Acroct —_ | Exciuswe-OR drect byte to Accumustor 1 MOV rectdrect | Move drect bye to det byte a | 2 |x Aen Exclunve-OR indeect RAM to : MOV drect@hi_ | Move indrect RAM to direct byte 2|2 ‘ccumator MOV drect #cata | Move inmedato data to drect bye | 3 | 2 | XRL Addata | Exciusvo-OR immecito data to ' Mov @RA Move Accumulator 10 indirect RAM aa ‘Accumulator MOV @ALarect_ | Mode drect byte to indirect RAM. 2 | 2 | xa recta | Exchuswo-OR Accumulator to direct byte 1 MOV @AL@daia | Move immodate cata to indrect RAM | 2 | 1 | XL drectedate | Exclusve-OR immediate data to drect 2 MOV DPTRLecalat6 | Move 1EDR constant to Data Ponter | 3 | 2 | GA A Gear Accumulator 5 MOVE A@As OPTA. | Move Code byte rlatve to OPTR to | 1 | 2 | CPL A ‘Complement Accumistor 1 ‘Acoumator ROA Rotate Accumulator Lat 4 MOV A@A+PC | Move Code byte relatve to PC to 1 | 2 [Rc A Rotate Accumulator Lat though Cary 5 ‘Accumualor Fig Move A@RI Move External RAM (@t address) to | 1 | 2 [AR A Rotate Accumulator Right : ‘Accumulator RRC A Rolale Accumulator Fight tough Cary ‘ Movx A@OPTR — | Move External RAM (16-bit adcress) to | 1 | 2 Fag ‘Accumuiator SWAP A Exchange neblos win the 1 MOVK GRA Move Accumulator to External RAM | 1 | 2 ‘Accumulator wove @oetna —|WNove curator Exeral RAM | to 2 pus (96 aden) ARITHMETIC ace |Site ew me | | + [Memon [onetnion ve | POP dvect op direct byte off of stack 2/2 ten Byte| Cye XCH ARN Exchange regator with Accumulator | 1 | m 7 XA | Beran pa ah catty | | 1 428 Ana, | Aa en aocumdt } XCH AGRI ne RAM with 1 | 7 [ano A@AI ‘Add indirect RAM to Accumulator 1 row non [Tatars nae nan sn | 1 | + ]3, Agate [Aug nmaaan get tect | & cle wih We LEN. ADOC Adroct | Add drect byte to Accumuator win | 2 Cary Flag BOOLEAN VARIABLE MANIPULATION nove Na Moma Namco Fase | ADOC Aedea — | Add immediate Frag 10 [memone [Owen vee Same serene | + SUB ARN Subirect regater from Accumuiator wis | 1 anc ur cary Sorrow GA bt Gar dee Adrest | Seow dec vm oA, ae ect sues Sibeact ect be tom Accumulator | 2 SETB bt Set dre bit sus8 Agri Subtract intact RAM from Accumusator| 1 wo oC ‘Complement Cary Flag sein Borrow cet bet Complement direct bit SUBB Adata | Subtract immodiato data trom 2 ANC Got AND deect bt Yo Carry Flag fecumulator wit Borow ANC Gti ‘AND complement of aeect Bit 10 Cary NCA tnoremect Accumiator : ont Ct (OR drect bt to Cary Flag INC Rn Increment rogiior 1 ORL Gyo ‘OR complement of drect bt to Cary INC dract Increment rect byte 2 Mov Ct Move erect Bit 16 Cary Flag INC GR Increment indvect RAM + Mov bite Move Cary flag to drect bt cee Decrement Accumulator 1 DEC An Decrement roger 1 DEC drect Decrement direct byte 2 a SE INC DPTR Increment Oeta Poinor 1 [penwin —owlon |S” [Scans |} [mnemonic | Jeveleye [wt S| orate : ML ARn OND rageter ‘ao cA OA Decimal Adjust Accumulator + BNL Aeroct | AND direct byte to Acoumator AL Agr [AND indirect RAM to Accumulator ANLAvedata | AND immedato data to Accumulator ANL directa’ | AND Accumulator to drect byte 90C521/80C321/80C541 8-19

[OTHER | CONTROL TRANSFER (SUBROUTINE) [Mnemonic [Description —JBite[ Gye [Mnemonic [Description [Bie eye jer wore Tr] vanes ese LCALL addrt6 Long Subroutine Call CONTROL TRANSFER (BRANCH) RET Retum trom Subroutine Call . REN tum from Interupt Call jMnemonie [Deeerption [Byte] ye ‘Addressing Modes: sume asdrtt | Absolste Jump ; LUMP addrié ‘Long Jump. Rn -Working register RO-R7 of the currently selected ‘SUMP rel ‘Short Jump (relative addr) Register bank. JMP ~~ @A+DPTR | Jump indirect relative to the OPTR direct 128 internal RAM locations, any /O port, control, or Zl ‘Jump it Accumulator is z6r0 ‘Special Function Registers. INZ rol ‘Jump if Accumulator is not zero @Ri Indirect internal RAM location addressed by register he rel Jump ‘ Carry B20 is sot RO or Ai. Hey Sir I any le not set ‘#data_—_-8-bit constant included in instruction. 8 bitrel Jump relative if direct bit is set 7 Ne ae Sune relate Oeeet tk ot sat #datat6 16-bit constant included as bytes 2 and 3 of JBC bitrel Jump relative if direct bit is set, instruction. 7 then clear bit bit 128 software flags, any 1/O pin, control, or status bit. CJNE Adirect,ret_ | Compare direct byte to 7 ‘Accumulator and Jump if not Equal Notes on Program Addressing Modes: INE A.tdatayel | Compare immediate to Accum NE Atomarel | Compere immediate to ‘ator adde16 _-Destination address for LCALL and LUMP may be CINE Fin, #catarel | Compare immediate to reg and ‘anywhere within the 64-kilobyte program memory Jump if not Equal address space. CINE @Fi,aatasl | Compare immediate to indirect ‘addr ~Destination address for ACALL and AJMP will be RAM and Jump if not Equal within the same 2-kilobyte page of program memory QUNZ Rn,ret Decrement register and Jump if not ‘as the first byte of the following instruction. 20r0 rel -SJMP and all conditional jumps include as 8-bit OWNZ droctrel | Decrement erect byte and Jump it offset by Range is +127, -128 bytes relative to first byte of the following instruction. TABLE 4, INSTRUCTION OPCODES IN HEXADECIMAL ORDER Hex Code Bytes Mnemonic Operands Hex Code Bytes Mnemonic Operands 00 1 NOP 20 1 aD ARI 1 2 AIMP Code ace 2a : s00 Ane 02 3 LMP Code addr 2B 1 ADD ARS 03 1 aR x ze : a0 Ane o : Ine nN Fy 4 20D ARS 05 2 INC Data ace 2e 1 md Ane 6 : Ne ero Fa : ADD AR? ° 1 Inc ent 30 3 ine Bi ade, code aad 28 1 NC fo EY 2 ACALL Coda adr 09 1 ING Rt Ea i fet on 1 NG Re a ; Fic A oe 1 ine fe Ed 2 nope Ateta oc : Ine Re a 2 ADOC Aidala adr 00 4 tne RS 2 i A00e = Ren oe ; ING Re Ed : ove Aga oF 1 ING Rr 38 : o0e ARO 10 a see Bi ade; code adie 39 : Apoc At it 2 ACALL Code aser EN 1 aooc Ane iz a (cat Gogo ass EY) 1 Doc ARS 3 ‘ Fre ES : aoc Ane ia i be Ok ap i apo ARS 5 2 bec Data ace a ‘ noo Ane 8 i bec ero oF : a00c AR? 7 1 Dee srt * 2 ie Code addr i 1 DEG Re Py 2 Amp Code aaa : occ At Pa 2 ont Data adc 1A i Be Re 8 3 ont Data scr # data 8 1 Sec Re a 2 ORL Reedata ie : bee Ae 5 2 ORL Aata ace 1 1 Ces Pd : oat eno ie 1 Dec Re 2 : OL gat iF 1 oe OP Pi : oat ano 20 3 Fr Bit ade,code ack Pr ; ORL AR 2 2 Aime Gado ar aA i Ont Ane 2 : fev 3 4 OR ARS 2 1 AL A Pd 1 OR Ane Ea 2 ADD Atdate Py 1 ORL ARS 2 2 300 Ada adr “e : ont Ane Fa i cr) Pra : Sat any Fd 1 a0 emt 50 2 snc Cove acer 3 i noo Amo 5 2 ACALL Code adr 8-20 800521/800321/800541

Hex Code Bytes: Mnemonic Operands Hex Code Bytes Mnemonic Operands: 82 2 ANL Data addr A aA 2 Mov Re.data ager 53 3 ANC Data add # data a8 2 Mov S.cata 00" 54 2 NL Aut cata a 2 Mov Ra‘data dor 5 2 ANC ata adr 0 2 Mov RS.cata ador 56 1 ANC Rano i 2 Mov R6vsata ador 7 1 ANE Aga a 2 Mov RY data ador 58 1 ANC ARO 30 2 ANC C/o acer 59 1 ANC ARI a 2 ACALL Code acer eA 1 ANC ARR a2 2 CPL Bit adar 5B 4 ANC ARS 33 1 PL c 5c 1 ANC ARG 84 3 GiNe A,#datacode addr 5D 1 ANC ARS 35 3 GINE data. ar. code adr se 1 ANE RAG 36 3 Gane @RO,#data code 5 1 ANE aR? aso 60 2 wz Code ader 27 3 cane GR, #cata.code 6 2 Rump Cove adr ade & 2 xRL Data ada A 86 3 CINE FRO. #data,code adr 63 3 xAL Data der # data Ey 3 GINE —-RY-#atacoce acer 6 2 xRL Avwoata BA 3 GINE RRL #dalacoge esr 6 2 xAL Adata adcr 88 3 GINE RS. #dalacove act 6 1 xAL R@RO 80 3 GINE Ra. edatacoge csr e + xAL Rar 60 3 GINE RS, #data.coge adr 6 1 xAL ARO Be a GINE AB edatacoge act 6 : xAL ARI BF 3 GINE RT. #datacode acr eA 1 xAL ARe co 2 PUSH Data adcr 63 1 xAL ARS C1 2 IMP Code adr 6c 3 xAL ARA ce 2 cir Bit acer 60 1 xRL ARS 3 1 LR ¢ ee 1 xAL ARG c 1 swap A ca 1 xRL ART cs 2 xCH ‘Adata addr 7 2 INZ Code acct ce 1 xCH A@RO nm 2 ACALL Code addr cr 1 XCH AGRI ) 2 OAL Coot aaae ce 1 xCH ARO 3B 1 IMP @A+ PTR co 1 xu ARI 7 2 ov At cata cA 1 xcH Ape 75 3 Mov Data adr, # data cs 1 xCH ARS % 2 MoV @RO.# dala co 1 xcH Ana iad 2 Mov GA #ceta co 1 xcH ARS 73 2 MOV FO, # data ce 1 xcH ARS i 2 Mov Riveaale oF 1 xCH NG 7A 2 Mov R2\\eoate 00 2 POP Data adr 78 2 Mov 3, #ata 1 2 ACALL Code adr 76 2 MoV Rae data 02 2 SETS Bit adr 79 2 Mov BS, #caia 03 4 SETS C te 2 Mov 6, eal De 1 DA rf | or 2 Mov R7.edata 35 3 DUNZ Data ader.code ecdr 80 2 SUMP Code adr 08 1 XCHD AGRO 8 2 AIMP Code adr o7 1 XCHD = AGRI 8 2 ANL Git adr 8 2 DINZ ———ROcade aadr 8 1 Move AGA +PC O8 2 DINZ ——-At.code adr be 3 ow 48 DA 2 DUNZ ——-R2.coge acer 85 3 Mov Data adr data addr De 2 DINZ ——-AS.code ado 88 2 Mov Data ado, @ RO Dc 2 DUNZ ——-Ra.code agar 87 2 Mov Data ad. @ Rt 0 2 DINZ ——-AB.code aor 88 2 Mov Data addr RO DE 2 DUNZ ——“ABcode ador 89 2 Mov Data ado oF 2 DUNZ ——_—7-coge ager 8A 2 Mov Data ada Re £0 1 MOvx -&,@OPTR 8 2 Mov Data ade isi 2 AIMP Code addr ec 2 Mov Data ager Aa 2 1 Movx —-K@RO 8 2 Mov Data adérA5 5 1 MOvX = -AL@RI 8 2 Mov Data acer RS EA 1 CLR N oF 2 Mov Data addeA7 55 2 Mov A.data eddr 80 3 Mov OPTR,#cata 56 5 Mov Reno 2 2 ACALL Code ader = 1 Mov Am 92 2 mov Bit agar 56 3 Mov ARO 93 3 MOVG = A@A +DPTR =9 3 Mov aR 9 2 SUBS Avecala EA 1 Mov ape 5 2 SUBB © Aldala er £9 1 Mov ARS 98 5 SUBS A@RO EC 1 Mov ana 7 1 SuB8 ARI £0 ‘ Mov ARS 28 1 uss. ARO ee 1 Mov ARS 9 1 sus ART EF 1 Mov aR? oA 1 suas AR Fo 1 MOVX —@DPTRA 98 i susaARO Ft 2 ACALL Code ar fa 1 sus ARA F2 1 MOVX = @ROA ry 1 sus ARS Fa 3 MOVX = @RLA 9 + suss ARG Fa 1 cL rN oF 3 suas. AR? 55 2 Mov Data agara 40 2 One Cot ager 6 1 Mov @AOA at 2 AMP Code adr a 1 Mov RIVA a2 2 Nov Coat aaae Fa 1 Mov ROA cy 1 INC OPTR 79 1 Mov RIA a 1 MUL a8 FA 1 Mov ROA as Reserves FB 5 Mov ROA a8 2 Mov @Ro.cata adce FC 1 Mov Raa "7 2 Mov GAi sate ace FO 3 Mov REA | ag 2 MOV Rosata dar FE 3 Mov REA

2 Mov Rivdata adar FF 1 Mov RTA

ADVANCED MICRO DEVICES 26 D mm@ 0257525 0032426 4 Mm AMD CHAPTER 11 T90-20 Pa Package Outlines an ees PHYSICAL DIMENSIONS* 7 Plastic Dual-In-Line Package (PD) PD 040 2.040 ‘ 2080 po 580 CTE ak ‘a rib eos 065 10 580 015 620 060 ALL 008 yo ee | + ~” vio 023 . PID# 068208 * For reference only. . NOTE: Package dimensions are given In inches. To convert to millimeters, multiply by 25.4, eee SS EE 14-1 |

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ADVANCED MICRO DEVICES | 28E D Mm@ 0257525 0032428 4 mm AND CHAPTER 11 Package Outlines Plastic Leaded Chip Carriers (PL) 20 PL 044 1-90" a Po 050 048 REF. 4 —| : 009 . > ie DIS 025 OOOO MMO oon ay 045 | a & 5 =e TYP. C] im == 630 885 cj im [_ == 500 895 i 5 . 926 +}, REF. so CF = a) Ee | cs rn a 5 — cS = P= 1.013 iam o fo 02 qj 5 be I A —— | (TR OUOOCUUU0Uo SH 009

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