N80C186-16

80C188 AMD | Alldatasheet

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| PRELIMINARY | Pa | 80C186/80C188 Advanced . . — Micro CMOS High-Integration 16-Bit Microprocessors Devices DISTINCTIVE CHARACTERISTICS @ Operation Modes Include —System-level testing support (high-impedance p test mode) Enhanced mode with Available in 25-MHz, 20-MHz, 16-MHz, 12.5-MH, 7 | , 12.1 iz, + DRAM Refresh Control Unit and 10-Mttz versions * Power-save mode 1 Direct addressing capability to 1-Mbyte of eos pao 88 pin-for-pin rep! memory and 64-Kbyte /O . pin-for-pin replacement for non-numerics applications : ed vetoly object on ibte with all Integrated Feature Set ompletely object code compatible with al 9 existing 8086/8088 software. Has ten additional —Enhanced 80C86/C88 CPU instructions over 8086/8088. —Clock generator @ Complete system development —Two independent DMA channels —There are many vendors making support tools —Programmable interrupt controller for the 80C186/C188. Software tools for the “4 NMOS 80186/80188 can be used for the —Three programmable 16-bit timers 80C186/C'188 as can the NMOS emulators ~—Dynamic RAM refresh control unit ® Available in iyi memory and peripheral chip —68-Pin Plastic Leaded Chip Carrier (PLCC) —Programmable wait-state generator —80-Pin Thin Quad Flat Pack (TOFP) —Local bus controtier —80-Pin Plastic Quad Flat Pack (PQFP) + In Trimmed/Formed Configuration —Power-save mode GENERAL DESCRIPTION The 80C186/C188 is a CMOS _high-integration (except for 8087 applications). The Enhanced mode of microprocessor. It has features that are new to the operation allows the full feature set of the 80C186/C188. 80186/80188 Family, which include a DRAM refresh _to be used. The 80C186/ 80C 188 is upward compatible control unit, and power-save mode. When used in with 8086 and 8088 software and fully compatible with “compatible” mode, the 80C186/C188 is 100% 80186 and 80188 software. i pin-for-pin compatible with the NMOS 80186/80188 Publican #17907 Rev. B Amendment 10 | Tis denirnrt conan wlomalion on a prodot under devabpmurt at Avance Wise Gevces he Tre wlemaion Tae Dane Juve 1098 ‘eeredichipyou wnat trot AND emt igiiochargtcarincs wk onths pope

INT2/INTAO TMR OUTO TMA OUTt CLKOUT INTVSECECT Jove ino fTMRINt | DRGO — ORQI o INTo y | y | a Programmable DMA Control Timers Unit Vi 0 1 2 oO 4 loc x1 X2 ‘Max Count V7 20-Bit Clock Programmable Register 8 4/4 | _Source Pointers Generator Interrupt Max Count DOB GND Controller Register A Destination Pointers Power Save 16-bit {6-Bit Count Registers Count Registers Control Control Registers Registers Control Registers f Internal Bus | SRDY | Ready Rotresh | | Execution Units | Control POS) nov 4 Logic ealsters | Control {| Registers A a7 16-Bit : Cl General : om Segment Registers | + Chip Select ross) | | Registers Bus Interface ‘ Control Unit 2 DEN Unit ‘ i S-Byte 16-Bit H TOOK Pretetch ALG ' | Queue wt M | HOLD ALE/QSO TEST iy PCS4-PCSO MCS1 HLDA RES RD/GSMD west tes AD15-ADO Reser | WRIQS1 OCS A19/S6-A16/S3 BHE WCS2 2 80C186/80C188 Microprocessors

INT2NTAO MR OUTO TMA OUT! CLKOUT INTISECECT trun ino f TMR INI DRGO = DRQI oi INTO Programmable DMA Control Timers: Unit o 1 2 0 1 V “ Xt Xe Max Count GZ 20-Bit Clock Programmable Register B YA |_Source Pointers Generator Interrupt Max Count 20-Bit GND Controller Register A Destination Pointers Regist i Control Control Count Registers Count Registers { { Internal Bus | ‘SRDY: * Execution Unit § ARDY: x Logic Registers Control 1 | Registers Al nit ' aati 16-Bit ‘ S2-S0 CI] General |! oA Segment Registers | | Chip Select POSS i Ragisters| Bus Interface : Control Unit oe DEI i “Byte Unit : 16-Bit : [OCR Prefetch ‘ i Queue AUT HOLD ALE/QSO TEST MCSO PCS4-PCSO HLDA RES RD/QSMD MCST cs ‘AD7~ADO RESET WRIQS1 mess | UCS A19/S6-A16/S3, FSH WCS2 A15-A8 13088B-001 80C186/80C188 Microprocessors 3

80C186 CONNECTION DIAGRAMS 68-Pin Plastic Leaded Chip Carrier (PL 068) =23 b 22728 E 8288,383 G3 SEf22Beesecgbae See eeER 23x83 BbB SSSSSSSsSSRSS BESS ADI5 Co le 51 F3 HLDA AD? C2 50 9 HOLD ADI4 C3 49 F> SRDY AD6 Ce 4 48 F] COCK ADI3 5 47 FS TEST ADS Co 6 46 3 NMI ADI2 C7 45 3 INTO ADS C8 4423 INT1 Voc =] 9 43 F2 Veo ADI1 CS 10 42 F INT2/NTAO ADS CO 11 41 2 INTS/NTAT AD1O CS 12 40 FTA AD2 CH 13 39 F3 DEN ADS CS 14 38-2 McsO ADI 15 37 3 MST ADs Cc 16 36 F Mcs2 ADo Sj 17 35 5 MCS3 SAFRANRAKRKRARRSHSHBS =SseorPePareeEs SS2295ER2 BB BBS SER Frese Fe Note: Pin One marked for orientation purposes only. 4 80C186/80C188 Microprocessors

800186 CONNECTION DIAGRAMS (continued)

80-Pin Plastic Quad Flat Pack (PQR 80) BESS85S 285858858 SEER ESSEE22EE"E OOO fo BLREKRKREKRKKKLISBESEB Apis CJ te 64 3 ADO no 2 63 > NC Atess SS 3 62 Fo NC mss 4 61 fF DRQo mess TS 60 fF brat Aigss SS & 59 F TMRINO pe 7 58 5 TMRINI wras! Cy 8 57 Fa TMROUTO Ro/GSMD Cy 9 56 FS TMROUTI ALE/QSo CH 10 55 F3 RES we cq 54 > PCSO Vss Tj 12 53 > Vss Vss CS 13 52 FS Pest Nic C4 14 51 > Pcs2 no 3 15 50 -a PCsa xi 4] 16 49 > Pose xo CJ 17 48 [5 PCSEIAT RESET Cj 18 47 [5 PCSBA2 cikour &} 19 46 [> [ts ARDY — 20 45 > US mc 2 44 FNC a 22 43 > NC wo 2 42 > MOSS Neo oy 24 41 ke wes2 RARRRBESSRSBBEBBES : UUUCUUUUCUUToUT ; rLeeer” = Fi zZeo°RR 5 25 ~ 2 Notes: 1. Pin 1 is marked for orientation purposes only. i 2. NC = Not connected. ; 80C186/80C188 Microprocessors 5

80C186 CONNECTION DIAGRAMS (continued) 80-Pin Thin Quad Flat Pack Top View er er =Q Ss22 << erZZ00 Io jm i Be SSEELEW B BEBBBBeE sBEPE PARSE SR ESREREE s BLLKLKTLKKCLGSSSSISIS ADO 4 1° 60-5 MSS ADB CS 2 59-3 MCS2 ADI C3 58 MCS Nic 4 57 MGSO ADs cj 5 56-5 DEN AD2 6 55-5 NC ADIo 7 54 DTA AD3 8 53 > INTSINTATIRG ADIt 9 523 INT2/INTAO Veo E=} 10 51 Voc Veo CS 11 SOE] Veo AD4 Cy 12 49—5 INTISELECT ADI2 13 48 INTO ADS cy 14 47 NMI ADIg C15 46> TEST ADs cj 16 45[= [OCK ADI4 17 44 SRDY Ap? J 18 43> HOLD ADIs 19 425 HLDA Veco 4 20 411 Ves RNRARKARASSSBSBEEBBE ore Sc0uros eerSshebxzNtED ee eee at ee gees a Z<ze & gg « 3 ic Notes: 1.Pin 1 is marked for orientation purposes only. 2. NIC = Not connected. mm 0257525 0049573 198 mt 6 80C186/80C188 Microprocessors

80C186 PIN DESIGNATIONS (sorted by Pin Name) | enna frcperion owe [rome mar Par] Tar] om _| Rrars6 65 28 CONT) nies 88 3 | o.Ha@,Ag) |[wesr [a7] 40 [68 v0, HAC), APU) Ai6is3 6 2 [messes [at [58 JOHAN, RPO) Anis + {a | [woss [as [2 [60 [OHA RFU) Abra a || 7 a A CA ST) AD12 7 | 75 | 13 [possi [at [ae [65 [0, HAD, R(t) Ass wo] 7] 2 [Poseaz | 32 [a7 | 64] 0.HAY) RO) |AD10. 12 | 69 7 ere |PCS4 30 49 66 ADS 14 | 67 5 /PCS3. 29 50 67 oe , % 4 VO, S(L), HA(Z), RZ) Pose 2 5 68 | O. HAC), F(A) |AD6 4 78 16 PCSO. 25 54 71 aoe gyre) i [Rorasmo| ee |e [28 VO AD, RPO) aba n| 70] 2 a A Ave 18 | 68 | 6 reset [67] 18 | 94 | O.HAM) labo 17 | 64 | 7 O, HAW), RZ) lease [er [to | 20 | OHA A) [SRY LS larovfssfeots7| ua (ress | 7 {2 [a [imu le Pes [7 Pos [oman Hane | | 8 | me | ise@ fouxour [se [10 | 36 | OHARA ITranouro Se [pen [oo [oe [36 [0.x ria) || nour, R_[ ona. acy [oRGo, ORGY fra, ref, col7e.7al_ su) ‘foes | oe | 45] 62 (OHA, APU] [ovr | a0 [or | sa [Ona AQ) eo |e | e110 a AN Vee e ] 3 | aus [toa [ot [as | a2 | ORAM), RIO = | % | bo Iwo Pas Por fe | LAE iiwaos | es [8 | 27 lonamam Le TE 25 | 12 | 20,70 [wremras |e [35 | s2 |V0,A€,u, Mano, nral| YS 2 | | a TSINTATAR| 41 [os [ 8 [ro A. Hae. Rails eee [ee [| pes fa feo fo} vorannew tke [se [7 [fo] [rook [a8 [28 | 45 [0 HAz), RPL) ‘On the POFP package, the following pins are N/C (No Connect): 2, 11, 14, 15, 24, 43, 44, 62, and 63. ‘On the TQFP package, the following pins are N/C (No Connect): 4, 25, 35, 55, and 72. Key to Pin Description Codes [1 [inpatGny +d R9 | Hold Reinowiadge: Pin state while proceneor is in the Hold Acknowledge state. [0 foupaony i HAL) = Internal driven to Ver Input or Output (depending on situation) HA(0) = Internally driven to Ves Synchronous: Setup and Hold times must HA(Z) = Internally floated be met for proper operation. ied = Remains active stat S(E) = Edge Sensitive = Retains current state S(L) = Level Sensitive R(x) | Reset: Pin state while the processor's RES A(x) | Asynchronous: Setup and Hold times guarantee line is held Low externally. signal recognition by the processor, R(1) = Internally driven to Voc ae) = Edge Sense Ag = jhternally riven to Vss (L) = Level Sensitive = Internally floatec R(A) = Remains Active R(PU) = Weak internal pull-up MM 0257525 0249574 Ochy R(PD) = Weak internal pull-down 80C186/80C188 Microprocessors 7

80C188 CONNECTION DIAGRAMS 68-Pin Plastic Leaded Chip Carrier (PL 068) a ~2°e E +o © ae KS eeeckeRzfxzgedf6nB8 BSSSSBSsSRSRERREBS ~ o — — Ais te 51 [> HLDA AD7 2 50 > HOLD Al4c4 3 49) SRDY AD6 4 4g - COCK M35 47 = TEST ADS 6 46 FS NMI a2? 45 [5 INTO AD4 8 44 INTI Voc J 9 43 3 Vec All Cy 10 42 5] INT2/INTAO ADs CS 11 41 £2 INTSANTAT Ato G4 12 40-3 OTR AD2 4 13 39 > DEN AICS 14 38 = MCSO AD J 15 a7 CST Ag 16 36 F]) MCS ADO cS 17 35 3 CSS SPRANRARKERIZ HIBS S5SSELEMBSENBBER B23 888 i bag ck Eeae Ooo 22 aa FF Note: Pin One marked for orientation purposes only, mm 0257525 0049575 Tho a 8 80C186/80C188 Microprocessors

80C188 CONNECTION DIAGRAMS (continued) 80-Pin Plastic Quad Flat Pack (PQR 80) me Sn Panto eer Ron x 2E2Z2EVFFEQE222e SBTRERKRERLELKGBSEEB Ais cy te 64 FS] ADO Ne oS 2 6k NC Aisa CS 3 e2 F> NC Ai7is4 C4 61 - DRGo Aig/ss TH 5 60 > prat Aig/s6 Cy 6 59 FQ TMRINO RFSH C7 58 FQ TMRINI Wras! Cj 8 57 FQ TMROUTO RO/QSMD C4 9 56 FQ TMROUT1 ALE/QSO Hj 10 55 FQ RES NC oo 54 F2 PCSO Ves CJ 12 53 Vs Vss Cy 13 52 F] CST Nc oy 14 51 Pcs Ne oS 15 50 Fo POSS x1 oy 16 49 Fo PoSa x2 7 48 FS PCSBIAI RESET CJ 18 47 [so Posera2 CLKOUT C4 19 46 cs ARDY C4 20 45 kK UCS ie 44 NC ago 2 4 NC oo 2 42 | MOSS Nic yj 24 41 ka ese SSRRRSSSBSSSERSS COUTTUTTUoTUoTo <a> & Sere geo a £33 SEbSSRQE 8 B aD >> cere a ge Fa 22 2 2 Zz ! Notes: 1. Pin 1 is marked for orientation purposes only. 2. NC = Not connected. M™ 0257525 OO4FS7G 9T7 80C186/80C188 Microprocessors 9

80C188 CONNECTION DIAGRAMS (continued) 80-Pin Thin Quad Flat Pack Top View Qe 9 e532 zz Zz - a geeez22RSRsRBRRRERRE s SLLRKKRKLKK LK GBS SSESTS ADO 1° 60-3 MCS3 ADs 2 59-5 MCS2 Adi 3 58,5 CST we cy 4 57> MSO ADs co § 56-5 DEN AD2 4 6 55 NC ADIOS 7 54> OTA AD3 CS 8 53 INTSANTAT/IRQ ADI co 9 529 INT2/ANTAG Veco =] 10 515 Veo Voc 4 11 509 Voo AD4 cS 12 49 INTI/SELECT AD12 CH 13 483 INTO ADS I 14 47 NMI AD13 CH 15 46 5 TEST ADs ef 16 45; TooK AD14 I 17 44-5 SRDY AD7 18 43 HOLD ADIs CS 19 425 HLDA Veo =} 20 415 Ves RAKRASKRASRRSSSBSSSESSES ese esczrzesaexthesznbe 22332885 8S 8s ego ggRhs Sb2e? = <<< < Boz = 3 ic Notes: 1.Pin 1 is marked for orientation purposes only. 2. NIC = Not connected. M@™ 0257525 0049577? 633 10 80C186/80C188 Microprocessors

PRELIMINARY amp &A 80C188 PIN DESIGNATIONS (sorted by Pin Name) | snnone rceporar| coe || ronal rceTvarr | Tam | con Ato/s6 5 | 6 | 24 [west [a7 [40 [sa [O, HAH), RIP) Agee fer | a | ae] O-HAGR@ —|f[wese [96 [a1 [se fo, Har, RU) aiess ge | 3 | at [wcss [ss [42 [60 [o, Hatt), RePU) At4 3 | 7} 17 [nmi 4s To a Tse ais 5 | 7 | 15 [possiat [si [ae [65 [ 0, HAO, RIA) Ate 7 | 75 | 13 ©, HAY), Rt) Att 10 71 9 A10 12 | 69 | 7 Besa 30 4 66 a9 14) 67 | § Bose 38 By & Jo, HA(1), R(t) As je} 65 | 2 POST 27 52 69 _ Az 2 | 80 | 18 | v0, sl, HAZ), RZ) || POS 28 54 a) AG 4 | 78 | 16 yasmo| 62 | 9 | 28 |, Ham), RIPU AS 6 76 14 Ad a | 74 | 12 a ES) a3 nn | 70 | 8 RESET (0, HAA) he te leeds [RSH [e476 HAZ), RZ) aeass_[e1_[ 10 [20 | o.HA@, Ro) |{SAOY ee ee ARDY [65_| 20 | 37 | LA) [mest [47 [20 | as [Rey | TMRINT 76 joen [29 [se [56 | OHA@).R@) | aRourTs 87 7% To DRGo, DRAI_f18, 1961, 60)79, 74] Ls) [TMROUTO 56 5 , HAYA), (1) [ovR tao [a7 [sa | oHa@, Re flocs [sa as 620, HAC), (PU) ee Ec 9 33 | 61,10 [Huo st [25 [42 [0 HAA), ROO)! Veo ba 3 | Seo" CC Ce ee oe LAE.) = 73 20 INTVSELECT LAE, L) [wriasi [63 [os [27 [0 Hag), RZ) [INTSANTAVIRG 41 [36 [53 [1/0, A(E, L), HAS), RZ} ° Bu aa SCT 5 cook [as [28 [as [ona RP Xe ss [7s TO) [weso{as_[ 39 [57 | 0, Har), RiPU) ‘On PQFP package the following pins are NIC (No Connect): 2, 11, 14, 15, 24, 43, 44, 62, and 63. ‘On TOFP package the following pins are N/C (No Connect): 4, 25, 35, 85, 72. Key to Pin Description Codes ['Symbor [Description [ Symbor | Description [|__| Input Only HA(x) | Hold Acknowledge: Pin state while processor [Output Only ae orcas ae. | _O _| Output Only HA(1) = Internally driven to Veo HA(O) « Internally driven to Ves ‘S(x) _| Synchronous: Setup and Hold times must HA(Z) = Internally floated be met for proper operation. HA(A) = Remains active : S(E) = Edge Sensitive HA(X) = Retains current state S(L) = Level Sensitive Rix) | Reset: Pin state while the processors RES ' - 7 line is held Low externally. : ‘Asynchronous: Setup and Hold times guarantee d signal recognition by the processor. Ai = {rtornally riven ‘ Nod A(E) = Edge Sensitive Az) x internally losted A(L) = Level Sensitive R(A) = Remains Active R(PU) = Weak internal pull-up @™ 0257525 00495578 777 R(PD) = Weak internal pull-down 80C186/80C188 Microprocessors n

80C186 ORDERING INFORMATION Commodity Products AMD® commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. N socias = 12 —_ SPEED OPTION Blank = 10 MHz ~12 = 12.5MHz ~16 = 16MHz =20 = 20MHz -25 = 25MHz DEVICE NUMBER/DESCRIPTION

800186 CMOS High-Integration 16-Bit Microprocessor

N = 68-Pin Plastic Leaded Chip Carrier S_ = 80-Pin Plastic Quad Flat Pack SB = 80-Pin Thin Quad Flat Pack TEMPERATURE RANGE | = Industrial (40°C to +85°C) Blank = Commercial (0°C to +70°C) Vals Combination [_Na0c186,INaoo1es | _ Valid Combinations lst configurations planned to NB0C186, IN80C186 be supported in volume for this device, Consult N@0C186-12, IN80C186-12 the local AMD sales office to confirm availability of [Naoctas—t6, INBOG186—16 | _SPetitic valid combinations and to check on newly PLC N80C186-16, INB0C186-16 rocated combinations, N80C186-20, INB0C 186-20 parr Trimmed and Formed $80C186-25 Tar ‘$B80C186-25 mm 0257525 0049579 Ob 12 80C186/80C188 Microprocessors

PRELIMINARY amo £4 80C188 ORDERING INFORMATION Commodity Products AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below, N s0cie8. 12 —_ SPEED OPTION Blank = 10 MHz 12 = 12.5MHz -16 = 16MHz -20 = 20MHz -25 = 25MHz DEVICE NUMBER/DESCRIPTION

806188 CMOS High-Integration 16-Bit Microprocessor

N_ =68-Pin Plastic Leaded Chip Carrier $= 80-Pin Plastic Quad Flat Pack SB = 80-Pin Thin Quad Flat Pack TEMPERATURE RANGE | = Industrial (-40°C to +85°C) Blank = Commercial (0°C to +70°C) Valid Combinations [_Ne0ct#a, Ineoo16a | _ Valid Combinations list configurations are planned NG0C188, INBOC188 to be supported in volume for this device. Consult the local AMD sales office to confirm the avail- | Ng0C188-16, IN0O188-16 _| ability of specific valid combinations and to check PLCC N800188-16, INBOC188-16_| Gr newly released combinations. POFP Trimmed and Formed — “30618820 SB80188 TOFP $B800188-16 '38800188-25 \\ M™ 0257525 0049580 328 mm '80C186/80C188 Microprocessors 13

A19/S6, A18/S5, A17/S4, A16/S3 BHE (80C186 only) Address Bus Outputs (Outputs) Bus High Enable (Output) Address Bus Outputs (19-16) and Bus Cycle Status The BHE (Bus High Enable) signal is analogous to AO in (6-3) indicate the four most significant address bits dur- that it is used to enable data on to the most significant ing T1. These signals are active High. half of the data bus, pins D15—D8. BHE is Low during T1 , ' when the upper byte is transferred and remains Low During T2, T3, TW, and T4, the S6 pin is Lowto indicate through T3 and TW. BHE does not need to be latched. aCPU. initiated bus cycle, or High to indicate a DMA-ini- BHE floats during HOLD or RESET. tiated bus cycle. During the same T states, S3, S4, and $5 are always Low. These outputs are floated during In Enhanced Mode, BHE is also used to signify DRAM bus HOLD or RESET. refresh cycles. A refresh cycle is indicated by both BHE and AO being High. A15-A8 (800188 only) — Address-Only Bus (Outputs) BHE and AO Encodings Address-Only Bus (15-8) contains valid addresses from BRE Value floated during a bus HOLD or RESET. Word Transfer _, Byte Transfer on upper half of data AddrosPata Bus (nputslOuputs) bie 06-1 puts/Outputs) Byte Transfer on lower half of data Address/Data Bus (7-0) signals constitute the time mul- bus (D7-D0) tiplexed memory or I/O address (T1) and data (T2, T3, Refresh TW, and T4) bus. The bus is active High. These pins are floated during bus HOLD or RESET. CLKOUT AD15-ADO (80C186 only) Clock Output (Output) Address/Data Bus (Inputs/Outputs) Clock Output provides the system with a 50% duty cycle Address/Data Bus (15-0) signals constitute the time waveform. Alldevice pintimings are specified relative to multiplexed memory or I/O address (T1) and data (T2, CLKOUT. CLKOUT is active during RESET and bus T3, TW, and T4) bus. The busis active High. Adis analo- HOLD. gous to BHE for the lower byte of the data bus, pins D7-DO. It is Low during T1 when a byte is to be trans- DEN ferred onto the lower portion of the bus inmemory or /O Data Enable (Output) operations. These pins are floated during a bus HOLD Data Enable is provided as a data bus transceiver output or RESET. enable. DEN is active Low during each memory and /O access (including 800187 access). DEN is High when- ALE/QSO ever DT/A changes state. DEN floats during a bus Address Latch Enable/Queue Status (Output) HOLD or RESET. Address Latch Enable/Queue Status 0 is provided by the 80C186/C188 to latch the address. ALE is active DRQO-DRQ1 High, with addresses guaranteed to be valid onthe trail- | OMA Requests (Inputs) ing edge. DMA Request is asserted High by an external device when it is ready for DMA Channel 0 or 1 to perform a ARDY transfer. These signals are level triggered and internally Asynchronous Ready (Input) synchronized. Asynchronous Ready informs the 80C186/C188 that the addressed memory space or I/O device will com- OTR plete a data transfer. The ARDY pin accepts a rising Data Transmit/Recelve (Output) edge that is asynchronous to CLKOUT and is active Data Transmit/Receive controls the direction of data High. The falling edge of ARDY mustbe synchronizedto —_ flow through an external data bus transceiver. When the 80C186/C188 clock. Connecting ARDY High always Low, data is transferred to the 80C186/C188. When asserts the ready condition to the CPU. If this line is High, the 80C186/C188 place write data on the data unused, it should be tied Low to yield control to the bus. DT/R floats during a bus HOLD or RESET. SRDY pin. W™ 0257525 0049581 ebh mm 1 14 80C186/80C188 Microprocessors

HOLD, HLDA data cycle associated with the instruction immediately (Input, Output) following the LOCK prefix. It remains active until the i i 7 completion of that instruction. No instruction prefetching HOLD indicates that conn bus master is requesting i occur while LOCK is asserted. LOCK has an intemal - input is active High. The I-up that is active during bus HOLD or RESET. 80C186/C188 generate HLDA (High) in response toa Pull up thats active during bus or : HLDA meboctesictesuitealinctocatbusandcon. MESO, MCST, MCS2, MESS ¥ re . Mid-Range Memory Chip Select trol lines. After HOLD is detected as being Low, the 80C186/C188 lower HLDA. When the 80C186/80C188 _(Output/Inputs, Outputs) needs to run another bus cycle, it will again drive the Mid-Range Memory Chip Select signals are active Low local bus and contro! lines. when a memory reference is made to the defined mid- range portion of memory (8K-512k). These lines do not In Enhanced Mode, HLDA goes Low when a DRAM finat during bus HOLD. The address ranges activating fefresh cycle is pending in the 80C186/C188 and an j4GEg_MGSO are software programmable external bus master has control of the bus. Itwillbe up to the external master to relinquish the bus by lowering In Enhanced Mode, MCSO and MCS3 become dummy HOLD so that the 80C186/C188 may execute the _ inputs to maintain compatibility. They should be treated refresh cycle. as inputs and tied High/Low when in Enhanced Mode. INTO, INT1/SELECT, INT2/INTAD, meso aug RES pave weak internal pull-ups that are INT3/INTAT/IRQ Maskable Interrupt Requests NMI (inputs, Input/Output) Non-Maskable Interrupt (Input) Maskable Interrupt Requests can be requested by acti- The Non-Maskable Interrupt input causes a Type 2 vating one of these pins. When configured as inputs, _interrupt. An NMI transition from Low to High is latched these pins are active High. Interrupt Requests are syn- —_and synchronized internally, and initiates the interrupt at chronized internally. INT2 and INT3 may be configured —_the next instruction boundary. NMI must be asserted for to provide active-Low interrupt-acknowledge output sig-__at least one CLKOUT period. The Non-Maskable Inter- nals. All interrupt inputs may be configured to be either tupt cannot be avoided by programming. edge or level triggered. To ensure recognition, all inter- tupt requests must remain active until the interrupt is BGS5/A1 acknowledged. When Slave Mode is selected, the func- Peripheral Chip Select 5 or Latched A1 (Output) soon on tn data cree) (see the Interrupt Controller erinheral Chip Select 5 or Latched A1 may be pro- . grammed to provide a sixth peripheral chip select, or to tes provide an intemally latched a signal. The address range activating PCS5 is software programmable. Lower Memory Chip Select (Output/Input) When programmed to provide latched At rather than Lower Memory Chip Select is active Low whenever a BSS, this pin will retain the previously latched value of memory reference is made to the defined lower portion A1 during abus HOLD. A1 is active High. PCS5/A1 does (1K-256K) of memory. LCS does not float during bus not float during bus HOLD. HOLD. The address range activating LCS is software programmable, PCS6/A2 UCS andLCSare sampleduponthe rising edge ofS. Peripheral Chip Select 6 or Latched A2 (Output) Ifboth pins are held Low, the 80C186/C 188 enter ONCE Peripheral Chip Select 6 or Latched A2 may be pro- mode. In ONCE mode all pins assume a high-imped- grammed to provide a seventh peripheral chip select, or ance state and remain so until a subsequent RESET. _to provide an internally latched A2 signal. The address TS has aweak internal pull-up that is activeonly during range activating PCS6 is software programmable. | RESET to ensure that the 80C186/C 188 does not enter When programmed to provide latched A2 rather than : ONCE mode inadvertently. PCS6, this pin retains the previously latched value of A2 ! during a bus HOLD. A2 is active High. PCS6/A2 does COCK not float during bus HOLD. Lock (Output) PCS4-PCSO LOCK output indicates that other system bus masters Peripheral Chip Select Signals (Outputs) are not to gain control of the system bus. LOCKis active Peripheral Chip Select signals (4-0) are active Low Low. The LOCK signal is requested by the LOCK prefix when a reference is made to the defined peripheral area instruction and is activated at the beginning of the first 80C186/80C188 Microprocessors 15 Mm oe57525 0049562 LTO .

(64-Kbyte I/O or 1-Mbyte memory space). These lines S2 may be used as a logical memory or I/O indicator, do not float during bus HOLD. The address ranges acti-. and S1 as a DT/R indicator. vating PCS4-PCSO are software programmable. RD/QSMD 80C186/C188 Bus Cycle Status Information Read Stobe ls an ate Low signal which ndcates [== [| % [ee Oreeinwied Read Strobe is an active Low signal, which indicates that the 80C186/C188 is performing a memory or VO [0 [0 [interrupt Acknowledge read cycle. Itis guaranteed not to go Low before the A/D. 1 | Read VO bus is floated. An internal pull-up ensures that RD/QS- | | 0 |Write VO a MD is High during RESET. Following RESET, the pin is poj;t |? | Halt OS sampled to determine whether the 80C186/C188 is to ~ provide ALE, RD, and WR, or queue status information. | 1 | © | 0 ||Instruction Fetch To enable Queue Status Mode, RD must be connected 1 | 0 [1 [Read Data from Memory to GND. RD floats during bus HOLD. 7 [7 | 0 [Write DatatoMemory RES [1 fi [1 | Passive (no bus cycle) RESET (Input) Anactive HES causes the 80C 186/188 to immediately SRDY terminate its present activity, clear the internal logic, and Synchronous Ready (Input) enter a dormant state. This signal may be asynchronous Synchronous Ready informs the 80C186/C188 that the to the 80C186/C188 clock. The 80C186/C188 begins addressed memory space or |/O device will complete a fetching instructions approximately 6% clock cycles data transfer. The SRDY pin accepts an active-High after RES is returned High. For proper initialization, Voc input synchronized to CLKOUT. The use of SRDY must be within specifications and the clock signal must allows a relaxed system timing over ARDY. This is be stable for more than four clocks with RES held Low. accomplished by elimination of the one-half clock cycle RES is internally synchronized. This input is provided required to internally synchronize the ARDY input sig- with a Schmitt-rigger to facilitate power-on RES gen- _nal. Connecting SRDY High always asserts the ready eration via an RC network. condition to the CPU. If this line is unused, it should be tied Low to yield control to the ARDY pin. RESET System Reset (Output) TEST RESET output indicates that the 80C186/C188 CPUis _Test (Input) being reset and can be used as a system reset. It is The TEST pin is sampled during and after reset to deter- active High, synchronized with the processor clock, and mine whether the 80C186/C188 is to enter Compatible lasts an integer number of clock periods corresponding or Enhanced Mode. Enhanced Mode requires TEST to to the length of the RES signal. RESET goes inactive be High on the rising edge of RES and Low four two clockout periods after RES goes inactive. Whentied CLKOUT cycles later. Any other combination places the to the TEST pin, RESET forces the 80C186/ 80C188 80C186/C188 in Compatible Mode. During power-up, into enhanced mode. RESET is not floated during bus active RES is required to configure TEST as an input. A HOLD. weak internal pull-up ensures a High state when the pin is not driven. This pin is examined by the WAIT instruc- RFSH (80C188 only) tion. If the TEST input is High when WAIT execution Refresh (Output) begins, instruction execution will suspend. TEST In compatible mode, AFSH is High. in enhanced mode, __‘Tesampled every five clocks until it goes Low, at which RFSHis asserted Lowto signify arefreshbuscycle, The _time execution resumes. If interrupts are enabled while RFSH output pin floats during bus HOLD or RESET, the 80C186/C188 is waiting for TEST, interrupts will be regardless of operating mode. serviced, 52-50 TMR INO, TMR IN1 Bus Cycle Status (Outputs) Timer Inputs (Inputs) Bus cycle status S250 are encoded to provide bus- Timer inputs are used either as clock or control signals, transaction information. depending upon the programmed timer mode. These inputs are active High (or Low-to-High transitions are The status pins float during HOLD/HLDA. counted) and internally synchronized. Timer inputs must M@@ 0257525 0049583 037 a 16 80C186/80C188 Microprocessors

TOTO Er orrrerrn—r SSSA NN be tied High when not being used as clock or retrigger, + WR/QS1 inputs. Write Strobe/Queue Status 1 (Output) Write Strobe/Queue Status 1 indicates that the data on TMA OUTO, TMR OUT! thet sobewtonioa nemoryaran VO devi Rl pI puts) - is active Low and floats during bus HOLD or RESET. Timer outputs are used to provide single pulse or contin- When the 80C186/C 188 is in Queue Status Mode, the uous waveform generation, depending upon the timer ALE/QS0 and WA/QS1 pins provide information about mode selected. These outputs are not floated during a processor/instruction queue interaction. bus HOLD. UCs Upper Memory Chip Select (Output/input) | © [© [Noquevecperation Upper Memory Chip Select is an active Low output | © | 1 _|First opcode byte fetched from the queue whenever a memory reference is made to the defined | 1 | 1 [Subsequent byte fetched from the queue upper portion (1K-256K block) of memory. UCS does fa | o | Empty the queue - not float during bus HOLD. The address range activat- ing UCS is software programmable. X1, X2 UCS andCS are sampleduponthe rising edge of RES. C¥Stal Inputs (Input/Output) If both pins are held Low, the 80C186/C188 enters Crystal inputs X1 and X2 provide external connections ONCE Mode. In ONCE Mode, all pins assume a high- for a fundamental mode or third overtone parallel reso- impedance state and remain so until a subsequent nant crystal for the internal oscillator. X1 can connect to RESET. UCS has a weak internal pull-up that is active an external clock instead of a crystal. In this case, mini- during RESET to ensure that the 80C186/C188 does mize the capacitance on X2. The input or oscillator fre- not enter ONCE Mode inadvertently. quency is internally divided by two to generate the clock signal (CLKOUT). Vee Power Supply (Inputs) ‘System power: +5-V power supply. Vss Ground (Inputs) ‘System ground. M 0257525 0049584 T73 SSS 80C186/80C188 Microprocessors 7

‘The following Functional Description describesthebase Pairs of Separate B-bit registers. Compatible and Enhanced. In Compatible Mode the —_to determine offset addresses of operands in memory. design: power-save control, and dynamic RAM refresh, address calculations. Register Set control flag bits (see Figures 1 and 2). function of the Status Word bits is shown in Table 1.

1 Segment Registers

Figure 1. 80C186/C188 Register Set

Table 1. Status Word Bit Functions 0 Carry Flag—Set on high-order bit carry or borrow; cleared otherwise.

4 AF Auxiliary Carry—Set on carry from or borrow to the fow order four bits of the general

purpose register AL; cleared otherwise. ) 6 | 2 | Zero Flag—Set if result is 0; cleared otherwise. Sign Flag—Set equal to high-order bit of result (0 if positive, 1 if negative). executes. TF is cleared by the single-step interrupt. to an interrupt vector specified location.

10 DF Direction Flag—Causes string instructions to auto decrement the appropriate index

register when set. Clearing DF causes auto-increment. Figure 2. Status Word Format The instruction setis divided into seven categories:data “Mata sheet.

PRELIMINARY amo © TT ere SSSA Input/Output REPNE/REPNZ Repeat while not equal/not zero IN Input byte or word Logicals OUT Output byte or word NOT “NOT" byte or word Address Object AND “AND" byte or word LEA Load effective address OR “Inclusive or’ byte or word Los Load pointer using DS XOR “Exclusive or” byte or word LES Load pointer using ES Test “Test” byte or word Flag Transfer Shifts oo LAE Load AH register from flags SHUSAL Shit logicavarithmetic left byte SAHF Store AH register in flags SHR Shitt logical right byte or word PUSHF Push flags onto stack SAR Shitt arithmetic right byte or word POPF Pop flags off stack Rotates Addition ROL Rotate left byte or word ADD Add byte or word ROR Rotate right byte or word ADC Add byte or word with carry RCL Rotate through carry left byte or word INC Increment byte or word by 1 RCR Rotate through carry right byte orword AAA ASCII adjust for addition Flag Operations DAA Decimal adjust for addition sTc Set carry flag Subtraction cLC Clear carry flag suB Subtract byte or word cmc Complement carry flag SBB Subtract byte or word with borrow sTD Set direction flag DEC Decrement byte or word by 1 cLD Clear direction flag NEG Negate byte or word STi Set interrupt-enable flag cMP ‘Compare byte or word cut Clear interrupt-enable flag AAS: ASCII adjust for subtraction External Synchronization DAS Decimal adjust for subtraction HLT Halt until interrupt or reset Multiptication WAIT Wait for TEST pin active MUL Multiply byte or word unsigned Esc Escape to extension processor | (MUL. Integer multiply byte or word LOCK Lock bus during next instruction o MM ASCII adjust for multiply No Operation fh Division NOP No operation x DIV Divide byte or word unsigned w _ High Level Instructions mw «IDV Integer divide byte or word ENTER ‘ pap ASCII adjust for division ramet stack for procedure entry . B cow Convert byte or word LEAVE estore stack for Procedure exit ' . cwp Convert word to doubleword BOUND rae values outside prescribed | & MOVS Move byte or word string Conditional Transfers oc INS Input bytes or word string | . JAJNBE Jump if above/not below nor equal cr OUTS Output bytes or word string 7 ! ry . JAE/JNB Jump if above or equal/not below a CMPS Compare byte or word string 7 JB/JNAE Jump if below/not above nor equal STOS Store byte or word string a JBE/JNA Jump if below or equal/not above REP Repeat JC J i REPE/REPZ Repeat while equal/zero ump # cany 80C186/80C188 Microprocessors 21

JENZ Jump if equal/zero address, is calculated by summing any combination of JG/JNLE Jump if greater/not less nor equal the following three address elements: JGE/JNL Jump if greater or equal/not less 1. the displacement (an 8- or 16-bit immediate value JUSNGE Jump if less/not greater nor equal contained in the instruction); JLEAING Jump if less or equal/not greater 2. the base (contents of either the BX or BP base UNG J inet registers); and, jump H not carry 3. the index (contents of either the SI or DI index JNE/INZ Jump if not equal/not zero registers). JNO Jump if not overflow Any carry out from the 16-bit addition is ignored. Eight- JNP/JPO Jump if not parity/parity odd bit displacements are sign-extended to 16-bit values. JNS Jump if not sign Combinations of these three address elements define JO Jump it overflow the six memory addressing modes, described below. JPIPE Jump if parity/parity even 1. Direct Mode: The operands offset is contained in JS Jump if sign the instruction as an 8- or 16-bit displacement Unconditional Transfers 2 ne nalrect Mode: Th asf . Register Indirect le: The operand’s offset is in CALL Call procedure one of the registers SI, Dl, BX, or BP. RET Return from procedure 3. Based Mode: The operand's offset is the sum of JMP- Jump an 8- or 16-bit displacement and the contents of a base register (BX or BP). Iteration Controls i 4. Indexed Mode: The operand's offset is the sum of LOOP Loop an 8- or 16-bit displacement and the contents of an LOOPE/ index register (SI or Dl). LOOPZ Loop if equal/zero 5. Based Indexed Mode: The operand's offset is the LOOPNE/ sum of the contents of a base register and an LOOPNZ Loop if not equal/not zero index register. ¥ i - 6. Based Index Mode with Displacement: The JOxZ Jump if register CX = 0 operand's offset is the sum of a base register’s Interrupts contents, an index register’s contents, and an 8- or INT Interrupt 16-bit displacement. INTO Interrupt if overflow Data Types IRET Interrupt return The 80C186/C188 directly supports the following data Addressing Modes ‘ype , ‘ lm Integer: A signed binary numeric value contained The 80C186/C 188 provides eight categories of addres- in an 8-bit byte or a 16-bit word. All operations sng modes to bpecty operands Two addressing assume a two's complement representation modes are provi instructions that operate on reg- a - is i i . @ Ordinal: An unsigned binary numeric value ister or Immediate operands: Contained in an 8-bit byte or a 16-bit word. 1. Register Operand Mode: The operand is located in m Pointer: A 16- or 32-bit quantity, composed of a ‘one of the 8- or 16-bit registers. 16-bit offset component or a 16-bit segment base paaihie 16-bR offset 2. Immediate Operand Mode: The operand is. component in addition to a 16-bit oftse included in the instruction. String: A conti of byt rd . - ™ String: A contiguous sequence les or words. Six modes are provided to Speci the location of an Astring may oontain inet Kbytes. operand in a memory segment. A memory operant . F address consists of two 16-bit components: a segment . ee eee te ach canard base and an offset. The segment base is supplied by a character representation 16-bit segment register either implicitly chosen by the . . addressing mode or explicitly chosen by a segment _™ BCD: A byte (unpacked) representation of the override prefix. The offset, also called the effective decimal digits 0-9. WM 0257525 0049589 555 a 22 80C186/80C188 Microprocessors

Figure 5. 80C186/C188 Supported Data Types

if the exception was caused by executing an ESC Non-Maskable Interrupt-NMI (Type 2) instruction, the return instruction points to the ESC An external interrupt source that is serviced regardless instruction, or to the segment override prefix immedi- _of the state of the IF (interrupt enable flag) bit. No exter- ately preceding the ESC instruction if the prefix was nal interrupt acknowledge sequence is performed. The present. In all other cases, the return address from an _|F bitis cleared atthe beginning of a NMI interrupt to pre- exception points to ‘the instruction immediately following vent maskable interrupts from being serviced. A typical the instruction causing the exception. use of NMI would be to activate a power failure routine. Atable containing up to 256 pointers defines the proper interrupt service routine for each interupt. Interrupts feakpoint Interrupt (Type 3) 0-31, some of which are used for instruction exceptions, A 1-byte version ‘of the INT instructions. It uses 12 are reserved. Table 3 shows the 80C186/C 188 prede- (OCH) as an index into the service routine address table fined types and default priority levels. For each interrupt, (because it is a Type 3 interrupt). an 8-bit vector must be supplied to the 80C186/C188, which identifies the appropriate table entry. Exceptions INTO Detected Overflow Exception (Type 4) supply the interrupt vector internally. In addition, intemal Generated during an INTO instruction if the OF bit is set. peripherals and non-cascaded external interrupts gen- erate their own vectors through the intemal internet Array BOUNDS Exception (Type 5) controller. INT instructions contain or imply the vector Ge , i ion i enerated during a BOUND instruction if the array and allow access to all 256 interrupts. Maskable hard- ing is outside the array bounds. The array bounds are ware-initiated interrupts supply the 8-bit vector to the located in memory at a location indicated by one of the CPU during an interrupt acknowledge bus sequence. —_inctruction operands. The other operand indicates the Non-maskable hardware interrupts use a predefined value of the index to be checked. internally supplied vector. 7 Unused Opcode Exception (Type 6) Interrupt Sources Generated if execution is attempted on undefined The 80C186/C188 can service interrupts generated by ‘opcodes. software or hardware. The software interrupts are gen- erated by specific instructions (INT, ESC, unused OP, ESCAPE Opcode Exception etc.) or the results of conditions specified by instructions 4 (array bounds check, INTO, DIV, IDIV, ee.) Allinterrupt (oo oey, It execution is ate ott check the sources are serviced by an indirect call thro ugh an ele- escape opcode trap bit. ESC traps occur in both compat- ment of a vector table. This vector table is indexed by ible and enhanced operating modes. The return using to see eens ore sampled at address of this exceptionwill point tothe ESC instruction the end ofeach instruction Thus, the software | inter ts causing the exception. if a segment override protix pre. i, i - vi ine js Ip ceded the ESC instruction, the return address will point begin service first. Once the service routine is entered to the segment override prefix. and interrupts are enabled, any hardware source of sutfi- eg Prefix, cient priority can interrupt the service routine in progress. Note: All numerics coprocessor opcodes cause a trap. The Those pre-defined 80C186/C 188 interrupts that cannot 80C 186/C 188 does not Support the numerics interface. be masked by programming are described below. i Divide Error Exceptio 0 Hardware Interrupts vide Error Exception (ype. ) . . Hardware-generated interrupts are divided into two © Generated when a DIV or IDIV instruction quotient can- groups: maskable interrupts and non-maskable inter- TY notbe expressed inthe number of bits inthe destination. —_rypts. The 80C186/C188 provides maskable hardware _ interrupt request pins INT3-INTO. In addition, maskable EH Single-Step Interrupt (Type 1) interrupts may be generated by the 80C186/C-188 inte- tn_ Generated after most instructions if the TF (single step) grated DMA controller and the integrated timer unit. The flag in the status word is set. This interrupt allows pro- vector types for these interrupts is shown in Table 3. S grams to execute one instruction at a time. Interrupts are Software enables these inputs by setting the interrupt o ‘= not be generated after prefix instructions (e.g., REP), enable flag bit (IF) in the Status Word. The interrupt con- a instructions that modify segment registers (e.g., POP troller is discussed in the peripheral section of this data <n DS), or the WAIT instruction. Vectoring to the single- sheet. & step interrupt service routine clears the TF bit. An RET . _ 7 . 1 _ instruction in the interrupt service routine restores the Further maskable interrupts are disabled while servicing G TFbit A logic d and wranators control to the next instruc- aeponse to eee re eivepton The seved Sane LJ tion to be single-steppe , P| 0 ng PP Word will reflect the enable status of the processor prior a 24 80C186/80C188 Microprocessors

Program are executed). ters to predefined values as shown in Table 4. Table 3. 80C186/C188 Interrupt Vectors

1. Generated as a result of an instruction execution.
2. Performed in the same manner as 8086/8088.
3. An ESC opcode wil cause a trap regardless of the 800 186/C 188 operating mode, The 80C186/C 188 are not directly compat

‘ble with the 80188 in this respect. The instruction set of the numerics coprocessor cannot be executed.

1. All three timers constitute one source of request to the interrupt controller. As such, they share the same priority level with

fespect to other interrupt sources. However, the timers have a defined priority order among themselves (2A > 2B > 2C).

1. The vector type numbers of these sources are programmable in Slave Mode.

Table 4. 80C186/C188 Initial Register State after Clock Generator be used either with a parallel resonant fundamental or at the falling edge of TW. should equal the values shown. It is advisable to limit cussed in the Chip Select/Ready Logic description. ing a crystal: approximately two and one-half clocks behind RES.

800188 Note 1

32 MHz 4,7 nH 420%

Figure 6. 80C186/C188 Oscillator Configurations local bus to other bus masters. It also provides outputs strobe data from the 80C186/C188 to memory or I/O.

Transceiver Control taking control of the bus to run the refresh cycle. shown in Table 5. then float them.

1. Drive S2-S0 to the inactive state (all High) and then

Table 5. Transceiver Control Signals Description float. DEN (Data Enable) Enables the output drivers of th 800188), DTIR. ata En 8 the o1 rivers of the . transceivers. It is active Low 4. Drive ALE Low. during memory, VO, or INTA 5. Drive HLDA Low. sor during a read operation. & RD/QSMD Low results in Queue Status Mode. Local Bus Arbitration m_UCS and LCS Low result in ONCE Mode. exchange. This provides an asynchronous bus exchange Mode. same bus can operate at separate clock frequencies. . the HOLD request is received. A HOLD request is written by the 800186/C188 CPU at any time. second only to DRAM refresh requests in priority of . ig increased by the length of the locked transter. internal chip select.

Table 6. UMCS Programming Values. Table 7. LMCS Programming Values UMCS register (see Figure 9). This register is at offset chip-select register. The internal generation of any 20-bit address whose Memory block are programmable. always OH, while the upper limit is programmable. By MCSS being active for the last range. | | the upper address selected and the size of the memory ity, as described in a later section.

Table 11. READY Bits Programming VO) orwithin the same space (e.g., Memory to Memory or [ojolo] 0 wait states, external RDY also used. cor in words (16 bits) to or from even or odd addresses. aan 3 wait sates inserted, external RDY also ‘one cycle to fetch data and the other to store data. external READY, not in series if the external READY is transfers can be performed with automatic termination. wait states generated by the internal generator over- operation.

1. All chip-select outputs are driven High, DMA Channel Control word Register
2. Upon leaving RESET, the UGS line is programmed + ation for the particular 80C186/C188 DMA chan.
3. No other chip select or READY control registers Fon ey Dies oF words are transterved (80186

m whether the source pointer is incremented, transfer. transfer remains constant after each cycle. m whether the source pointer addresses memory or . m= whether the destination pointer addresses memory transfer. the channel is operating. However, any changes made transfer. DMA Control Word Bit Descriptions remains constant after each cycle. contents of the TC register reach 0. Figure 14. DMA Unit Block Diagram

is__i4 43 2) to 0 MiG DEC INC | Mio Dec inc} To | INT SYN Tora] x Ocha STOP Figure 15a. DMA Control Register for the 80C186 1 44 13 2 td dl GG 9 Destination Source sw MIO_DEC INC} MIO DEC INC] Tec | INT SYN ToRQ| x _|NOCHG STOP} Xx Figure 15b. DMA Control Register for the 80C188 SSMS INT Enable Interrupts to CPU upon transfer count ually incremented or decremented after each transfer. If termination. word transfers are performed, the pointer is increm- SYN 00 No synchronization ented or decremented by two. Note: When unsynchronized transfers are specified, the TC Each pointer may point into either memory or I/O space. iis Ignored and the STSTOF bitiscleareduponthe Since the upper four bits of the address are not automat- transfer count reaching zero, stopping the channel. ically programmed to zero, the user must program them 01 Source synchronization in order to address the normal 64K I/O space. Since the . 40 Destination synchronization DMA channels can perform transfers to or from odd

4 UI addresses, there is no restriction on values for the

1 nused pointer registers. Higher transfer rates can be achieved P Channel priority relative to other if all word transfers are performed to or from even channel during simultaneous requests addresses so that accesses occur in single bus cycles.

0 Low priority eee

1 High priority Higher

Channels alternate cycles if both are set at Register same priority level. Lower A ister] A1S—A12] A11-A8 ]A7—A4 | A3-AO TORQ Enable/Disable (1/0) DMA requests from _asieter [ars—ara[ant—ae [arnt [ao-a0 | Timer 2. 15 0 CHG/NOCHG XXX = Don't Care Change/Do not change (1/0) ST/STOP bit. If 13087D-017 this bit is set when writing to the control word, the ST/STOP bit is programmed by the write to Figure 16. DMA Pointer Register Format the control word. If this bit is cleared when —_ << writing the control word, the ST/STOP bit is i: not altered. This bit is not stored; itis always DMA Transfer Count Register | | read as 0. Each DMA channel maintains a 16-bit transfer count register (TC). This register is decremented after every o STOP st/Stop (1/0) channel DMA cycle, regardless of the state of the TC bit in the uo fartiStop (1/0) channe DMA Control Register. However, if the TC bit inthe DMA ety Bw Byte/Word (0/1) transfers (for the 80C186 control word is set or if unsynchronized transfers are a only) programmed, DMA activity terminates when the transfer (1 DMA Destination and Source Pointer counter register reaches 0

2 Registers DMA Requests

= — Each DMA channel maintains a 20-bit source and @ ata transfers may be elther source or destination syn- ao 20-bit destination pointer. Each of these pointers takes chronized, that is, either the source of the data or the © __uPtwotull 16-bitregisters inthe peripheralcontrolblock. —_Gestination of the data may request the data transfer. In mu Foreach DMAchannel to be used, allfour pointer regis _adition, DMA transfers may be unsynchronized: that i, co» ers must be initialized. The ower four bits ofthe upper the transfer takes place continually until the correct t= __ fegister contain the upper four bits of the 20-bit physical number of transfers has occurred. When source or "op address (see Figure 16). These pointers may be individ- SSS | | 80C186/80C188 Microprocessors 35

clock cycles (assuming no wait states). When destina- respond to the NMI request. destination device time to remove its request if another before the ST/STOP bit is set. No explicit DMA acknowledge pulse is provided. Since __Petween updates to the channel registers. nal. Since the chip-select lines can be programmed to be . . active for a given block of memory or /O space, and the m The ST/STOP bit for each channel is reset to STOP. DMA pointers can be programmed to point to the same Any transfer in progress is aborted.

• pointers, and destination pointers are indeterminate.

have priority over internal CPU cycles except between external events, generate non-repetitive waveforms, etc. memory locations; however, an external bus hold takes is useful for real-time coding and time delay applications. request cannot suspend a DMA operation and the CPU the other two, or as a DMA request source. Table 13. Maximum DMA Transfer Rates at 25 MHz for the 80C186/80C188

Figure 17. Timer Block Diagram peripheral control block. The configuration of these regis- 0 any individual clock or gate input. current value of the timer. Itcan be read or written at any ters are all 16-bits wide, 16 bits of resolution are provided. p fl the internal ti the internal bus. clock, one clock after the maximum count value has been events. External clocking of the timers may be done at up to arate grated timers.

Table 14. Timer Control Block Format configured in dual MAX COUNT register mode, this bit Register Offset willbe set each time the value in MAX COUNT register A. Max Count A s2H | sAH | 62H through interrupts. Count Register 50H 58H 60H Programmer's intervention is required to clear this bit. enabledto increment subjectto the input pin constraints Provided by the input pin. count. respect to the 80C186/C188 clock. cleared after the interrupt request has been generated, _o obtain the prescaled clock. RIU asynchronous with respect to the 800 186/C188 clock. “The Maximum Count bit is set whenever the timer out losing clock pulses.

ALT 1, AIlEN (Enable) bits are reset preventing timer The ALT bit determines which of two MAX COUNT reg- counting. isters is used for count comparison. If ALT = 0, register 2. For Timers 0 and 1, the RIU bits are reset to zero Afor that timer is always used, while if ALT = 1, the com- and the ALT bits are set to one. This results in the parison alternates between register A and register B Timer Out pins going High. when each maximum count is reached. This alternation i allows the user to change one MAX COUNT register 3. The contents of the count registers are while the other is being used, and thus provides a method of generating non-repetitive waveforms. INTERRUPT CONTROLLER Square waves and pulse outputs of any duty cycle ar® a The g9c186/6188 canroceive interrupts froma number subset of available signals obtained by not changing the sources, both internal and external. The internal inter- ‘ final count registers. The ALT bit also determines the bd " ’ " . " s tupt controller serves to merge these requests on a function of the timer output pin. If ALT is 0, the output pin riority basis for individual service by the CPU goes Low for one clock, the clock after the maximum Priority ¥ count is reached. If ALT is 1, the output pin reflects the Internal interrupt sources (Timers and DMA channels) current MAX COUNT register being used (0/1 for B/A). canbe disabled by their own control registers or by mask bits within the interrupt controller. The 80C186/C188 CONT interrupt controller has its own control register that sets Setting the CONT bit causes the associated timer to run the mode of operation for the controller. continuously, while resetting it causes the timer to halt . — upon maximum count. If CONT =0 and ALT =1, the The interrupt controller resolves priority among timer counts to the MAX COUNT register A value, _‘@quests that are pending simultaneously. Nesting is resets, counts to the register B value, resets, andhalts. Provided so interrupt service routines for lower priority interrupts may themselves be interrupted by higher Not all mode bits are provided for Timer 2. Certain bits priority interrupts. A block diagram of the interrupt con- are hardwired as indicated below: troller is shown in Figure 19. ALT = 0, EXT = 0, P=0, RTG=0, RIU=0 The 80C186/C188 have a special slave mode in which the intemal interrupt controller acts as a slave to an Count Registers external master. The controller is programmed into this Each of the three timers has a 16-bit count register. The Tode by setting bit 14 in the peripheral control block contents of this register may be read or written by the _‘“@location register (see Slave Mode section). processor at any time. If the register is written into while the timer is counting, the new value takes effect in the MASTER MODE OPERATION current count cycle. Interrupt Controller External Interface The count registers should be programmed before Five pins are provided for external interrupt sources. attempting to use the timers, since they are not automat- One of these pins is the non-maskable interrupt, NMI, ically initialized to zero. NMlis generally used for unusual events such as power- fail interrupts. The other four pins may be configured in Max Count Registers any of the folowing ways i Timers 0 and 1 have two MAX COUNT registers, while ; i ath i Timer 2 has a single MAX COUNT registen These con- = As four interrupt lines with internally generated tain the number of events the timer counts. In Timers 0 interrupt vectors; and 1, the MAX COUNT register used can alternate @ Asan interrupt line and interrupt acknowledge line between the two MAX COUNT values whenever the pair (cascade mode) with externally generated current maximum countis reached. A timer resets when interrupt vectors, plus two interrupt input lines with the timer count register equals the MAX COUNT value internally generated vectors; and, being used. If the timer count register or the MAX m As two pairs of interrupt/interrupt acknowledge COUNT register is changed so that the MAX COUNT is lines (cascade mode) with externally generated less thanthe timer count, the timer does not immediately interrupt vectors. reset. Instead, the timer counts up to OFFFFH, “wraps External sources in the Cascade Mode use externally around” to zero, counts up to the MAX COUNT value, generated interrupt vectors. When an interrupt is and then resets acknowledged, two INTA cycles are initiated and the . vector is read into the 80C186/C188 on the second Timers and Reset cycle. The capability to interface to external 82C59A Upon RESET, the Timers perform the following actions: Programmable interrupt controllers is providedwhen the inputs are configured in Cascade Mode. mm 0257525 OO49b0b 4b4 me 80C186/80C188 Microprocessors 39

Figure 19. Interrupt Controller Block Diagram The basic modes of operation of the interrupt controller of higher priority than the in-service interrupt.

interrupt instruction. If the fully nested structure has issued by the programmer. input-dedicated acknowledge signal pairs. The intercon- through the same 80C186/C188 interrupt request pin. ity 80C186/C-188 interrupt sources. levels of priority are created, requiring priority resolu- polling of the IS register in the external master 82C59A. tion inthe 80C 186/C 188 interrupt controller, the mas- is required to determine if there is more than one bit set. interrupt is serviced, one |S bit is set at each of these the next interrupt service routine is entered. Figure 21. Cascade and Special Fully Nested Mode Interrupt Controller Connections

Operation In a Polled Environment Trigger Mode The controller may be used ina polled mode if interrupts The four external interrupt pins can be programmed in are undesirable. When polling, the processor disables either Edge- or Level-trigger Mode. The control register for interrupts and then polls the interrupt controller when- each external source has a Level-trigger Mode (LTM) bit. ever it is convenient. Polling the interrupt controller is A\\ll interrupt inputs are active High. In the Edge-sense accomplished by reading the Poll Word (Figure 30). Bit Modeorthe Level-trigger Mode, the interrupt request must 15 in the Poll Word indicates to the processor that an _remain active (High) until the interrupt request is acknow!- interrupt of high enough priority is requesting service. edged by the 80C186/C188 CPU. In the Edge-sense Bits 4-0 indicate to the processor the type vector of the Mode, if the level remains High after the interrupt is highest-priority source requesting service. Reading the acknowledged, the input is disabled and no further Poll Word causes the in-service bit of the highest-priority requests are generated. The input level must go Low for at source to be set. least one clock cycle to re-enable the input. In the Level- . . . trigger Mode, no such provision is made; holding the inter- Itis desirable to be able to read the Poll Word informa- i i it It tion without guaranteeing service of any pending inter- rupt input High causes continuous interupt requests. tupt, that is, not set the indicated in-service bit. The Interrupt Vectoring 80C186/C1: 88; provides a Poll Status ‘Word, in additionto ‘The 80C186/C188 Interrupt Controller generates interrupt the conventional Poll Word, to allow this to be done. Poll ° \\ oa " ‘ vectors for the integrated DMA channels and the inte- Word information is duplicated in the Poll Status Word, grated timers. In addition, the Interrupt Controller gener- but reading the Poll Status Word does not set the ates interrupt vectors: for the ‘external interrupt lines, if they associated in-service bit. These words are located in are not configured in Cascade or Special Fully Nested two adjacent memory locations in the register file. Mode. The interrupt vectors generated are fixed and can- Master Mode Features not be changed (see Table 3) Programmable Priority Interrupt Controller Registers The user can program the interrupt sources into any of The Interrupt Controller Register Mode is shown in Figure eight different priority levels. The programming is done 22. It contains 15 registers. All registers can either be read by placing a three-bit priority level (0-7) in the control —_or written, unless specified otherwise. register of each interrupt source. (A source with a prior- ity level of 4 has higher priority over all priority levels. = ofeet from 5 to 7. Priority registers containing values lower [NTS Control Register__| than 4 have greater priority.) All interrupt sources have INT3 Control Register SEH preprogrammed default priority levels (see Table 3). SCH aH Httwo requests with the same programmed priority level 38H are pending at once, the priority ordering scheme shown 36H in Table 3 is used. if the serviced interrupt routine re-en- 34H ables interrupts, it allows other interrupt requests to be 32H serieed, | Tterapr Status Resistor [20H End-of-intorrupt Command |_—Tterupt Request eis _[2EH The end-ot-interrupt (EO!) command is used by the pro- j2cH grammerto reset the in-service (IS) bitwhen an interrupt AH service routine is completed. The EO! command is 28H issued by writing the proper pattern to the EOI register. 28H There are two types of EO! commands, specific and 24H non-specific, The non-specific command does not spec- ify which IS bit is reset. When issued, the interrupt con- 22H troller automatically resets the 1S bit of the highest 19087D-023 priority source with an active service routine. A specific EOI command requires that the programmer send the Figure 22. nt ides Paaister interrupt vector type to the interrupt controller indicating which source's IS bit is to be reset. This command is used when the fully nested structure has been disturbed or the highest priority IS bit that was set does not belong to the service routine in progress. mm 0257525 0049609 173 a 42 80C186/80C188 Microprocessors

— TC etiMINARY no In-Service Register that are used in the individual control registers; pro- This register can be read from or written into. The for- gramming a mask bit using the mask register also mat is shown in Figure 23. It contains the in-service bit changes this bit in the individual contro! registers, and for each of the interrupt sources. The in-service bit is vice versa. set to indicate that a source's service routine is in prog- ress. Whenan in-service bit is set, the interruptcontrol- Priority Mask Register ler does not generate interrupts to the CPU when it This register is used to mask all interrupts below a partic- receives interrupt requests from devices with a lower ular interrupt priority level. The format of this register is programmed priority level. The TMR bit is the in-service shown in Figure 24. The code in the lower three bits of bit for all three timers; the DO and D1 bits are the in-ser- this register inhibits interrupts of priority lower (a higher vice bits for the two DMA channels; the 1310 are the in- priority number) than the code specified. For example, service bits for the external interrupt pins. The IS bit is 100 written into this register masks interrupts of level five set when the processor acknowledges an interrupt (101), six (110), and seven (111). The register is reset to request either by an interrupt acknowledge or by read- _ seven (111) upon RESET so no interrupts are masked ing the poll register. The IS bit is reset at the end of the due to priority number. interrupt service routine by an end-of-interrupt com- mand. Interrupt Status Register This register contains general interrupt controller status Interrupt Request Register information. The format of this register is shown in Fig- The internal interrupt sources have interrupt request bits ure 25. The bits in the status register have the following inside the interrupt controller. The format of this register functions: is shown in Figure 23. A read from this register yields the status of these bits. The TMR bit is the logical OR of all DHLT: DMA Halt Transfer; setting this bit halts all timer interrupt requests. DO and D1 are the interrupt DMA transfers. It is automatically set when- request bits for the DMA channels. ever a non-maskable interrupt occurs, and it is oC reset when an IRET instruction is executed. The state of the external interrupt input pins is also indi- This bit allows prompt service of all non-mask- cated. The state of the external interrupt pins is not a able interrupts. This bit may also be set by the stored condition inside the interrupt controller; there- programmer. fore, the external interrupt bits cannot be written. The external interrupt request bits are set when an interrupt IRTx: These three bits represent the individual timer request is given to the interrupt controller, so it Edge- interrupt request bits. These bits differentiate triggered Mode is selected, the bit in the register is High between timer interrupts, since the timer IR bit only after an inactive-to-active transition. For internal in the interrupt request register is the OR func- interrupt sources, the register bits are set when a tion of all timer interrupt requests. Note that request arrives and are reset when the processor setting any one of these three bits initiates an acknowledges the requests. interrupt request to the interrupt controller. Writes to the interrupt request register affectthe D0 and Control Registers: Timer, DMA 0, 1 D1 interrupt request bits. Setting either bit causes the These registers are the control words for all the internal corresponding interrupt request, while clearing either bit interrupt sources. The format for these registers is removes the corresponding interrupt request. All other shown in Figure 26. The three bit positions PRO, PR1, bits in the register are read-only. and PR2 represent the programmable priority level of the interrupt source. The MSK bit inhibits interrupt I | Mask Register requests from the interrupt source. The MSK bits in the This is a 16-bit register that contains a mask bit for each individual control registers are the exact same bits as in 3 _ interrupt source. The format for this registeris shown in _the Mask Register; modifying them in the individual con- ti; _ Figure 23. A oneinabitposition correspondingtoapar- _trol registers also modifies them in the Mask Register, “I _ ticular source serves to mask the source from generat- and vice versa. Hi___ inginterrupts. These mask bits are the exact same bits tt TT 8 15 14 7o 9 8 FT 6 5 4 3 2 4 0 3 LofoT. Tot ofof eT ef ne] of oof o [ima] r 3 19087D-024 2 Figure 23. In-Service, Interrupt Request, and Mask Register Formats i | 80C186/80C188 Microprocessors 43

INT3-INTO Control Registers interrupt. Reading the poll status register does not set These registers are the control words forthe fourexter- _the IS bit of the highest priority pending interrupt; only nal input pins. Figure 27 shows the format of the INTO _the status of pending interrupts is provided. and INT1 control registers; Figure 28 shows the format 7 of the INT2 and INT3 control registers. In Cascade Encoding of the Poll and Poll Status register bits are as. Mode or Special Fully Nested Mode, the control words / for INT2 and INT3 are not used. Se Encoded information that indicates the vector ; , ‘ type of the highest priority interrupting source. eons in the various control registers are encoded as Valid only when INTREQ = 1 INTREQ: This bit determines if an interrupt request is PR2-0: Priority programming information. Highest present. Interrupt Request =1; no Interrupt priority = 000, lowest priority = 111. Request = 0. LTM: Level-trigger Mode bit. 1 = level-triggered; 0 = edge-triggered. Interrupt input levels are | SLAVE MODE OPERATION active High. In Level-triggered Mode, an When Slave Mode is used, the internal 80C186/C188 interrupt is generated whenever the external interrupt controller is used as a slave controller to an line is High. In Edge-triggered Mode, an external master interrupt controller. The internal interrupt is generated only when this level is 80C186/C188 resources are monitored by the internal preceded by an inactive-to-active transition interrupt controller, while the external controller func- ‘on the line. In both cases, the level must tions as the system master interrupt controller. remain active until the interrupt is . acknowledged. Upon reset, the 80C186/C 188 is in the Master Mode, To , provide for Slave Mode operation, bit 14 of the reloca- MSK: Mask bit, 1 = mask; 0 = non-mask. tion register should be set (see Figure 7). c: Cascade Mode bit, 1 = cascade; 0 = direct. Because of pin limitations caused by the need to inter- SFNM: Special Fully Nested Mode bit, 1 = SFNM. face to an external 82C59A master, the internal interrupt EO! Register controller no longer accepts external inputs. There are, The end of the interrupt register is acommand register Nowever, enough 80C186/C188 interrupt controller that can only bewritten into. The format of this registeris __iMputs (internally) to dedicate one to each timer. In this shown in Figure 29. It initiates an EOI command when ‘Mode, each timer interrupt source has its own mask bit, written to by the 80C186/C188 CPU. |S bit, and control word. The bits in the EOI register are encoded as follows: In Slave Mode each peripheral must be assigned a unique priority to ensure proper interrupt controller Sx Encoded information that specifies an operation. Therefore, itis the programmer's responsibil- interrupt source vector type as shown in Table ity to assign correct priorities and initialize interrupt con- 3. For example, to reset the in-service bit for trol registers before enabling interrupts. DMA channel 0, these bits should be set to 01010, since the vector type forDMAchannel Slave Mode External Interface Ois 10. The configuration of the 80C186/C188 with respect to Note: tthe single bit the th an external 82C59A master is shown in Figure 31. The To reset the single in-service bit for any of the three INT input is used as the 80C186/C188 CPU interrupt Pare ne coges efor Timer (8) should bewrt- input. INT/Q functions as an output to send the 80C186/C188 slave-interrupt-request to one of the eight NSPEC/SPEC: master PIC inputs. A bit that determines the type of EO! ' ‘command. Non-specific = 1, Specific = 0. Correct master-slave interface requires decoding of the slave addresses (CAS2-CAS0). Slave 82C59As do this Poll and Poll Status Registers internally. Because of pin limitations, the 80C186/C188. These registers contain polling information. The format slave address has to be decoded externally. of these registers is shown in Figure 30. They can only INT1/SELECT is used as a slave-select input. Note that be read. Reading the Poll register constitutes asoftware _the slave vector address is transferred internally, but the poll. This sets the IS bit of the highest priority pending READY input must be supplied externally. M™! 0257525 oo4db12 768 = 80C186/80C188 Microprocessors. 45

(eaor Tyoe eee) 38H write; all other bits are read only. 2cH rupt control register corresponding to the bit. 7 channels have their own Control Register. Figure 32. Interrupt Controller Registers must be programmed at specified levels. The bits in the EOI register are encoded as follows: the priority level ofthe interrupt request. Interrupt Request Register value. All levels of lower priority are masked.

Allthe Enhanced Mode features are completely masked Figure 38) and the contents of a 9-bit counter. Figure when in Compatible Mode. A write to any of the 39 illustrates the origin of each bit. Enhanced Mode registers has no effect, while a read does not return any valid data. Refresh Control Unit Programming and Operation In Enhanced Mode, the 80C186/C188 operates wih Se" Programming ne MOSM and the CORAM reais- Power-Save, and DRAM retresh in addition to all the fers (See Flgutes 88 and 40), he RCUis enabledby set Compatible Mode features. ing the “E” bit in the register (Figure 41). The clock counter (T8-T0 of EDRAM) is loaded from C8-CO of CDRAM during T3 of the instructioncycle that sets the Entering Enhanced Mode “E” bit. The clock counter is then decremented at each This mode can be entered by tying the RESET output subsequent CLKOUT. signal from the 80C186/C188 to the TEST input. Arefreshis requested when the value of the counter has Queue-Status Mode reached 1 and the counter is reloaded from CDRAM. In The Queue-status Mode is entered by strapping the RD order to avoid missing refresh requests, the value in the pin Low. RD is sampled at RESET and if Low, the CDRAM register should always be at least 18 (12H). 80C186/C188 reconfigures the ALE and WA pins to be Clearing the “E” bit at anytime clears the counter and QS0 and QS1, respectively. This mode is available on stop refresh requests, but does not reset the refresh the 80C186/C188 in both Compatible and Enhanced address counter. Modes. POWER-SAVE CONTROL DRAM Refresh Control Unit Description . The Refresh Control Unit (RCU) automatically gener- | Power-Save Operation ates DRAM refresh bus cycles. The RCU operates only The 80C186/C 188, when in Enhanced Mode, can enter in Enhanced Mode. After a programmable period of a power saving state by internally dividing the processor time, the RCU generates a memory read request tothe —_—_clock frequency by a programmable factor. This divided BIU. tithe address generated during arefresh bus cycle frequency is also available at the CLKOUT pin. The is within the range of a properly programmed chip PDCON register contains the three-bit fields for select- select, that chip select is activated when the BIU _ing the clock division factor and the enable bit. executes the refresh bus cycle. The ready logic and wait . 7 states programmed for that region are also in force. If no All internal logic, including the Refresh Control Unit and chip select is activated, then external ready is automati- _the timers, has their clocks slowed down by the division cally required to terminate the refresh bus cycle. factor. To maintain a real time count or a fixed DRAM refresh rate, these peripherals must be reprogrammed If the HLDA pin is active when a DRAM refresh request when entering and leaving the Power-Save Mode. is generated (indicating a bus hold condition), then the . . 80C186/C188 deactivates the HLDA pin in ordertoper- The Power-Save Mode is exited whenever an interrupt form a refresh cycle. The circuit external to the is processed by automatically resetting the enable bit. If 80C186/C188 must remove the HOLD signal for atleast the Power-Save Mode is to be re-entered after serving ‘one clock in order to execute the refresh cycle. The the interrupt, the enable bit needs to be set in software sequence of HLDA going inactive while HOLD is being _—before returning from the interrupt routine. held active can be used to signal a pending refresh The internal clocks of the 80C186/C188 begin to be request. divided during the T3 state of the instruction cycle that All registers controlling DRAM refresh may be read and sets the enable bit. Clearing the enable bit restores full written in Enhanced Mode. Whenthe processorisoper- Speed in the T3 state of that instruction. ating in Compatible Mode, they are deselected and are ie " i therefore inaccessible. Some fields of these registers me a oinipur cleo teat design and as such cannot be written and are always read as Os. ° DRAM Refresh Addresses The address generated during aretresh cycle is deter- mined by the contents of the MDRAM register (see WM 0257525 0045616 303 a SSSSSSSSSSSsSSSsS 80C186/80C188 Microprocessors 43 .

v, Address Reset oo AI9-A16, 7AAC373 ROM AD15~ADO. = ™ Latch RESET a RES -e —I | ‘| A RD fd a 0 : | | a “a RAM ee | BRE SS eA SRDY +5V ARDY a NMI ~ Low . ee oe, ee MR OUTO es 74AC245 Tranncahor Hs _ K ~~~ 7-po K > Terminal DEN T OF oT vo oe PP Al eg a | |= vik = Ko De Interface a ed DRQo 13087D-044 Figure 43a. A Typical 80C186 System M@! 0257525 0049618 166 a 80C186/80C188 Microprocessors 51

¥. A15-A8 | naseos | Reset “ee AIS-A16, TN ancsr | ROM j ‘AD7-ADO TAAcars a RESET RES =r 800188 AD15-ADO RO Sd ae NO CTT} Program cory} ™ MCS3-MCSO|_— — SRDY _] +5V ARDY NMI 1 = L*] tow HOLD Cr— |) RAM ™ee TMR OUTO C] 74AC245 Transcaver Hs) K— 07-00» K > Terminal DEN T CE )> Serial ion Pe rt ‘Co | | Le ise Keo Di Disk Interface {ene ed DRQO 13087D-044 Figure 43b. A Typical 80C188 System Wm 0257525 0049619 Ole a 52 80C186/80C188 Microprocessors

PRELIMINARY amp &t OO Orrereorrrrn AMD ABSOLUTE MAXIMUM RATINGS Ambient temperature under bias Not to exceed the maximum allowable die temperature Voltage on any pin with or above these limits is not implied. Exposure to absolute maxi- SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS DC CHARACTERISTICS over operating ranges Ta= 0°C to +70°C, Taino = 40°C to +85°C, Veo = 5 V 410% a Parameter Description Test Conditions Min Max Unit Input Low Voltage (Except X1) ; t~—SY 05 02Vec-03 | V Vis [Clock Input Low Voltage (x1) ; t~—~SY 05 06 Vv Vm | Input High Voltage 0.2 Vec+ 0.9 | Voo+ 0.5 v (Except X1, RES) | Input High Voltage (RES) 30 | Veo# 0.5 Vo. | Output Low Voltage lou = 2.5 mA (82-80) 0.45 v lox. = 2.0 mA (others) vl low = -200 pA @ Voc -0.5 Veo v Voo- 0.8 loc | Power Supply Current | 25 MHz, 0°C Voo = 6.5 V8) 125 mA 20 MHz, 0°C Vec= 5.5 Vi) 100 mA 16 MHz, °C Veo = 5.5 V9) 80 mA 12 MHz, 0°C Voo = 5.5 V9) | 65 mA 10 MHz, 0° Vec= 5.5 Ve) 50 mA DC, o°c Voc = 5.5V 100 HA lo Output Leakage Current 0.45 V < Vout $ Veo"! 10 vA a @ 0.5 MHz 4 Vouo _ [Clock Output High loyo = 500 WA Voo 0.5 Vv in Cw _| Input Capacitance @ 1 MHz2) pF [Ge Jouiptor 10 Capacance @imiz | | | oF a Notes: © 1. Defauit priorities for the interrupt sources are used only ifthe user does not program each source to a unique priority te level, Pins being floated during HOLD or by invoking the ONCE Mode. © 2. Characterization conditions are: a) Frequency = 1 MHz;b) Unmeasured pins at GND; c) Vy @ +5.0 Vor 0.45 V. This a parameter is not tested. uy 3 Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open. = 4. ADOSMD, UCS, LCS, MCS0, MCSI, LOCK, and TEST pins have internal pull-up devices. Loading some of these I pins above lo = -200 wA can cause the 800 186/C188 fo go into alternative modes of operation. : ss SsSSSSSSSSSSSS—SSSSSS— 80C186/80C188 Microprocessors 53

Figure 44. Ic, versus Frequency 43087D-045

PRELIMINARY amp £1 Parameter Number with Description tine |e | mewonsrer Name # Name Setup Time [ass [$2 [ARDY Seup Tine | Tape | 2 [Dain Foe) = 28 [FOOK Valisiovale Day 2 [RD nace Dey | ewoe | 6UKOUT se Tine [ee | 28 ROA Onay to Reset Diy . CLKOUT High Time tousn a Status Inactive Delay _ toncTy 22 |Contro! Active Delay 2 tommy [5 | Timer Output Delay DEN inaave Daly Chip Select Hot tom Co, ave | oon | 8 Jouve seus Doay [we | HOLD Seto | toon | 39 [CLKINFall Time DRQO, DRQI Setup Time toxin 36 |CLKIN Period tua 10 | ALE Width CLKIN Rise Time - ~ 13 ‘Address Hold from ALE Inactive toc 46 |CLKOUT Fall Time —_ | tees 87 | RES Setup

50 ARDY Act Hot Tne 2

tou 5 Address Valid Delay tra 28 AD Inactive to ALE High tous 18 [Ares Flt ay te taci_[ 8 [olkoUTLowTine weer | 85 [ Wt nacive to DER rive ‘acer | 16 @@ 0257525 0045622 LO? 80C186/80C188 Microprocessors 55

SWITCHING CHARACTERISTICS over COMMERCIAL operating range Major Cycle Timings (Read Cycle) Ta = 0°C to 470°C, Voo = 5 V#10% [# | sym] Description | [win [Wax[ Win [Max] win [Max | ee a 7% [zbtax [atainvow wo) {_@ | | a {| [3 ns Status Active Delay |} 3 ete [4 | tess [Status inactive Delay 3 la {3 fast 3 [30 | ns | 5 | teuw [Adress Valid Delay 3 [a] [se] 3 | | re | © teu [Adress Hold a T [tay [Data Vals Daly [steps [fs [eto | [2 tow [Status Hold Time [io | ot | eT [ALE ActeDeley «dS | fs | cl hl [17 | tom [ALE Inactive Delay | 30 25 | 20 | 12) ta. | Address Valid to ALE Low" Tecn—18= 26 “tace-15= | Teun —15 = | \\ 20 11.25 ape fer eee Peer | Pree || Inactive" 20 11.25 ir} tue [Adsr Vaidto Oberg ep oT Po [15 tor [Adaross Float Delay | team=0 | 90 | tem=0 [25 [ tomno [20 [ns | His teen [Ohip-SelectAaiveboay [spat 2 fas| 3 [a [ns | yee mecca [RL fore] | Seam || ‘Command Inactive” 16.25 Te} Tacx [ChipSelect nacive Doky | 3 [s] a [aos fa | os | Hie tore DEN naciveto DTIRLw | 0 | | o | [0 J [ne | es [ar | ter [DEWinaciveDeay | 3 || 3 (af os | [221 ten ConvorAaiveDowy2 [| [fs [art [25 tay LOOK Valdtvais Ovay | 8 | 3 157 | [as | [24] tom [Adiress FoatoROAewe Te || oe [25 [tin [RBAciveDely || | oa [re | [= [oe forename || ae || 170 135 100 [zr | tame RO TcweOsay fs jets fa{ 2 [af] ere pemewwanar Pee [fee [wee | 30 12.25 Pepe reson fee] [eee] [eeg TTI 47.50 Notes: “Equal Loading “DEN, INTA, WR All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-25 MHz). For AC tests, input Vj, = 0.45 V and Viy= 2.4 V, except at X1 where Ves = Veo ~ 0.5 V. MM 0257525 OO45be3 S43 a 56 80C186/80C188 Microprocessors

SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Major Cycle Timings (Read Cycle) Ta = 0°C to +70°C, Vog = 5 VH10% Lp — |p [# [sym [Description [win [Wax] Min [Max| tover_[DatainSewp (A/D) TOTS «dT Sid va | t= ‘oxox [DatainHod(wo) Ts fis | tcsv_| Status Active Delay [25 [3 23 [ns | ‘ters [Status Inactive Delay _ [2] 3 [23 | ns | toray_|Address Valid Delay _ fes[ 3 (| 20 | [6 | tcuax | Address Hold __ o | | Data Valid Delay _ 3 | 8 | tcuox [Status Hold Time 10 [ [town [ALE Acive Demy | [70 | twa ALEWath iia} tea tesar] | [1 | tows [ALE Iacive Boay ao] fe ey [2 tau. [Adress Vado ALE Low? taannt=10] —_[iaae Se TO] | ne | 13] tuax | Address Hold from ALE Inactive" towcis10 = tcHe.-10= 5 ; [| 14 | taven__|Addr Valid to Glock High 0 = _o [ ns | 15 | tciaz [Address Float Delay touax=0 | 171 toax=0 [ ns | | 16 | tcicsy |Chip-Select Active Delay 3 _ 3 | 77 | foxx | Chip-Select Hold from teicH—10= [| teicH-10= 5 Command Inactive* 10 | 78 | toicax |ChinSlectinacivoBoay | 3 [a | 3 | w [ra | | toxo. [DEW InacivetoDTALow fo | |e | [ns] Let ee fe [sea fs | 21 | tovoex_ [BEN inactive Dlay [fe [3 8 Fs | 22 | teuctv_| Control Active Delay 2 3 feel 3 | 20 | ns | 23 | tcuy _|LOCK Valid/invalid Delay “3 3 [18 [ns | [24] taza. [Address Float to RD Active 0 0 [| teint | RD Active Delay ~~ 3. | 27 3. 24 Ba tata [RD Pulse Width “2tec1-20= | | “atera-15= | 80 65 [27 | ‘eins |AOtaaveeuy fs fae [3 te i a i Kaa an [tua-10=30 |] ns | Notes: “Equal Loading All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CG, = 50-100 pF (10-25 MHz). For AC tests, input Vy = 0.45 V and Vjy = 2.4 V, except at X1 where Viy = Voo -0.5 V. Mi 0257525 o049b24 4aT me 80C186/80C188 Microprocessors 87

80C186/80C188 Read-Cycle Waveforms ty te ts i CLKOUT \\ ////) ~ ol | 169 E/AFSH ‘BHE/RFSH Atarge MOSS ee ony) Kaew (806188 only) re i Ot T]

4 AS "©

ALE ) Ce te Ft | | (coche on eral | | €8) Fre TER Rese Gap FOE 301 6 | JY TCS, MCS, USS, ® BGS (Note 2) iD) J @ ® i DEN a (Note 3) DTA \\ Ky @ (ote 5) fe] (2) @) note 4) en ED TOCK A A Notes: 1. Status inactive in state preceding t. 2 Itlatched, At and A2 aro selected instead of PUSS and PCSB, only texcsy is applicable. 3. For write cycle followed by read cycle. 4, 1, of next bus cycle. 5, Changes in t-state preceding next bus cycle if followed by write. M@™ 0257525 O049b25 316 mm a 58 80C186/80C188 Microprocessors

SWITCHING CHARACTERISTICS over COMMERCIAL Operating range (continued) Major Cycle Timings (Write Cycle) Ta = 0°C to +70°C, Veo = 5 V #10% [Preliminary a CL [# [Sym Doseription [in| Wax | Win [wax | ain a] Sialus Active Delay [sey sys] 3 vate] [eee fsaustece gy 3 | 3 [850 |r| eo or —s | 6 | toux [Address Hold 0 0 ee [8 tows [StausHed time 40 te to] | 9 | town [ALE Active Delay a |i a | po fee [Ae eee Peg Peay Pe] 85 65 475 toms [ALE Inactive Delay ao fdas | | 12 | tau [Address Valid to ALE Low* tanl8 = tory 15 = tovey—15 = Es emer eee [eee sel Te 29 20 11.25 as aS [3 fas =< | [se [estima | Ee | [Sag PB | Command Inactive* 34 25 16.25 | 18 | terse [ChipSelectinaciveDoay [3 as | a pao] s |=] w| tevew [Control Aetive Delay 1" [sae [sf a | 8 | 30_| teioox [Data Hold Tine i Control Inactive Delay"* | 3 {4s | 3s [or | 3 | at fos _| a GGG 170 135 100 30 21 12.25 = eee Sse ee ee 66 60 [= [Se [rmerrrermes Pear Peel [ee DF] 34 25 16.25 Notes: *Equal Loading All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-25 MHz). For AC tests, input Vi = 0.45 V and Vj, = 2.4 V, except at X1 where Vii = Veo - 0.5 V. ° M@ 0257525 OO49b2b 252 my 80C186/80C188 Microprocessors 59

SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Major Cycle Timings (Write Cycle) Th = 0°C to +70°C, Veo = 5 V#10% [Preliminary eee [oe sym Beseription [in Wax [in Wax] [3] tomy [Status Ave Delays TT CT | [oats [Stats inactive Delay | sf | Ps [os [tar lAdeross Vaid Delay [| os TT 20s | [oe [ti laddesstos Es | [7 [tao Joata Val Dey Sid eT | [eT ex |stausro Time [to [oe tte ALE Actvo Deley SP | [opt ALE actveDomy dS | | [a2 | tan YAderess Valdto ALE Low [uorton fo || tors-10 | | os | [13 tua [Adsross Hold from ALE naa” [ta10=10 | | wat0=5 | [ns | [a [two AddrVaidto Cookin | Ts [16 | tenoor |ChipSelectActve Delay [3 | a [3 | 2% | rs | Ae ee ‘Command inactive’ [ie tex ]ohi Select inactive Delay [3 | 2 fs | ve | | [18 toe [EN Inactive TRL |e] CT | | [20 [tere [ontotAaive Daly [3 | 2 | 3 | i [rs | [2s] teas cOoK valtivatis Belay [3 | 2 | 3s | 8 [os | [30 | tum —[OatarodTime +d 3 TdT Cd | [cat | tevenConolinacive Daly |e | 2 | 3 | a0 [ns | |e Pulse Width Bteur20=80 | | Ayo. -15 = 65 | 33 | WR Inactive to ALE High” taa14=6 | | tao-10=5 [oe | tata Hold ater eet =38 || toto= 00 | [ns | [35 | twoex [WA inactive to DEN Inactive | tea-t0=10 [| taans=10 | ns | Notes: *Equal Loading Alltimings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-25 MHz). For AC tests, input V, = 0.45 Vand Vj, = 2.4 V, except at X1 where Viv = Voc - 0.5 V. mm 0257525 oo4usbe? 195 a a 60 80C186/80C188 Microprocessors

—retiinary a 80C186/80C188 Write-Cycle Waveforms i te ty te | | are | CLKOUT a _ © @) oT ep | Ney BHE/AFSH BHE, RFSH ANS-AB os al | F ok || +] TTT ¥re ne ALE © = C8) ait? si AD15-AD8 le [A] a) F I ares PCS (Note 2) Ht a) ro ovat le} (Note 3) (| @ @ ote 8). My _ ® @) (Note 4) COCK V VY Z\\ Z\\ Notes: 1. Status inactive in state preceding t. 2, Iflatched, A1 and A2 are selected instead of PCSS and PUSS, only tercsy is applicable. 3. For write cycle followed by read cycle. 4. 1, of next bus cycle, 5. Changes int-state preceding next bus cycle if followed by read, INTA, or halt. | 0257525 0049628 O25 my a me 80C186/80C188 Microprocessors 61

SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Major Cycle Timings (Interrupt Acknowledge Cycle) Tay = 40°C to +85°C, Voc = 5 V#10% a ee a Sm [| __Deseription | win [max] win [Max] min [wax 80C186 General Timing Requirements (fisted more than once) [rT um foams Ts | f= | | = | Trl [zoo lowanvoeao) |e | |e | [= | Ie] [stow [Sauencieony Ts [ef = [=[ 8 [afr| [ass [Sausineaveovey | a f#| sie] = |» [ms Ls [tam laddeesvertoaly | 9 [w{ 2 je] 9 [as [m| stem [asst *e | fe | [ e | [| 7 [er [oma ons | a fe] fete [a [oe fe | toon [euustoetinn fo | | | | | fo [stom [NeAawony | jot is af] oj wa acwon —eacteeee | [tmactenes | [txacte-er | [| 12| tau [Address Valid to ALE Low* toi 18 = toc 15 = tow 15 = Leow’ | [eee | [eet | [| Fc ad a an poe | fe Pe | 18 | touz [Address Float Delay [temo | 90 | tum-o | 25 [ tann0 | [ ns | [ao [tren loontciaave dow |e j#{« j@7{ 5 [atm | 21 | tovoex | DEN Inactive Delay 44 37 flee feowmmomy | “Te et i [22 [tw [oonroiacivedekya- | os [ae [ 8 | a | | rs | [2 [tow [COCR Vaidinvataoowy [sao |e | a | fe] [rT toren [contotinacivedsey” | 3 if 3 [a] 3 ia|n | Notes: *Equal Loading All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. Alloutput test conditions ara with G, = 50-100 pF (12.5-25 MHz). For AC tests, input Vy = 0.45 V and Vy = 2.4 V, except at X1 where Vv = Voc — 0.5 V. WM 0257525 0049629 Th) a 62 80C186/80C188 Microprocessors

PRELIMINARY amo © SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Major Cycle Timings (Interrupt Acknowledge Cycle) Ty =0°C to +70°C, Voc = 5 V#10% a ee a eC 1 | toveu [Data in Setup (A/D) Z rl.» | ee ce ee a fe [ets sstvesneoony | a [a 5 | tcuay_ [Address Valid Delay [ 25 | 6 | tux | Address Hold | [oo | 7 | tery [Data Valid Delay [a] 3 | fe | oox oitnbadtne J ve | [wo } [| be [tea [AA o0uy | fof ea [wewon—fsaraoe] —[earwea7] [| [11 | toma. [ALE inactive Delay [|| 12 | tana [Address Valid to ALE Low terc10 = 10 torr = 10 oo 13] tiax [Address Hold from ALE inactive” | toyci—10 = 10 tavon Addr Valid to Clock High | ° test} fe] [| eve [atau PeetOsey | tame [7 | mr | fv | [| we betimcnenotmion fe | [| [| fs] sir [ows sctwoaiy = [ae | |e [| tevoex _|DEN Inactive Delay efor freiioseesy fet [| la [ew [eousacimoaye= [a [wef fm || | 23 | tor [LOOK Valia/invalid Delay 2} tele] ea Notes: “Equal Loading “DEN, INTA, WA All timings are measured at 1.5 V and 100 pF loading on CLKQUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (12.5-25 MH2). > MM@ 0257525 0049630 733 mm 80C186/80C188 Microprocessors 63

80C186/80C188 Interrupt Acknowledge Cycle Waveforms tr tb ts te CLKOUT (ote +) S55 @ ___lanrag e A19/S6-A16/S3 EK AIS-AI6 BHE, Sé"63 r ere | ana ache ALE ® ea ~ A15-A8 (800188) ro) | @) (woe 2 AD15-ADO (800186) PTR) ‘AD7-ADO (80C188) @ NTA Seo | 4 ° DEN i) (Note 4) ova | i) = @ Wote 6) ke TOCK (Note 5) CJ 6) 4 @ Notes: 1, Status inactive in state preceding t 2. The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to tex (min). 3. TNTA occurs one clock later in Slave Mode. 4. For write cycle followed by interrupt acknowledge cycle. 5. TOCRiis active upon t, of the first interrupt acknowledge cycle and inactive upon te of the second interrupt acknowledge cycle. 6. Changes in t-state preceding next bus cycle if followed by write. {MM 0257525 0049631 617 ee 64 80C186/80C188 Microprocessors

SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Software Halt Cycle Timings Th = 0°C t0 70°C, Veo = 5 V 410% PT Prtininary | somes temiiz tome [#[ sym [Description [min [Max[ in [Max | in| Wax [3 | ty _[Save Acie Ose 2 [#8] = =] 3 [a [re Status Inactive Delay 3 | 46 | 3 fas [ 3 | a0 | ns | Address Valid Delay 3 [a] 3 | eee ea so [72 | tom. [DEN naciveto OVAL Po fo fr | [22 | Toren [Contol have Belay ee par ae | ee eee Le [#1 sym | dewenion [win [wax] win |] Status Active Delay [2] 3 125 [ns | | 5 | taw [Address Valid Delay } 3 [as | [ ne | ee [70 [tow [ALE Wa eee] ae | [it tou [AEheaveony fifa] ff] [727 tose [DEW rasvet» VALow [8 fo | vo | [22 | tower [Control Active Delay 2 See | 8 20 [as | Notes: *Equal Loading All timings are measured at 1.5 Vand 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (12.5-25 MHz). For AC tests, input Vi, = 0.45 Vand Vjy = 2.4 V, except at X1 where Vij = Voc - 0.5 V. : MM 0257525 0049632 Sob me

80C186/80C188 Software Halt Cycle Waveforms cuxkout a s as O- = @ A19/S6-A16/S3, od | AD 15-ADB/A15-A8, Invalid Address ‘AD7-ADO ALE 7) DEN (Note 1) oma Note: 1. For write cycle followed by halt cycle. a A A Clock Waveforms @ a) CLKOUT © @ : Mm 0257525 0049633 442 ml a 66 80C186/80C188 Microprocessors

SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Clock Timings Tr = 0°C + 70°C, Veo = 5 V 410% | anne [ro rr as J Bessrption [Win Wax] Win [Wax] Win Ta CLKIN Requirements Measurements taken with: external clock input to X1 and X2 not connected (Float). . | 36 [tom [CUKINPeriod 80 Tas | [37 [tao [LKIN Cow mers ve 20 tet [58 | tore JOLKINHigh Time .5v@™ [a0 te ts CUKINFallTimeds= FOV PP] r | [40 | tonn [GLK Rise Timeso—a5v 8 PP re | CLKIN to CLKOUT Skew rs ee ee ee [42 | cua. [CLKOUT Period [too aa a8 431 towcy | CLKOUT Low Time OS tca—6 O5taa—5 O5toa—5 ns Ci= 100pFe 0.8 tora 8 05 tora -7 0.5 tev —7 447 ‘exe |CLKOUT High Time 05 tora —6 OBtaa-5 O05 toc —5 ns Ci= 50 pre =44 =35 = 26.25 C.= 100pF OStaa-8 OS toc =7 05 terc,—7 48 | toncre |CLKOUTRise Time 1.0-35V [| ‘10 | tof 10 | 46 | toizo.1 [CLKOUT Fall Time 35-1.0V [10 | fof i | ee eee ee [# [sym [Description [Min ___[Wex[ Win [Max] CLKIN Requirements Measurements taken with: external clock input to X1 and X2 not connected (Float). CLKIN Period ps 20s] [97 | exo [OLKIN Low Tine Wes a | CLK High Time 18V@_— [8a | GLKINFal Time s5=t0V fT | CLR Rise Time .0=38V fs 8 | | CLKOUT Timing [41 | texo [ELKIN to CLKOUT Skew ee [18 [ns | ‘eeu | CLKOUT Peviod [so on a 4 | teicn | CLKOUT Low Time OB tic. — 5= 20 OS taa-5= 15 | Ci= 50 pro x= 100 pF [ostaa-7 18 [ [Ad 44] toa. [OLKOUT High Timo O5 tera —5 = 20 OS taa-5= 15 C= 50 pre [c= 100eF) ——fosta=7-t8 [fA id [45 | tance [GIKOUTRve Tine tO-35v [| 8] C*d | [46 | tases [CLKOUTFallTimes5-tov [Te fd 8 [ns | Notes: All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. ‘Alouput test conditions are mth G = 60-100 pF (10-25 Mii) For AC tests, input Vj, = 0.45 V and Vs, = 2.4 V, except at X1 where Vi) = Vac - 0.5 V. 1. letck and texick (CLKIN Low and High times) should not have a duration less than 40% of toxin. 2. Tested under worst case conditions: Vec = 5.5 V @ 25 MHz, Ta=70°C. 3. Not tested. 4. Tested under worst case conditions: Vee = 4.5 V @ 25 MHz, Ta =0°C. + MM 0257525 0049634 329 = as 80C186/80C188 Microprocessors 67

SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) Ready, Peripheral, and Queue Status Timings Ta =0°C to +85°C, Voc = 5 V210% Pretiinary Parana ee [* [sum [Description [min Jax [win [wax] win __ [Max] [27 tower [SROY Taeten Soup tre” [ET 7 eT [8 [rs [45 | tasme [SAOV Tans oa TineT [vs] | | fs | 49 | tarvon | ARDY Res. Transition Setup 15 15 [e[oe fire remrsne PT Te TT eT le [| ean [AROY AaivowgTmeT [es | [51 [urvcre [ARDY hacine HolingTine [|e | [| [2 [meme [AROVSeup Tine” ast | Yo | [S| wor Seater [| TT P| TMR IN, TEST/BUSY [=] tence _[OFG0, OFT SoupTime™ |e | | TP | [55] tow [Tmeroupabeey [| «dT [ «dT | [Se [towosy [oveve Satusoeay | taf i*| —~*f tr} eee ee [# [sym [Description [in [ax[ win [Max [47 | ‘saver [SROY Transition Soup time? [10 [TT 0 TT ns | [22 [teeny [SROY Warsi Hoatine™” [vo || | [rs tarycu | ARDY Res. Transition Setup. [= [ror laaeewewensee Pe eT [50 [texan [ARDY ActiveHoid Time? [of [0s | [81 [tanvere [ARDY InactiveHoldingTime [30 | [0 | ns | [82 [amnce [ARDYSetup Time? Ts TTT ns | tinvc | Peripheral Setup(): INTx, NMI, 10 10 [= [we ratictesimoor™ [TP || [=| wer [ORO ORGY Seupting®™ [ve || Tie [55 | tonosy JOuove Stas Dey | sd | +d | ve | Notes: All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-25 MHz). 1. To guarantee proper operation. 2. To guarantee recognition at clock edge. WM 0257525 0049635 2bS me a 68 80C186/80C188 Microprocessors

Synchronous Ready (SRDY) Waveforms | ty Ort, OF t; | tw Or te | tw OF te | te | CLKOUT SRDY ee Asynchronous Ready (ARDY) Waveforms | ty ort, ort, | tw OF te | tw or ts | & | CLKOUT ARDY (Normally Not Ready System) ARDY (Normally Ready System) @ (2) W@™ 0257525 OO45b3b 1TL a SSS 80C186/80C188 Microprocessors 69

Peripheral and Queue Status Waveforms iS) INT3-INTO, NMI, TEST, TMRIN g || DRQo, DRQI TMR OUT =" i) QSo0, QS1 RESET Waveforms © @ RES cuxour XX __/ @ @ RESET M™ 0257525 0049637 038 mm ee 70 80C186/80C188 Microprocessors

SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued) RESET and HOLD/HLDA Timings Th = 0°C to +85°C, Voc = 5 V#10% Priory [omnes [vere tome | [# | sym | description [min [ex] win Tmax] win [ax | [ 87 | tres [RES Setup re a a bse te roto Ses ———] ss | 2] J [| ns | fists [patos Pear Oaay ———[ 0 [we] 0 fae | ota [Stow [Address Val Delay ‘| 8 jaf 3 | a] 3 | = | ae | [et [tas [ResetDoay Cd Cd Cr | ee 63 | teyee [Command ines FoatDelay | ‘(ao ——i aa | | 28 [ns | a a a (aftor Float ee ee a [# [Sym | beccipion [win [Wox| Win [War] [27] teen [Resse Od [32 | ae, HOLD Sena) 0 te | | [1 [ee [Aston Foster fae Poo [= [tow [Actress VaisDaty [8 fas [8 oe | [er] tao [ResetDewy dT C*d eps fe eax ay ——- se | a — fr [| | 63 | tcncz | Command Lines Float Delay Fe tcxey [Command Lines Valid Delay [| ee [erren aL |" Notes: All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-25 MHz). For AC tests, input V_ = 0.45 V and Vy = 2.4 V, except at X1 where Vy = Voc - 0.5 V. 1. To guarantee recognition at next clock. Me 0257525 0049638 T?4 80C186/80C188 Microprocessors 71

80C186/80C188 HOLD/HLDA Waveforms (Entering HOLD) | hort | t | ti | CLKOUT S\\ Sf’ HOLD $ HLDA s AD15-AD8/A15-A8, 5 AD7-ADO, DEN i A19/S6-A16/S3, RD, WA, a) BHE/RFSH, DT/R, S2~S0, S TOCK 80C186/80C188 HOLD/HLDA Waveforms (Leaving HOLD) en ra ee | CLKOUT HOLD ae HLDA AD15-AD8/A15-A8, AD7-AD0, DEN ao Wa @ A19/S6-A16/S3, RD, WR, S BHE/AFSH, DT/A, S2-S0, LOCK M™@ 0257525 0049639 900 me 72 80C186/80C188 Microprocessors

SWITCHING CHARACTERISTICS over INDUSTRIAL operating range Major Cycle Timings (Read Cycle) Taino = ~40°C to +85°C, Veo = 5 V +10% J Preliminary ee eee [eS | Deseripiton | win [Wax [Win [wax] Win [ax] [1 toa [DatanSeup@o) | 18] [8] J] 8] Je | [2 tae lOmtaina wo) | | | 3 | [3 [re | [3 | tour [StausAeiveOsay ——s|_—S S] Te | [3 [asf spas | a of | [5 [tw [Adress Vaid Doly [a fas | 3 fae re | [| tac [Address Hoa ae ee 3 [ae fs re | [e| tox [Sia Ho time fo | | | | 0, | Leela have aay fe st a | ec cd a M1 {tom [ALE Inactive Delay [80 | 20 [patie] [eae | omar [| 26 20 N25 | 13 | tux | Address Hold from ALE touor-15 = touc-15 = | ac a a [4 tacn|Adr Vaidto Cio vigh [0 | | 0 |_| 0 | [we] [15.1 tue [Ades Fst Dany ‘Ganz PS eee OT Tae | | Command Inactive* 16.25 [is Tex |onip-Soect inacive Dewy [a [as | a |] 8 [2 we] [12 | toc. [DEW aciveto OTL fo | fo | _- 0} [re] [20"| Yevew [ContelAaive Doky = [a [af a} |e [are | [21 tere BEN hactve Dey | a] # | a ar | 9 [a Je | [22"| tow [Contr Asive Deay2= [a _| «| a [er] a} 31 |] [25 | teuv [COOK Vatdinvaia Delay | 8} 0] [or | 3 15 [ns | [24 | tum [Address Foatio AD Acive [0 | J 0 | _] | [25 "tam | RD Active Doay [taf 3s for} 3 tae a \\ 170 135 100 [a7 | am |ABracive Doty | a | w@ |» |} sai [ws 12.25 Notes: “Equal Loading All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-16 MHz). For AC tests, input V;, = 0.45 V and Vp, = 2.4 V, except at X1 where Viy = Voc - 0.5 V. M@™ 0257525 OO45b40 bee

80C186/80C188 Read-Cycle Waveforms t to ty & | | w | | CLKOUT BHE/AFSH BHE/RFSH arorse-ar61so 83 on) Se (800188 only) re ce ot] Anahen ALE @ O (80C188 only) A Ql | | (z) a, oF Fy ho4 186 on (pais) aetna | Mt __ly eS) BGS (Note 2} | (P) y DEN t | (Note 3) DTA \\ ke @ ote 5) ® @ wote 4) Xo =F TOOK a A Notes: 1. Status inactive in state preceding ty. 2. Iflatched, At and A2 are selected instead of PCSS and PCS6, only texcsy is applicable. 3. For write cycle followed by read cycle. 4. t, of next bus cycle. 5, Changes in t-state preceding next bus cycle if followed by write Mi 0257525 0049641 5b 74 80C186/80C188 Microprocessors

SWITCHING CHARACTERISTICS over INDUSTRIAL operating range (continued) Major Cycle Timings (Write Cycle) Trwno = ~40°C to + 85°C, Vec = 5 V 10% LE Prliminary ee ee [# [| Sym [Description [win [Wax] Min [Max[ Win | Wox| [3 | teiey [StawsAcwveDemy | 3 [a] 3s [se] s [a] | [4 | tecox [Status inactive Delay [8 [a] 3s [ss] 3 | 90 |_| [5 [aw [Adsross Vaid Delay ——S=«dSCi fa |p ff |e [eta [AddeessiHeid SST [ore] | 7 | txov [DataValidDolay ao | s 6 | | 33 | ns | [8 | towox [StausHodTine ‘| 10 | | 40 [| [10 |_| re I dO Ga 85 65 47 [| ta [Ae raaveDey |i |e | ie Meester [Mesh | [Meee | fea | | | 26 20 1 Pe ee) fe) fe] 29 20 1 | 74 | Wwcu [Adar Valito CockHigh [| 0 | | o | | 0 _| [16 | ese [ChipSelet Active Dey | __3 | @| 9 [a | 3 | o | ms _| I a Command Inactive" 34 25 16 [io | force [Chip-Select inactive Delay | 3 [ae | a [ao | 3 [as | m_ [16 | tox [DEN inaciveto OTHALow [0 | | o | | o |_| w=] [20 | toverr [ConvolAaive Dey [a [#| 9 [#7 | a [a] | [23 | tay [COCK Vaidnvals Delay | 3 | [a [a7 | 3 [as | ms _| [20 [tanox [Oaanowtime [8] .s |] 3 | |= | | 31 | teverx [Control inactive Delay* | 8 | a4 | fo | 8 at | os [| tom [errr [Peso [Pate] [Paver] | | 170 135 100 Pe [ee frmesremrr preg fre Pa | 30 21 12.25 a nc Ma 66 60 42.5 [= [mo [remeron Pgs] Peay Pea] | 34 16.25 Notes: *Equal Loading All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-16 MHz) For AC tests, input V, = 0.45 V and Vjy = 2.4 V, except at X1 where Vs) = Voc — 0.5 V. m™ 0257525 OO4Sb42 YTS i 80C186/80C188 Microprocessors 75

80C186/80C188 Write-Cycle Waveforms t ns es | | . CLKOUT a © @ 250 rT ae BHEAFSH SHEIRFSH aroe me Kine XK BHEFSHse-so ea ee ee a 1: 8 (eoctdi ont) hoy i oly | +11 Anan ne ALE 6} 5 AD15-AD8 @ Van |) ssid. 15-1 (soetes on) CaF o HEH Pore | coma ita. BGS (Note 2} @) ay, @ | > (8) DEN @ } oun G9 ke} (Note 3) ( (a) ®@ wore 5) I (Note 4) Tock y, 2) el - Wy, XX Notes: 1. Status inactive in state preceding 4. 2. Iflatched, A1 and A2 are selected instead of PCSB and PCSB, only teucsy is applicable, 3. For write cycle followed by read cycle. 4. t, of next bus cycle. 5. Changes in t-state preceding next bus cycle if followed by read, INTA, or halt mM 0257525 0049643 331 76 80C186/80C188 Microprocessors

PRELIMINARY amo &A SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (continued) Major Cycle Timings (Interrupt Acknowledge Cycle) Ty = 40°C to 485°C, Veo = 5 V 410% ee ee ee [= [Sim [sein | nur] ne] ine a Fe eS femsnceee —— 3 -|- | + + F = 4] [2 | [Sie Aa ny ee Status Inactive Delay [as] 3 35 eeiees— eee [7 tor [oaavasonny | sw] sw] 3 J | [ef [een tow | ve] | | tow [ALE Active Delay | sf 0 — | a fas | . tin [ALE Width [tert = 85 2] | | t15 = 47 [ ns | [11 | tows _ [ALE Inactive Delay poe | ns | twu | Address Valid to ALE Low* fees | | | 13] tux [Address Hold from ALE inactive [weg | fears [| 29 20 ch ed ee [ 15 | touz | Address Float Delay | tom=0 | 30 | toux= 0 [25 | tan=0 | 20 | as | [ 19 | tox. [DEN inactive to DT/A Low" ; oo | | 0 | | oO [rs | DEN Inactive Delay 3 3 37 3 31 (Non-Write Cycles) touy _ |LOGK Valid/Invalid Delay a al] 3 | 35 3 ee ee ec Notes: “Equal Loading All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-200 pF (10 MHz) and C, = 50-100, pF (12.5-20 MHz). For AC tests, input V, = 0.45 V and Vy, = 2.4 V, except at X1 where Vpy = Veo ~ 0.5 V. : MP 0257525 oo4se4y 275 80C186/80C188 Microprocessors 77

80C186/80C188 Interrupt Acknowledge Cycle Waveforms tw CLKOUT (Note ty 52-50 @® , statue WU A a © mE: ISA Cit) Ga A19/S6-A16/S3 F AIS-A16 BHE, S6-$3 D r ang ana aawe ALE + | o A15-AB (800188) [| (2) (Note 2) ‘AD15-ADo (80186) ‘AD7-ADO (800188) @ PTA) . Ez oN @ (Note 4) oR \\ @ — @ (Note 6) >] Tock (Note 5) eS 5 Notes: 1, Status inactive in state preceding t, 2. The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to texox (min). 3. TNTA occurs one clock later in Slave Mode. 4. For write cycle followed by interrupt acknowledge cycle. 5. LOCRiis active upon t, of the first interrupt acknowledge cycle and inactive upon b of the second interrupt acknowledge cycle. 6. Changes in t-state preceding next bus cycle if followed by write, Wm 0257525 OO49b4S 104 mm i SSeS ' 78 80C186/80C188 Microprocessors

PRELIMINARY amo &l SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (continued) Software Halt Cycle Timings Th = 40°C to 85°C, Veo = 5 V 410% J Prtiinary [# [sym | Descripon [win [wax] win [max] win Tox [= [tor [Saueaciecoy Ts Te] 8 [e] 8 a]a| [+ Toa [atnsnaaveovey | 3 [#] 2s [o[s [»[m] [=| em latiecsvaitoeiy | fw {s [xe{ 2 [=o] To] twa [ALE Width ; too-15= 85] | toxoi-15 = 65 tooi-15 = 47 ns [72 | to. [DEWiracivero OTRLGW [oo re | [22 ew [Conroracive Dey [3 et 3 perf 3 fat fos | Notes: “Equal Loading All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-200 pF (10 MHz) and ©, = 50-100 pF (125-20 MHz). For AC tests, input Vy = 0.45 Vand Viy = 2.4 V, except at X1 where Vyy = Voc - 0.5 V. M™™ 0257525 OO4IbYb O4O me 80C186/80C188 Microprocessors 79

80C186/80C188 Software Halt Cycle Waveforms 3250 © (0) A19/S6-A16/S3, ar AD15-ADB/A15-A8, Invalid Address ‘AD7-ADO rt ALE ) DEN (Note 1) oTv/R Note: 1. For write cycle followed by halt cycle. Clock Waveforms x1 @ CLKOUT M@ 0257525 OO45b4? Ta? Me 80 80C186/80C188 Microprocessors

PRELIMINARY amp &A ———— Oe errr AD SWITCHING CHARACTERISTICS over INDUSTRIAL operating range (continued) Clock Timings Trai = “40°C to +85°C, Veo = 5 V 410% oe [#{_svm [description [win [max] win [wax] win Tax] CLKIN Requirements Measurements taken with: external clock input to X1 and X2 not connected (Float). [26] texw [CUKIN Period T8082 | [s7 | toc [GLKNLow Time teva [ao | fe] tt ds | [98 | tener [OLKINFigh Time 15V@_—— a0 fp te] tt | CLKINFalTimesé-10v || 8 {fs || 8 fas | [40 tan [GLKIN Rise Time 10-36V_ [| s fs || s | ms | [4 | teco [CLK CKOUT Skew Cid] ir | | 42 |" tc. [CLKOUT Period a a toc |CLKOUT Low Time 05 tov 6 OS tac—8 05 tec— 5 C= 50 pre =44 =35 = 26.25 C= 100 pre OS tog—8 O5taa-7 OS taa-7 =42 =33 = 24,25 44 tour |CLKOUT High Time 05 tea-6 OS taa—5 05 taci—5 C= 50 pre) =44 =36 = 26.25 Ci= 100 pF(4) 05 te-8 05 tac-7 0.5 teve.-7 =4 =33 = 24.25 45 | tome |CLKOUT Rise Time 10 1.0-3.5V 48 | towoir | CLKOUT Fall Time 10 3.5-1.0V Notes: All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C, = 50-100 pF (10-16 MHz). For AC tests, input Vi, = 0.45 Vand Vy = 2.4 V, except at X1 where Vij = Voc - 0.5 V. 1. texcx and toycx (CLKIN Low and High times) should not have a duration less than 40% of fox. 2. Tested under worst case conditions: Vec=5.5 V@ 16 MHz, Ty=70°C. 3. Not tested. 4, Tested under worst case conditions: Vec=4.5 V@ 16 MHz, Ty =0°C. 5. Toguarantee proper operation, 6. To guarantee recognition at clock edge. 7. To guarantee recognition at next clock. Wm 0257525 0049b48 913 a SSSSSsssSs 80C186/80C188 Microprocessors 81

SWITCHING CHARACTERISTICS over INDUSTRIAL operating range (continued) Ready, Peripheral, and Queue Status Timings Taino = 40°C to 485°C, Voc = 5 V +10% Le [# [sym [Description [min ax] win [eax] win [max Ready and Peripheral Timing Requirements taavon [ARDY Res. Transition Setup 15 Time® [50 | toum [ARO AciveHowTimes) [ts | Ts Ts ns | [st | won [ARDY mecieRatie tine [| | = | | 8 | [we] fs [ ma lanorenntnos | | || | = | |e Peripheral Setup(®): INTx, NMI, 15 TMR IN, TEST/BUSY Peripheral and Queue Status Timing Responses Alltimings are measured at 1.5 V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with G, = 50-100 pF (10-16 MHz). For AC tests, input V; = 0.45 Vand Vu = 2.4 V, except at X1 where Vy = Voc - 0.5 V. Notes: 1. teack and tuck (CLKIN Low and High times) should not have a duration less than 40% of txw- 2. Tasted under worst case conditions: Voc=5.5 V@ 16 MHz, Tan70°C. 3. Not tested. 4. Tasted under worst case conditions: Voc=4.5 V@ 16 MHz, Ty =0°C. 5. To guarantee proper operation. 6. To guarantee recognition at clock edge. 7. To guarantee recognition at next clock. mm 0257525 0049649 BST 82 80C186/80C188 Microprocessors

PRELIMINARY amo &t PRELIMINARY AM Synchronous Ready (SRDY) Waveforms | twort, ort, | ty ort, | tw OF ty | tu | CLKOUT SRDY TO Asynchronous Ready (ARDY) Waveforms | ty ort, ort; | ty Or te | tw Or ts | t | CLKOUT ARDY (Normally Not Ready System) ARDY (Normally Ready | 2) M@™ 0257525 OO49650 57) me SSSSsssSsSsSsSSsSsSsssSSSSsSsSSSSSSee 80C186/80C188 Microprocessors 83

Peripheral and Queue Status Waveforms INT3-INTO, NMI, TEST, TMR IN e. | | DRQo, DRAI TMR OUT QSo, ast SSS RESET Waveforms xt RES cuour KX _/ © @ RESET mM 0257525 0045651) 408 mm 84 80C186/80C188 Microprocessors

SWITCHING CHARACTERISTICS ova INDUSTRI SWITCHING CHARACTERISTICS over INDUSTRIAL operating range (continued) RESET and HOLD/HLDA Timings Taino = 40°C to +85°C, Veo = 5 V 10% [# [Sm | oeecipion | win [Woe] win [ux] win [won] RESET and HOLD/HLDA Timing Requirements [= | tan [RES Sep l= ~.], «= |] = [Je] [se twa [Housewife | Pst | [15] tour [Adios Fossey | 0 [| 0 [mo lat] RESET and HOLD/HLDA Timing Requirements [st [Remon |i] i] 64 | toucy [Command Lines Valid Delay 44 36 32 (alter Float) Notes: All timings are measured at 1.5 V and 100 pF loading on CLKOUT unless othenwise noted. All output test conditions are with C; = 50-100 pF (10-16 MHz). For AC tests, input Vi = 0.45 Vand Vy = 2.4 V, except at X1 where Vyy = Veo — 0.5 V. 1. fexcx aNd toyex (CLKIN Low and High times) should not have a duration less than 40% of tox. 2. Tested under worst case conditions: Voc = 5.5 V @ 16 MHz, Ty=70° C. 3. Not tested. 4, Tested under worst case conditions: Voc = 4.5 V@ 16 MHz, Ty =0°C. 5. To guarantee proper operation. 6. To guarantee recognition at clock edge. 7. To guarantee recognition at next clock. WB 0257525 OO49bS2 344 me OO SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS— 80C186/80C188 Microprocessors 85

80C186/80C188 HOLD/HLDA Waveforms (Entering HOLD) fork t 1 ti 1 CLKOUT S\\_/J* HOLD 5 HLDA s EF ® AD15-ADS/A15-A8, ‘AD7-ADO, DEN i A19/S6-A16/S3, FD, WR, —$ BHE/RFSH, DT/R, S2-S0, re TOCK ® oe 80C186/80C188 HOLD/HLDA Waveforms (Leaving HOLD) end ne ee | CLKOUT @&) HOLD HLDA s AD15-ADB/A15-A8, R | 4 AD7-ADO, DEN _ ) A19/S6-A16/S3, RD, WA, s BHE/AFSH, DT/A, S2-S0, TOCK M™@ 0257525 0045653 280 a a 86 80C186/80C188 Microprocessors

PRELIMINARY amp &4 eA EXPLANATION OF THE SWITCHING 80C186/C188 EXECUTION TIMINGS SYMBOLS A determination of 80C186/C188 program execution Each timing symbol has from five to seven characters. timing must consider bus cycles necessary to prefetch The first character is always a ‘t” (stands for time). The instructions, as well as the number of execution unit other characters, depending on their positions, stand for cycles necessary to execute instructions. The following the name of a signal or the logical status of that signal. instruction timings represent the minimum execution The following is a list of allthe characters and what they __time in clock cycles for each instruction. The timings stand for. given are based on the following assumptions: A Address @ The opcode, along with any data or displacement ARY Asynchronous Ready Input required for execution of a particular instruction, c Clock Output has been prefetched and resides in the queue at cK Clock | ‘ the time it is needed. Input cs Chip Select No wait states or bus HOLDs occur. cT Control (DT/A, DEN... | All word-data is located on even-address D Data nna ) boundaries (80C 186 only). — Alljumps and calls include the time required to fetch the DE DEN . opcode of the next instruction at the destination H Logic Level High address. L Logic Level Low or ALE All instructions that involve memory access can require ° Output ‘one or two additional clocks above the minimum timings utp shown due to the asynchronous handshake as Queue Status (QS1, QS2) between the bus interface unit (BIU) and execution unit R RD Signal, RESET Signal Ss Status (2, 87, 50) With a 16-bit BIU, the 800186 has sufficient bus pertor- on mance to ensure that an adequate number of pre- SRY Synchronous Ready Input fetched bytes reside in the queue most of the time. v Valid Therefore, actual program execution time is not sub- Ww WR Signal stantially greater than that derived from adding the x No Longer a Valid Logic Level instruction timings shown. z Float The 80C 188 8-bit BIU is noticeably limited in its perfor- Examples: mance relative to the execution unit. A sufficient number tev—Time from Clock Low to Address Valid of prefetched bytes may not reside in the prefetch queue i i much of the time. Therefore, actual program execution towe—Time from Clock High to ALE High time will be substantially greater than that derived from tcacsy—Time from Clock Low to Chip Select Valid adding the instruction timings shown. mm 0257525 OO49bS4 117 a eeeSSSSSSsSSsSSSSSSSSSSSssseeeee 80C186/80C188 Microprocessors 87

80C186 INSTRUCTION SET SUMMARY ro Cycles Registro ogistermeery ae eisemenery rags 2 mmedatroregsiermenoy | 1100011 | mosooovm | dam | camtwnr | 1249 arent immeciate to rogistor [sortwoo | dom | oawitwor | aa anevit ero occu [rore000m | eiiron | cwxion | 8 smo sea it 29 | Segment register to register/memory ant PUSH = Push: semen eps F IPUSHA = Push All* 96 fimo [soos | enor tooorisy 2 elt [orersies | ‘0 segmentrgister (e901) 8 POPA «Pop At st XCHG = Exchango: Pegstrmenory win rege a7 iN = input from: ed po [::so010 [son] ‘© lour = output to: Fixed pot [sssoorrw [oon] 9 arte pont 7 IKLAT = Translate byte 0 AL 1 LEA Load EA regi 6 Los = Lead inertos * ILAHF - Load AH with lags 2 ISAHF ~ Stora AH into lags 3 PUSHF = Push flags 9 a [reornor ] , Note: “Indicates instructions not available in 8086 or 8088 microsystems. mm 0257525 0049656 TST mm

80C186 INSTRUCTION SET SUMMARY (continued) Clock Cycles DATA TRANSFER (continued) SEGMENT = Segment Override: es ‘ bs Leora | : es Dor00t10 2 ARITHMETIC: ADD = Add: regironorywinregstriosiner [0000000 ano Immediate to accumiator coooorew | aa | canter | we aneut AADC » Add with cary: Regimemory with registerto ether | 000100dw ano INC einerement: Regiicimemory ws SUB =Subtract: ‘'SBB = Subtract with borrow: Immediate from accumulator O001110W ee | 4 8/16 bit DEC « Decrement: CMP = Compare: NEG « Change sign registermemory 30 AAA = ASC\\| adjust for add [ corsorss | 8 DAA = Decimal adjust for add 4 AAS = ASCII adjust for subtract 7 DAS = Decimal adjust for subtract [oororttt | 4 toaeewe Register dyte 26-28 Aegster-Wors eo Homey Bie gee Memory-Word 4143 mm 0257525 OO49b5? Web = a 90 80C186/80C188 Microprocessors

PRELIMINARY AMD &! 80C186 INSTRUCTION SET SUMMARY (continued) Clock Cycles | Comment Register-t 25-26 Bepatec nor Bea Memory-Byie 31-34 ey re, Fee (signed)* ¥ 29-32 egeer Mors Ea Memory Word a : Register: Word seat bese as CBW = Convert byte to word 2 CWD = Convert word to double word 4 TIT Instruction

000 ROL

010 RCL

100 SHUSAL

101 SHR:

AND = And: Regimemory and register to either 001000dw ato Immediate to register‘memory 1000005w | modt000m a | ane | | ‘Immediate to accumulator 00100T0W [ = | dalaitw= 1 v4 BAS bit o | Sis wo wn Ss Regimemory and register to either w10 ao wo e XOR = Exclusive or: om | Feomemaryandregsteriostner [oottooaw | noirom | ano “Indicates instructions not available in 8086 or 8088 microsystems. an 80C186/80C188 Microprocessors 1

80C186 INSTRUCTION SET SUMMARY (continued) [ron rome Sie [coe Cycles [STRING MANIPULATION: MOVS = Nove bytetnord “ CMPS = Compare bytetword 2 SCAS - Scan bytemnord [rorosstw | 16 (008 - Ld an ALA a eros -seetmenatonaua [reror07w | INS « Input bytelwd from DX port* [orsort0m | 14 OUTS = Output bytewd to DX por* 14 Repeated by coun in CX (REP/REPE/REPZPEPNEIPEPNZ) |CMPS = Compare string [ritroore [roroo11w | 54 22n . LODS = Load string 64+tin INS = Input sting* a Been OUTS = ouput sting? Been CONTROL TRANSFER CALL = Call: within segment Indirect intersegment (mod 19) 38 IMP = Unconaltlonal jump: shetong [prevors [ serion “ Ores win segment “ Rogistavmem indrectwihinsogment [ 11191141 _| wir | teonenscesor Indirect intersegment [rirtiits | modtotem | (mod « 11) 26 RET = Return from CALL: Within segment 6 Intersegment 22 Intersegment adding immediate to SP [ or] 25 “Indicates instructions not available in 8086 or 8088 microsystems. M@™§ 0257525 0045655 779 a 92 80C186/80C188 Microprocessors

80C186 INSTRUCTION SET SUMMARY (continued) Clock Function Format Cycles ‘CONTROL TRANSFER (continued) utdmponeauszeo — [aTTOTeO | awe] ws ]ULJNGE = Jump on less JLEKING = Jump on less SB/JNAE = Jump on below! ‘JBEVINA = Jump on below or J YPAUPE = Jump on panty’ ‘party even crore | a +d ana UMP rot JO = Jump on overtiow oTtTo000 | dep __| ans takervJMP 38 = Jumponsion oriii000 | ae ana taken JSNEMINZ = Jump on not equal watts ws INUIGE = Jump on not less ‘greater or equal orsiiso1 | dsp | ans INLENG = Jump on not less! a CL wn JJNBIJAE = Jump on not below : INBEWA = Jump on not below sensi” — Carron [a] ws JNP/PO = Jump on not NO = Jump en not vertion ortio001 | ap | ws YOXL= Jumpon CX zor0 [rrooo1s [sap | ad LOOP = Loop Cx Times t1100010 | asp | ene LOOP not taker’ LOOPZ/LOOPE = Loop while zaro/equal [is:00001 | om» | ens Loop vaken LOOPNZILOOPNE = Loop while notzero/eqal [11100000 [és | aie =o 18 tet 25 ust 22+ 16in-1) LEAVE = Leave Procedure 11001001 8 INT = Interrupt: Type spectied EETSEDT a Types 11001100 45 if INT. tekorv INTO = Interrupt on overtiow 49/4 | if NT.nottaken RET = Interrupt run 28 BOUND = Detect value outotrarge* [071 00070 w-35 “Indicates instructions not available in 8086 or 8088 microsystems. M™@ 0257525 cO4dbbO 410 = ——o ss SSS 80C186/80C188 Microprocessors 93

800186 INSTRUCTION SET SUMMARY (continued)

CMC = Complement carry STC = Set carry (CLD = Clear direction [irttit00 | |STD = Setirection CU = Clearinterupt (iitito10| S11 Setiropt HLT = Halt WAIT = Wait ESC = Procassor Extension Escape LOCK = Bus lock pretix NOP = No Operation {TT T LLL are opcode to processor extension) Footnotes REG is assigned according to the following table: ‘The Effective Address (EA) of the memory operand is com- puted according to the mod and r/m fields: 16 Bit (w= 1) 8 Bit (Ww =0) if mod = 11 then r/m is treated as a REG field : Sif mod = 00 then DISP = 0°, disp-low and disp-high are 000 AX 900 AL absent 001 CX oot CL «if mod = 01 then DISP = disp-low sign-extended to 16-bits, 010 DX 010 DL disp-high is absent +f mod= 18 then DISP = disphigh: disptow o1t BX o11 BL +f = 900 then EA = (BX) + (SI) « DIE 100 SP 100 AH if /m = 001 then EA = (BX) + (Dl) + if /m = 010 then EA = es) + gh DISP 101 BP 101 CH sf m= O11 then EA = (BP) + (Dil + DISP 110 SI 110 DH « if rim = 100 then EA = sh ISP 118 cifim= tt = * itm = 110 then ER = (Bx) ¢ DISE The physical addresses of all operands addressed by DISP follows second byte of instruction (before data if the BP register are computed using the SS segment reg- required) - ister. The physical addresses of the destination oper- except mod = 00 and r/m = 110 then EA = disp-high: ands of the string primitive operations (those addressed ' i by the DI register) are computed using the ES segment, EA calculation time is four-clock cycles for all modes, and is : 4 Faded intho execution times given whenever appropriate. Which may not be overridden. ‘Segment Override Prefix [oTo[s Teo Ts] +] 2] Reg is assigned according to the following: Segment Reg Register 00 eS 01 cs 10 ss " os we 0257525 O049bb1 357 oe 94 80C186/80C188 Microprocessors

80C188 INSTRUCTION SET SUMMARY Cycles Register to register/memory ania Regstermamory rite 2 Immediate to registermemory [ trec011w | mosoooum | cam | daaiwat | 12-413 aiievit Immediate 0 rogister [rorwes | sa | caatwai_| a4 aneuit Register/memary to segment register N38 Segment register toregstermenoy, [ TOOTTTOO | ans PUSH = Push: wero ° Regie “ Segmerregister ® USHA Push All* Cy POP = Pop: tm Ee oe “ Register “4 [Segment register (reg +01) 2 POPA = Pop Al™ a XCHG = Exchange: Aegistermeory wih register ar IN = Input from: OUT = Output to: Fred pot [srroormw [pon] ° Variable por [strortaw | r XLAT = Trandate byle to AL | sio10111 | 18 LEA = Load EA to rogistor 6 LDS = Load pointer to OS (mod #11) 28 LES = Load pointer to ES [ 11000100 | modregrim | (meds) 28 LAW = Load AH wth tags 2 |SAHF = Store AH into flags 3 |PUSHF = Push tlags 3 Pom Pena [Lieve | c Notes: *Clock cycles shown for byte transfer. For word operations, add 4 clock cycles for all memory transfers. “indicates instructions not available in 8086 or 8088 microsystems. ‘ M™ 0257525 004%bbe 293 80C186/80C188 Microprocessors 95

80C188 INSTRUCTION SET SUMMARY (continued) Function Format | Sait, [comment JDATA TRANSFER (Continued) |SEGMENT = Segment Override: es : Ss : ps 2 ES 00100110 2 ARITHMETIC: ADD = Add: Regimamary wen regstertostner [O000s0dw anor Immediate to registevmemory 100000sw | mod 000nm | oza | data ifsw= 01 ane ADC = Add with carry: INC increment: Register 07000789 3 SUB Subtract: Reegimemory and register to other sito" |SBB = Subtract with borrow: Reg/memory and register to either snot Immediate from accumulator Toor Tow | ama‘ daatwot | aia anebit DEC = Decrement: Register/memory mod 001 1m ans* © [CMP = Compare: wn Ss NEG = Change sign registormemory ano" [asa asc ait aa 8 | DAA - Decimal adjust tor add [ooroartt | 4 Oy] Aas = ASCI adjust for subtract 7 tex [PAS = Decimal acjust for subtract 4 FU MUL = Multiply (unsigned) Tod OO rim | ig Registor Byte, 26-28 Hogister Wore 38.57 i Monony aye 32-34 Mernory-Word ana Note: : *Clock cycles shown for byte transfer. For word operations, add 4 clock cycles for all memory transfers. 96 80C186/80C188 Microprocessors

PRELIMINARY am &t PRELIMINARY AM GN 80C188 INSTRUCTION SET SUMMARY (continued) Clock Cycles ARITHMETIC (Coninuedy Rogistor-Byto 25-28 Aegater Woe pa jemory Byte Bios Memory Wore Fare (signed) 23-32 Register aye 23 ean 2 mary aye Memory: Wora ao Rogistor- aye 4-82 costo Se fomory Bye. 50 Memory: Wore sor JAAM ~ ASCI adjust for multiply Doo0T010 19 JAAD = ASCII adjust fordivide [rrovoror | oo00t010 18 [CBW = Convert byte to word: 10011000 2 }CWD = Convert word to double word [10011007 4 Loaic |Shift/Rotate instructions: RogterMemay by CL med TT om sevtten mT Instruction

001 ROR

100 SHUSAL_

101 SHR

111 SAR

AND = And: Rogmomory and register other [001 000dw ano TEST = And function to tiags, | Ino result: TS __|immesite data and rogitrinerory mocoomm | daa | eater _| ww Tu tr |mmedisiedeaansaccamsstor [Fores0w | owe | aaatwas _| wu arse ty JORsor: FU |Reoiemary ant reise tier aio uw Fy | xon = Exctusive or: T | Fegmemoryandeisie tositer [oor 00aw snot T_ | Nor = nverregsiermemary: snot i Notes: “Clock cycles shown for byte transfer. For word operations, add 4 clock cycles for all memory transfers. “‘Indicates instructions not available in 8086 or 8088 microsystems. —— Rrra eae oe oOo 80C186/80C188 Microprocessors 97

80C188 INSTRUCTION SET SUMMARY (continued) a Cycles ‘STRING MANIPULATION: Dove sero tyerwerd cups-conpureoyowerd —-rosoortw | a Lops. toad byiamdioaLax [10101 10W | 12 |STOS = Store byternd from ALA 10 INS = Input byte/wd trom DX port** 4 OUTS = Output byte’wd to DX port"* 14 Repeated by count in CX (REP/REPE/REPZPEPNEPEPNZ) MOVS = Mave string Ee 8+6n* JCMS = Compare string 5+22n* LODS = Load string 6+ tin" INS = Input sting” a +80" OUTS = Output string" [rteore [orraitiw | 8480" CONTROL TRANSFER CALL = Call: Direct within segment [sr0ro00 | aispiow [asprin] 19 within segment Indirect ntersegment [PERT | erOT Tam [Oe TT 54 IMP = Unconditional jump: Ragistermem indirect within segment Wes {edirect intersegment oda 34 RET = Return from CALL: ‘ntorsegment [rr001011 | 30 Intersegment adding immediate to SP [awaiow | datanioh —] 33 Notes: “Clock cycles shown for byte transfer. For word operations, add 4 clock cycles for all memory transfers. “Indicates instructions not available in 8086 or 8088 microsystems. mM 0257525 OO4%bbS TTe 98 80C186/80C188 Microprocessors

80C188 INSTRUCTION SET SUMMARY (continued) Clock ncion fmt id Gycles_| Comment ‘CONTROL TRANSFER (Continued): YE/Z = Jump on equal zero o11t0700 [isp] As SUINGE = Jump on less/ ILEAING = Jumpon less/ crewainctgreaer = [ortisis0 | a] ana UB/JNAE = Jump on below! |JBE/JNA = Jump on below or acs ws PIPE = Jump on parity! JO = Jump on overflow [orttooce | dsp | ans taken/JMP 48 = Jump on sign orri1000 | asp _| ana taken INEWNZ = Jump on not equal’ INLIGGE = Jump on not less poate os citer | a | ws UNLENIG = Jump on not less INBIJAE = Jump on not below above ar equal ittoomr | ow —'d ans JNBE/JA = Jump on not below: INP/JPO = Jump on not E10 = dump on net overtow [ortsocor [ep ana INS = Jump on not sign Porstroon [isp | ans }YOXZ = Jump on CX zer0 [risooors [isn | sis LOOP = Loop OX Times [isp | ens LOOP not LOOPZILOOPE = Loop while wae = [sssoo001 Tae] ere | tatentoor LOOPNZ/LOOPNE = Loop while not zero/equal [11100000 [ a» | ene taken ENTER - Enver Pocedie™ 17007000 | camiow | daahgh > a 1 try 23 th 26 + 20(0~ 1) LEAVE = Loave Procedturo" 8 INT = Interrupt: "ye epost [eeorer [me ” Types 11001100 45 it INT. takery| INTO = interrupt on overtiow 11001410 4a |itiNT.nottake IRET = rtorupt return 28 BOUND ~ Detoct value out of range" [01100010 99-95 Notes: “Clock cycles shown for byte transfer, For word operations, add 4 clock cycles for all memory transfers. “‘indicates instructions not available in 8086 or 8088 microsystems. WM 0257525 OO4%bbb 935 a SSSSSSSSSsSSSss 80C186/80C188 Microprocessors 99

80C188 INSTRUCTION SET SUMMARY (continued) PROCESSOR CONTROL CLC = Clear cary {eMC = Complement cary STC =Setcarry ‘CLD = Clear direction STD =Setdirection CLI = Clear interrupt HLT = Hat WAIT = Wait it vest =0 LOCK ~ Bus lock pratix NOP «= No Operation Footnotes REG is assigned according to the following table: The Effective Address (EA) of the memory operand is com- puted according to the mod and r/m fields: 16 Bit(w=1) 8 Bit(w=0) «if mod = 11 then r/mis treated as a REG field * if mod=00 then DISP =0*, disp-low and disp-high are 000 AX 000 AL absent 001 CX 001 CL «if mod = 01 then DISP = disp-low sign-extended to 16-bits, 010 DX o10 DL disp-high is absent si mod = 10 then DISP = disp-igh: disp-low 011 BX ott BL «if r/m = 000 then EA = (BX) + (Sl) + DISP 100 SP 100 AH if /m = 001 then EA = (BX) + (oH + DISP ifm = 010 then EA ~ (BP) + (Si) DISP 101 BP 101 CH «if /m = 011 then EA = (BP) + (Dl) + DISP 110 SI 110 DH * if tim = 100 then EA = (Sl) + DISP DI 411 BH eiff/m=110then = * if rim = 111 then EA = ‘a0 t DISP The physical addresses of all operands addressed by DISP follows second byte of instruction (before data if the BP register are computed using the SS segment reg- required) ister. The physical addresses of the destination oper- ‘except if mod = 00 and r/m = 110 then EA = disp-high: ands of the string primitive operations (those addressed disp-low. by the DI register) are computed using the ES segment, EA calculation time is four-clock cycles for all modes, and is 4 " included in the execution times given whenever appropriate. which may not be overridden. Segment Override Prefix Reg is assigned according to the following: ‘Segment Reg Register 00 ES 01 cs 10 ss 1 Ds @™ 0257525 OO45bL? 675 me 100 80C186/80C188 Microprocessors

For reterence only. Dimensions are measured in inches unless otherwise noted. BSC is an ANSI standard for Basic Space Centering. PL oes 020 042 ose MIN 048 - 042 02: oe 056 SBR a , > q p LP g q t>P 1 q i ELL or J =] F021 q q [ >P q fh 026 ie 032 J 985 950 Y p LE —s«800 .890 ‘998 ose Y i >P REF 930 q P Er p =

4 P Er

} H ah | ' Er ch CSS SSS N= ale, $59 013 .090 985 165 [Shoe ioe 995 180 BASE ode TOP VIEW SIDE VIEW @@ 0257525 OO4dbLS 701 SSS 80C186/80C188 Microprocessors 101

PHYSICAL DIMENSIONS (continued) PQR 80 (measured in millimeters) 17.10 13,9 17.30 Pin 40. 12.0 14.10 REF HARA RAR AR AB AAA | | Pin 24 AUNUUTNROUUARUGHOUOAOROUORETIOE H = ' Erno i¢.40 oo ‘ Fes ner | . 45 wee eee eee ee —— 19.90 =| ‘ == 20.10 oC ' == 23.00 so | : fo 23.40 =a : ==, Pin)? Dey + Pint 1.0—> © Pin 64 CMM HUHBEEHUUEUYEEER Top View Pin 80 + i 0.80 Basic | nn Or m- 3.35 APUPUPAPDAPUPAEUGAGAG APNG APE GL Te FAI AN 270 2.90 15590C

0.25 BM43

“ Side View 7/2393 MH Notes: 1. All dimensions and tolerances conform to ANSI Y 14.5M-1982. ZX _ Datum Plane [EA=]is located at the mold parting line and is coincident with the bottom of the lead where the lead exits the plastic body. LBS. These dimensions do not include mold protrusion. Allowable protrusion is 0.25 mm per side. These dimensions do include mold mismatch and are determined at datum plane 4. Deviations from lead-tip true position shall be within +0.076 mm. 5. Lead coplanarity shall be within 0.10 mm. mm o257525 OO49bL9 bus a 102 80C186/80C188 Microprocessors

PRELIMINARY amp &A PHYSICAL DIMENSIONS (continued) PQT 80 Thin Quad Flat Pack (metric unit) 13.80 1190 14.20 950 12.10 | REF ; PAAR ARARARH ADA RHARART | ocfo i a cxf i i i i Lo ox i bos a | = oo | bi, 9.50 | j [REF = en -— i 11.90 “= 1 _ 12,10 oo i bo 13.80 = i = 14.20 ox i Es or i fr oe j Lis = = THOAAOHWHOPUOeoeeoooo OOoOcgcgogtcadooO | OdUgaedcdddgaa Top View Detail X. “7 Detail Y Sw H Cc Nia JE MAX \\ 7 0.50 1.00. -- Basic REF Side View 0.17 0.27 0.16 el Gage 4 iH Plane y A | we 0.25 4 4 0.18 Dotall X y A 9.1265 045 4 1] 0.1275 0.75 . en” 20000A Ck 64 Detail Y M™ 0257525 OO49b70 3bT am 08/03/93 MH 80C186/80C188 Microprocessors 103