N256S08XXHDA AMI | Alldatasheet

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Technical content

Features

  • Power Supply Options 1.8V to 3.6V
  • Very low standby current As low as 200nA
  • Very low operating current As low as 500uA
  • Simple memory control Single chip select (CS) Serial input (SI) and serial output (SO)
  • Flexible operating modes Word read and write Page mode (32 word page) Burst mode (full array)
  • Organization 32K x 8 bit
  • Self timed write cycles
  • Built-in write protection (CS high)
  • H O L D pin for pausing communication
  • High reliability Unlimited write cycles
  • RoHS Compliant Packages Green SOIC and TSSOP Device Options Part Number Density Power Supply (V) Speed (MHz) Feature Typical Standby Current Read/Write Operating Current N256S0818HDA 256Kb 1.8 20 HOLD 200nA 500 uA @ 1MhzN256S0830HDA 3.0 25 1uA

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information Functional Block Diagram Pin Names Pin Name Pin Function CS Chip Select Input SCK Serial Clock Input SI Serial Data Input SO Serial Data Output HOLD Hold Input NC No Connect VCC Power VSS Ground 1CS SOIC SO NC VSS VCC HOLD SCK SI 1CS TSSOP SO NC VSS VCC HOLD SCK SI Package Configurations SRAM Array Decode Logic CS Clock Circuitry SCK Data In Receiver SI Data Out BufferSO HOLD

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information Absolute Maximum Ratings1 Item Symbol Rating Unit Voltage on any pin relative to VSS VIN,OUT –0.3 to VCC+0.3 V Voltage on VCC Supply Relative to VSS VCC –0.3 to 4.5 V Power Dissipation PD 500 mW Storage Temperature TSTG –40 to 125 oC Operating Temperature TA -40 to +85 oC Soldering Temperature and Time TSOLDER 260oC, 10sec oC 1. Stresses greater than those listed above may cause permanent da mage to the device. This is a stress rating only and functiona l operation of the device at these or any ot her conditions above those indicated in the operating se ction of this specification i s not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Item Symbol Test Conditions Min. Typ1 1. Typical values are measured at Vcc=Vcc Typ., T A=25°C and are not 100% tested. Max Unit Supply Voltage VCC 1.8V Device 1.7 1.95 V Supply Voltage VCC 3V Device 2.3 3.6 V Input High Voltage VIH 0.7 x VCC VCC+0.3 V Input Low Voltage VIL –0.3 0.3 x VCC V Output High Voltage VOH IOH = -0.4mA V CC–0.5 V Output Low Voltage VOL IOL = 1mA 0.2 V Input Leakage Current ILI CS = VCC, VIN = 0 to VCC 0.5 µA Output Leakage Current ILO CS = VCC, VOUT = 0 to VCC 0.5 µA Read/Write Operating Current ICC1 F = 1MHz, IOUT = 0 500 µA ICC2 F = 10MHz, IOUT = 0 4m A ICC3 F = 20/25MHz, IOUT = 0 8/10 mA Standby Current ISB 1.8V Device CS = VCC, VIN = VSS or VCC 200 500 nA 3V Device CS = VCC, VIN = VSS or VCC 13 µA Capacitance1 1. These parameters are verified in device characterization and are not 100% tested Item Symbol Test Condition Min Max Unit Input Capacitance CIN VIN = 0V, f = 1 MHz, TA = 25oC 7p F I/O Capacitance CI/O VIN = 0V, f = 1 MHz, TA = 25oC 7p F

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information Timing Test Conditions Item Input Pulse Level 0.1VCC to 0.9 VCC Input Rise and Fall Time 5ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 100pF Operating Temperature -40 to +85 oC Timing Item Symbol 1.8V Device 3V Device Units Min. Max. Min. Max. Clock Frequency fCLK 20 25 MHz Clock Rise Time tR 2 2 us Clock Fall Time tF 2 2 u s Clock High Time tHI 25 20 ns Clock Low Time tLO 25 20 ns Clock Delay Time tCLD 25 20 ns CS Setup Time tCSS 25 20 ns CS Hold Time tCSH 50 40 ns CS Disable Time tCSD 25 20 ns SCK to CS tSCS 55 n s Data Setup Time tSU 10 10 ns Data Hold Time tHD 10 10 ns Output Valid From Clock Low tV 25 20 ns Output Hold Time tHO 00 n s Output Disable Time tDIS 20 15 ns HOLD Setup Time tHS 10 10 ns HOLD Hold Time tHH 10 10 ns HOLD Low to Output High-Z tHZ 10 10 ns HOLD High to Output Valid tHV 50 40 ns

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information Serial Input Timing Serial Output Timing Hold Timing CS tCSS MSB in SCK SO SI LSB in tFtR tCLD tCSH tCSD tSU tHD High-Z tSCS CS tLO MSB out SCK SI SO LSB out tDIS tCSH tHI tV Don’t Care CS tHS n+2 SCK SI SO tSUtHZ tHH n+1 n High-Z tHS tHH tHV nn - 1 nn - 1 n+2 n+1 n HOLD Don’t Care

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information Functional Operation Basic Operation The 256Kb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI) common on many standard micro-controllers. It may also interface with other non-SPI ports by programming discrete I/O lines to operate the device. The serial SRAM contains an 8-bit instruction register and is accessed via the SI pin. The CS pin must be low and the HOLD pin must be high for the entire operation. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared, the user can assert the HOLD input and place the device into a Hold mode. After releasing the HOLD pin, the operation will resume from the point where it was held. The following table contains the possible instructions and formats. All instructions, addresses and data are transferred MSB first and LSB last. Control Signal Descriptions Signal Name I/O Description CS Chip Select I A low level selects the device and a high level puts the device in standby mode. If CS is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence being started. SCK Serial Clock I Synchronizes all activities between the memory and controller. All incoming addresses, data and instructions are latched on the rising edge of SCK. Data out is updated on SO after the falling edge of SCK. SI Serial Data In I Receives instructions, addresses and data on the rising edge of SCK. SO Serial Data Out O Data is transferred out after the falling edge of SCK. HOLD Hold I A high level is required for normal operation. Once the device is selected and a serial sequence is started, this input may be taken low to pause serial communica- tion without resetting the serial sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low, the Hold function will not be invoked until the next SCK high to low transition. The device must remain selected during this sequence. SO is high-Z during the Hold time and SI and SCK are inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low. Lowering the HOLD input at any time will take to SO output to High-Z. Instruction Set Instruction Instruction Format Description READ 0000 0011 Read data from memory starting at selected address WRITE 0000 0010 Write data to memory starting at selected address RDSR 0000 0101 Read status register WRSR 0000 0001 Write status register

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information READ Operations The serial SRAM READ is selected by enabling CS low. First, the 8-bit READ instruction is transmitted to the device followed by the 16-bit address with the MSB being a don’t care. After the READ instruction and addresses are sent, the data stored at that address in memory is shifted out on the SO pin after the output valid time from the clock edge. If operating in page mode, after the initial word of data is shifted out, the data stored at the next memory location on the page can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is read out. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. If operating in burst mode, after the initial word of data is shifted out, the data stored at the next memory location can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (7FFFh), the address counter wraps to the address 0000h. This allows the burst read cycle to be continued indefinitely. All READ operations are terminated by pulling CS high. Word READ Sequence CS Instruction SI 04 32516 9 81 07 11SCK 15 14 13 12 210 7 6543 210High-Z 16-bit address Data Out SO 21 2322 24 28 29 30 31 26 2725 000 0 0 011

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information Page and Burst READ Sequence Page READ Sequence Burst READ Sequence CS Instruction SI 04 32516 9 81 07 11SCK 15 14 13 12 210 7 6543 210High-Z 16-bit address Data Out from ADDR 1 SO 21 2322 24 28 29 30 31 26 2725 000 0 0 011 7 6543 210 Data Out from ADDR 2 7 6543 210 7 6543 210... 32 3433 35 39 40 41 42 37 3836 43 45 44 46 47 Don’t Care Don’t Care ADDR 1 Data Out from ADDR 3 Data Out from ADDR n Page X Word Y Page X Word Y+2 Page X Word Y+1 Page X Word 31 Page X Word 0 Page X Word 1 SI SO Data Words: sequential, at the end of the page the address wraps back to the beginning of the page 16-bit address Page address (X) Word address (Y) Page X Word Y Page X Word 31 Page X Word Y+1 Page X Word 0 Page X+1 Word Y Page X+1 Word Y+1 SI SO 16-bit address Page address (X) Word address (Y) Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. . . . Page X Word 1 . . . Page X Word Y-1

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information WRITE Operations The serial SRAM WRITE is selected by enabling CS low. First, the 8-bit WRITE instruction is transmitted to the device followed by the 16-bit address with the MSB being a don’t care. After the WRITE instruction and addresses are sent, the data to be stored in memory is shifted in on the SI pin. If operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is sequential on the same page. Simply write the data on SI pin and continue to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. The new data will replace data already stored in the memory locations. If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (7FFFh), the address counter wraps to the address 0000h. This allows the burst write cycle to be continued indefinitely. Again, the new data will replace data already stored in the memory locations. All WRITE operations are terminated by pulling CS high. Word WRITE Sequence CS Instruction SI 04 32516 9 81 07 11SCK 15 14 13 12 2107 6543 210 High-Z 16-bit address Data In SO 21 2322 24 28 29 30 31 26 2725 000 0 0 010 ...

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information Page and Burst WRITE Sequence Page WRITE Sequence Burst WRITE Sequence CS Instruction SI 04 32516 9 81 07 11SCK 15 14 13 12 2107 6543 210 High-Z 16-bit address Data In to ADDR 1 SO 21 2322 24 28 29 30 31 26 2725 000 0 0 010 7 6543 210 Data In to ADDR 2 7 6543 210 7 6543 210... 32 3433 35 39 40 41 42 37 3836 43 45 44 46 47 ADDR 1 Data In to ADDR 3 Data In to ADDR n High-Z 16-bit address Page address (X) Word address (Y) Page X Word Y Page X Word Y+2 Page X Word Y+1 Page X Word 31 Page X Word 0 Page X Word 1 SI SO Data Words: sequential, at the end of the page the address wraps back to the beginning of the page High-Z Page X Word Y Page X Word 31 Page X Word Y+1 Page X Word 0 Page X+1 Word Y Page X+1 Word Y+1 SI SO 16-bit address Page address (X) Word address (Y) Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. . . . Page X Word 1 . . . Page X Word Y-1 High-Z

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information WRITE Status Register Instruction (WRSR) This instruction provides the ability to write the status register and select among several operating modes. Several of the register bits must be set to a low ‘0’ if any of the other bits are written. The timing sequence to write to the status register is shown below, followed by the organization of the status register. WRITE Status Register Sequence Status Register CS Instruction SI 04 32516 9 81 071 1 SCK 7 6543 210 High-Z Status Register Data In SO 00 0 00 1 0 12 13 14 15 Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7 Hold Function 0 = Hold (Default) 1 = No Hold Reserved Must = 0 Reserved Must = 0 Mode 0 0 = Word Mode (Default) 1 0 = Page Mode 0 1 = Burst Mode 1 1 = Reserved

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information READ Status Register Instruction (RDSR) This instruction provides the ability to read the Status register. The register may be read at any time by performing the following timing sequence. READ Status Register Instruction (RDSR) Power-Up State The serial SRAM enters a know state at power-up time. The device is in low-power standby state with CS = 1. A low level on CS is required to enter a active state. CS Instruction SI 04 32516 9 81 071 1 SCK 7 6543 210High-Z Status Register Data Out SO 00 0 00 1 0 12 13 14 15

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information 8-Lead Plastic Small Outline, 150mil SOIC Note: 1. All dimensions in Millimeters 2. Package dimensions exclude mold flash and protusions. Parameter Sym Min Nom Max Pin Pitch p 1.27 Overall height A 1.35 1.55 1.75 Molded Package Thickness A2 1.32 1.42 1.55 Standoff A1 0.10 0.18 0.25 Overall Width E 5.79 6.02 6.20 Molded Package Width E1 3.71 3.91 3.99 Overall Length D 4.80 4.90 5.00 Chamfer Distance h 0.25 0.38 0.51 Foot Length L 0.48 0.62 0.76 Foot Angle φ 04 8 Lead Thickness c 0.20 0.23 0.25 Lead Width B 0.33 0.42 0.51 Mold Draft Angle Top α 01 2 1 5 Mold Draft Angle Bottom β 01 2 1 5 D p B A2 A1 A 45o c βL h φ α E

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information 8-Lead Plastic Thin Shrink Small Outline, 4.4 mm TSSOP Note: 1. All dimensions in Millimeters 2. Package dimensions exclude mold flash and protusions. Parameter Sym Min Nom Max Pin Pitch p 0.65 Overall height A 1.10 Molded Package Thickness A2 0.85 0.90 0.95 Standoff A1 0.05 0.10 0.15 Overall Width E 6.25 6.38 6.50 Molded Package Width E1 4.30 4.40 4.50 Overall Length D 2.90 3.00 3.10 Foot Length L 0.50 0.60 0.70 Foot Angle φ 04 8 Lead Thickness c 0.09 0.15 0.20 Lead Width B 0.19 0.25 0.30 Mold Draft Angle Top α 05 1 0 Mold Draft Angle Bottom β 05 1 0 D p B A2 A1 A c βL φ α E

This is a developmental specification and is subject to change without notice. N256S0818HDA/N256S0830HDAAMI Semiconductor, Inc. Advance Information

Ordering Information

© 2006 AMI Semiconductor, Inc. All rights reserved. AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be expected to result in significant injury or death, including life support systems and critical medical instruments.

Revision History

Revision # Date Change Description A October 2005 Initial advance release B January 2006 Separated density, removed write protection and added page and burst modes C January 2006 Changed packages to green type D January 2006 Changed TSSOP pinout to match SOIC E September 2006 Split x8 and x16 devices Converted to AMI Semiconductor N256S08 XX XX A X- XX I 25 = 25MHz 20 = 20MHz S2 = Green SOIC (RoHS Compliant) T2 = Green TSSOP (RoHS Compliant) HD = Hold Function Input Performance Package Function Voltage 18 = 1.8V 30 = 3V