N156BGE-EA1

N156BGE-EA1 CHIMEI | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 OVERVIEW
• 1.2 GENERAL SPECIFICATI0NS
• 2.1 CONNECTOR TYPE
• 3.1 ABSOLUTE RATINGS OF ENVIRONMENT
• 3.2 ELECTRICAL ABSOLUTE RATINGS
• 3.2.1 TFT LCD MODULE
• 4.1 FUNCTION BLOCK DIAGRAM
• 4.2 INTERFACE CONNECTIONS
• 4.3 ELECTRICAL CHARACTERISTICS
• 4.3.1 LCD ELETRONICS SPECIFICATION
• 4.3.2 LED CONVERTER SPECIFICATION
• 4.3.3 BACKLIGHT UNIT
• 4.4 DISPLAY PORT SIGNAL TIMING SPECIFICATION
• 4.4.1 DISPLAY PORT INTERFACE
• 4.4.2 COLOR DATA INPUT ASSIGNMENT
• 4.5 DISPLAY TIMING SPECIFICATIONS
• 4.6 POWER ON/OFF SEQUENCE
• 5.1 TEST CONDITIONS
• 5.2 OPTICAL SPECIFICATIONS
• 7.1 MODULE LABEL
• 7.2 CARTON
• 7.3 PALLET
• 7.4 UN-PACKAGING METHOD
• 8.1 HANDLING PRECAUTIONS
• 8.2 STORAGE PRECAUTIONS
• 8.3 OPERATION PRECAUTIONS

Version 2.2 7. Nov, 2013 1 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Customer: APPROVED BY SIGNATURE Name / Title Note Please return 1 copy for your confirmation with your signature and comments. Doc. Number: □ Tentative Specification □ Preliminary Specification ▓ Approval Specification MODEL NO.: N156BGE SUFFIX: EA1 Approved By Checked By Prepared By 曾淑郁 2013-11-13 17:56:11 CST 曹文彬 2013-11-11 15:46:24 CST 張君浩 2013-11-08 13:49:33 CST

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REVISION HISTORY

2.0 Jun.13, 2013 All Spec Ver.2.0 was first issued 2.1 Oct.22,2013 4 Modify” 1.2 GENERAL SPECIFICATI0NS” Power Consumption: Add 2. MECHANICAL SPECIFICATIONS Note (2)Dimensions are measured by caliper 12 Modify”4.3.2 LED CONVERTER SPECIFICATION” LED Power Current 14 Modify “4.3.3 BACKLIGHT UNIT” 17 Modify “4.5 DISPLAY TIMING SPECIFICATIONS” 21 Modify “5.1 TEST CONDITIONS” LED Light Bar Input Current change to 51mA Modify “5.2 OPTICAL SPECIFICATIONS” Color Chromaticity White Variation of 5 & 13 Points 31 Modify “Appendix. EDID DATA STRUCTURE” 2.2 Nov.07,2013 5 Modify”1.2 GENERAL SPECIFICATI0NS” Luminance, White:220nit Power Consumption: 11 Modify”4.3.2 LED CONVERTER SPECIFICATION” LED Power Current 13 Modify”4.3.3 BACKLIGHT UNIT” 20 Modify”5.2 OPTICAL SPECIFICATIONS” 35 Modify” Appendix. SYSTEM COVER DESIGN GUIDANCE ” 41 Add” Appendix. LCD MODULE HANDLING MANUAL”

Version 2.2 7. Nov, 2013 5 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. 1. GENERAL DESCRIPTION

1.1 OVERVIEW

N156BGE-EA1 is a 15.6” (1 5.547 ” diagonal) TFT Liquid Crystal Display module with LED Backlight unit and 30 pins eDP interface. This module supports 1366 x 768 HD mode and can display 262,144 colors. The optimum viewing angle is at 6 o’clock direction.

1.2 GENERAL SPECIFICATI0NS

Item Specification Unit Note Screen Size 15.547” diagonal Driver Element a-si TFT active matrix - - Pixel Number 1366 x R.G.B. x 768 pixel - Pixel Pitch 0.252 (H) x 0.252 (V) mm - Pixel Arrangement RGB vertical stripe - - Display Colors 262,144 color - Transmissive Mode Normally white - - Surface Treatment Hard coating (3H), Anti-Glare - - Luminance, White 220 Cd/m2 Note (1) The specified power consumption (with converter efficiency) is under the conditions at VCCS =

3.3 V, fv = 60 Hz, LED_VCCS = Typ, fPWM = 200 Hz, Duty=100% and Ta = 25 ± 2 ºC, whereas mosaic

pattern is displayed. 2. MECHANICAL SPECIFICATIONS Item Min. Typ. Max. Unit Note Horizontal (H) 359 359.5 360 mm Vertical (V) 206 206.5 207 mm Thickness (T) - 3.05 3.20 mm Module Size Thickness (T) (PCBA with Mylar) - - 3.25 mm (1) Weight - 345 360 g Note (1) Please refer to the attached drawings for more information of front and back outline dimensions. Note (2) Dimensions are measured by caliper.

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2.1 CONNECTOR TYPE

Please refer Appendix Outline Drawing for detail design. Connector Part No.: IPEX-20455-030E-12 User’s connector Part No: IPEX-20453-030T-01 3. ABSOLUTE MAXIMUM RATINGS

3.1 ABSOLUTE RATINGS OF ENVIRONMENT

Min. Max. Unit Note Storage Temperature T ST -20 +60 ºC (1) Operating Ambient Temperature T OP 0 +50 ºC (1), (2) Note (1) (a) 90 %RH Max. (Ta < 40 ºC). (b) Wet-bulb temperature should be 39 ºC Max. (Ta < 40 ºC). (c) No condensation. Note (2) The temperature of panel surface should be 0 ºC min. and 60 ºC max. Pin1 Pin30 Temperature (ºC) Relative Humidity (%RH) Operating Range 100 80 60 -20 40 0 20 -40

5 Storage Range

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3.2 ELECTRICAL ABSOLUTE RATINGS

3.2.1 TFT LCD MODULE

Min. Max. Unit Note Power Supply Voltage VCCS -0.3 +4.0 V Logic Input Voltage V IN -0.3 VCCS+0.3 V (1) Converter Input Voltage LED_VCCS -0.3 26 V (1) Converter Control Signal Voltage LED_PWM, -0.3 5 V (1) Converter Control Signal Voltage LED_EN -0.3 5 V (1) Note (1) Stresses beyond those listed in above “ELECTRICAL ABSOLUTE RATINGS” may cause permanent damage to the device. Normal operation should be restricted to the conditions described in “ELECTRICAL CHARACTERISTICS”. 4. ELECTRICAL SPECIFICATIONS

4.1 FUNCTION BLOCK DIAGRAM

4.2 INTERFACE CONNECTIONS

Pin Symbol Description Remark

1 NC No Connection (Reserved for LCD test)

2 H_GND High Speed Ground

3 NC No Connection (Reserved for LCD test)

4 NC No Connection (Reserved for LCD test)

5 H_GND High Speed Ground

6 ML0- Complement Signal-Lane 0

7 ML0+ True Signal-Main Lane 0

8 H_GND High Speed Ground

9 AUX+ True Signal-Auxiliary Channel

DC/DC CONVERTER & REFERENCE VOLTAGE GENERATOR INPUT CONNECTOR LED CONVERTER

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10 AUX- Complement Signal-Auxiliary Channel

11 H_GND High Speed Ground

12 VCCS Power Supply +3.3 V (typical) 13 VCCS Power Supply +3.3 V (typical)

14 NC No Connection (Reserved for LCD test)

15 GND Ground

16 GND Ground

17 HPD Hot Plug Detect

18 BL_GND BL Ground

19 BL_GND BL Ground

20 BL_GND BL Ground

21 BL_GND BL Ground

22 LED_EN BL_Enable Signal of LED Converter

23 LED_PWM PWM Dimming Control Signal of LED

24 NC No Connection (Reserved for LCD test)

25 NC No Connection (Reserved for LCD test)

26 LED_VCCS BL Power

27 LED_VCCS BL Power

28 LED_VCCS BL Power

29 LED_VCCS BL Power

30 NC No Connection (Reserved for LCD test)

Note (1) The first pixel is odd as shown in the following figure. 1,1 (odd) 1,2 (even) 1,3 (odd) 1,4 (even) 2,1 2,2 3,1 Ymax,1 Ymax, Xmax 1,Xmax Pitch Pitch

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4.3 ELECTRICAL CHARACTERISTICS

4.3.1 LCD ELETRONICS SPECIFICATION

Min. Typ. Max. Unit Note Power Supply Voltage VCCS 3.0 3.3 3.6 V (1)- High Level 2.25 - 2.75 V HPD Low Level 0 - 0.4 V Ripple Voltage V RP - 50 - mV (1)- Inrush Current I RUSH - - 1.5 A (1),(2) Mosaic 250 300 mA (3)a Power Supply Current Black lcc 300 340 mA (3) Note (1) The ambient temperature is Ta = 25 ± 2 ºC. Note (2) IRUSH : the maximum current when VCCS is rising IIS : the maximum current of the first 100ms after power-on Measurement Conditions: Shown as the following figure. Test pattern: black. (High to Low) (Control Signal) +12V SW 1uF VCCS +3.3V 2SK1470 Q1 2SK1475 47K VR1 47K C2 0.01uF 1uF FUSE (LCD Module Input)

Version 2.2 7. Nov, 2013 10 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Note (3) The specified power supply current is under the conditions at VCCS = 3.3 V, Ta = 25 ± 2 ºC, DC Current and f v = 60 Hz, whereas a power dissipation check pattern below is displayed. VCCS rising time is 0.5ms Active Area a. Mosaic Pattern

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4.3.2 LED CONVERTER SPECIFICATION

Min. Typ. Max. Unit Note Converter Input power supply voltage LED_Vccs 5.0 12.0 21.0 V Converter Inrush Current ILED RUSH - - 1.5 A (1) Backlight On 2.2 - 5 V EN Control Level Backlight Off 0 - 0.6 V PWM High Level 2.2 - 5 V PWM Control Level PWM Low Level 0 - 0.6 V PWM Control Duty Ratio 5 - 100 % PWM Control Permissive Ripple Voltage VPWM_pp - - 100 mV PWM Control Frequency f PWM 190 - 2K Hz (2) LED Power Current LED_VCCS =Typ. ILED 154 191 200 mA (3) Note (1) ILED RUSH : the maximum current when LED_VCCS is rising, ILED IS : the maximum current of the first 100ms after power-on, Measurement Conditions: Shown as the following figure. LED_VCCS = Typ, Ta = 25 ± 2 ºC, fPWM = 200 Hz, Duty=100%. (High to Low) (Control Signal) LED_VCCS(Typ) SW=24V 1uF LED_VCCS(Typ) IRL3303 Q1 IRL3303 47K VR1 47K C2 0.01uF 1uF FUSE (LED Converter Input)

Version 2.2 7. Nov, 2013 12 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. 90% 10% 0.5ms ILED Rush ILED IS ILED LED_VCC 100ms LED_PWM LED_EN Note (2) If PWM control frequency is applied in the range less than 1KHz, the “waterfall” phenomenon on the screen may be found. To avoid the issue, it’s a suggestion that PWM control frequency should follow the criterion as below. PWM control frequency f PWM should be in the range N : Integer ) 3( ≥N f : Frame rate Note (3) The specified LED power supply current is under the conditions at “LED_VCCS = Typ.”, Ta = 25 ± 2 ºC, f PWM = 200 Hz, Duty=100%. VLED rising time is 0.5ms

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4.3.3 BACKLIGHT UNIT

Ta = 25 ± 2 ºC Value Parameter Symbol Min. Typ. Max. Unit Note LED Light Bar Power Supply Voltage VL 28.6 31.9 33.0 V LED Light Bar Power Supply Current IL 60 mA (1)(2)(Duty100%) Power Consumption P L 1.716 1.914 1.98 W (3) LED Life Time L BL 15000 - - Hrs (4) Note (1) LED current is measured by utilizing a high frequency current meter as shown below : Note (2) For better LED light bar driving quality, it is recommended to utilize the adaptive boost converter with current balancing function to drive LED light-bar. Note (3) P L = I L ×V L (Without LED converter transfer efficiency) Note (4) The lifetime of LED is defined as the time when it continues to operate under the conditions at Ta = 25 ±2 oC and I L = 20 mA(Per EA) until the brightness becomes 50% of its original value.≦ LED Light Bar VL, IL Light Bar Feedback Channels

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4.4 DISPLAY PORT SIGNAL TIMING SPECIFICATION

4.4.1 DISPLAY PORT INTERFACE

Parameter Symbol Min. Typ. Max. Unit Notes Differential Signal Common Mode Voltage(MainLink and AUX) VCM 0 2 V (1)(3) AUX AC Coupling Capacitor C AUX 75 200 nF (2) Note (1)Display port interface related AC coupled signals should follow VESA DisplayPort Standard Version1. Revision 1a and VESA Embedded DisplayPortTM Standard Version 1.2. There are many optional items described in eDP1.2. If some optional item is requested, please contact us. (2) The AUX AC Coupling Capacitor placed on Source Devices. (3) Display Port Compliance Test Specification (CTS) 1.1 VCM |V ID | Single Ended VD- VD+

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4.4.2 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 6-bit gray scale data input for the color. The higher the binary input the brighter the color. The table below provides the assignment of color versus data input. Data Signal Red Green Blue Color R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Basic Colors Black Red Green Blue Cyan Magenta Yellow White Gray Scale Of Red Red(0)/Dark Red(1) Red(2) Red(61) Red(62) Red(63) Gray Scale Of Green Green(0)/Dark Green(1) Green(2) Green(61) Green(62) Green(63) Gray Scale Of Blue Blue(0)/Dark Blue(1) Blue(2) Blue(61) Blue(62) Blue(63) Note (1) 0: Low Level Voltage, 1: High Level Voltage

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4.5 DISPLAY TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram . Refresh rate 60Hz Signal Item Symbol Min. Typ. Max. Unit Note DCLK Frequency 1/Tc 68.78 76.42 80.24 MHz - Vertical Total Time TV 790 800 830 TH - Vertical Active Display Period TVD 768 768 768 TH - Vertical Active Blanking Period TVB TV-TVD 32 TV-TVD TH - Horizontal Total Time TH 1566 1592 1716 Tc - Horizontal Active Display Period THD 1366 1366 1366 Tc - DE Horizontal Active Blanking Period THB TH-THB 226 TH-THB Tc - Note (1) Because this module is operated by DE only mode, Hsync and Vsync are ignored. Note (2) The module can be operated at 50Hz and 40Hz refresh rate. However, there might be some side effect like flicker, brightness change. INPUT SIGNAL TIMING DIAGRAM TH TC DCLK THD TVD Tv DE DE DATA

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4.6 POWER ON/OFF SEQUENCE

The power sequence specifications are shown as the following table and diagram . t12 Restart Power On Power Off 10% t10 t2 90% 10% 90% Black Video t11 10% Black Video Video from Source AUX Channel Operational Link Training Idle Valid Video Data tA tC tE tB Idle or off t5 t6 t8 t9 -Power Supply for LCD, VCCS 0V 90% 10% tF tD -eDP Display -HPD from Sink -AUX Channel -Main Link Data - Power Supply for LED Converter, LED_VCCS - LED Converter Dimming Signal, LED_PWM - LED Converter Enable Signal, LED_EN 90% 10%

Version 2.2 7. Nov, 2013 18 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Timing Specifications: Value Parameter Description Reqd. By Min Max Unit Notes t1 Power rail rise time, 10% to 90% Source 0.5 10 ms - t2 Delay from LCD,VCCS to black video generation Sink 0 200 ms Automatic Black Video generation prevents display noise until valid video data is received from the Source (see Notes:2 and 3 below) t3 Delay from LCD,VCCS to HPD high Sink 0 200 ms Sink AUX Channel must be operational upon HPD high (see Note:4 below ) t4 Delay from HPD high to link training initialization Source - - ms Allows for Source to read Link capability and initialize t5 Link training duration Source - - ms Dependant on Source link training protocol t6 Link idle Source - - ms Min Accounts for required BS-Idle pattern. Max allows for Source frame synchronization t7 Delay from valid video data from Source to video on display Sink 0 50 ms Max value allows for Sink to validate video data and timing. At the end of T7, Sink will indicate the detection of valid video data by setting the SINK_STATUS bit to logic 1 (DPCD 00205h, bit 0), and Sink will no longer generate automatic Black Video t8 Delay from valid video data from Source to backlight on Source - - ms Source must assure display video is stable t9 Delay from backlight off to end of valid video data Source - - ms Source must assure backlight is no longer illuminated. At the end of T9, Sink will indicate the detection of no valid video data by setting the SINK_STATUS bit to logic 0 (DPCD 00205h, bit 0), and Sink will automatically display Black Video. (See Notes: 2 and 3 below) t10 Delay from end of valid video data from Source to power off Source 0 500 ms - t11 VCCS power rail fall time, 90% to 10% Source 0.5 10 ms -

Version 2.2 7. Nov, 2013 19 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. t12 VCCS Power off time Source 500 - ms - tA LED power rail rise time, 10% to 90% Source 0.5 10 ms - tB LED power rail fall time, 90% to 10% Source 0 10 ms - tC Delay from LED power rising to LED dimming signal Source 1 - ms - tD Delay from LED dimming signal to LED power falling Source 1 - ms - tE Delay from LED dimming signal to LED enable signal Source 1 - ms - tF Delay from LED enable signal to LED dimming signal Source 1 - ms - Note (1) Please don’t plug or unplug the interface cable when system is turned on. Note (2) The Sink must include the ability to automatically generate Black Video autonomously. The Sink must automatically enable Black Video under the following conditions: - Upon LCDVCC power-on (within T2 max) - When the “NoVideoStream_Flag” (VB-ID Bit 3) is received from the Source (at the end of T9) Note (3) The Sink may implement the ability to disable the automatic Black Video function, as described in Note (2), above, for system development and debugging purposes. Note (4) The Sink must support AUX Channel polling by the Source immediately following LCDVCC power-on without causing damage to the Sink device (the Source can re-try if the Sink is not ready). The Sink must be able to response to an AUX Channel transaction with the time specified within T3 max.

Version 2.2 7. Nov, 2013 20 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. 5. OPTICAL CHARACTERISTICS

5.1 TEST CONDITIONS

Ambient Temperature Ta 25±2 oC Ambient Humidity Ha 50±10 %RH Supply Voltage V CC 3.3 V Input Signal According to typical value in "3. ELEC TRICAL CHARACTERISTICS" LED Light Bar Input Current I L 60 mA The measurement methods of optical characteristics are shown in Section 5.2. The following items should be measured under the test conditions described in Section 5.1 and stable environment shown in Note (5).

5.2 OPTICAL SPECIFICATIONS

Item Symbol Condition Min. Typ. Max. Unit Note Contrast Ratio CR 350 500 - - (2), (5),(7) TR - 3 8 ms Response Time TF - 8 13 ms (3),(7) Average Luminance of White LAVE 190 220 - cd/m 2 (4), (6),(7) Rx 0.573 - Red Ry 0.346 - Gx 0.341 - Green Gy 0.595 - Bx 0.161 - Blue By 0.115 - Wx 0.313 - Color Chromaticity White Wy Typ – 0.03 0.329 Typ + 0.03 (1),(7) Color gamut C.G θx=0° , θY =0° Viewing Normal Angle 42 45 % (8) θx+ 40 45 Horizontal θx- 40 45 - θY+ 15 20 - Viewing Angle Vertical θY- CR ≧10 40 45 - Deg. (1),(5), (7) (7) White Variation of 5& 13 Points δW 13p θx=0° , θY =0° 65 75 - %

Version 2.2 7. Nov, 2013 21 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Note (1) Definition of Viewing Angle (θx, θy): Note (2) Definition of Contrast Ratio (CR): The contrast ratio can be calculated by the following expression. Contrast Ratio (CR) = L63 / L0 L63: Luminance of gray level 63 L 0: Luminance of gray level 0 CR = CR (1) CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (6). Note (3) Definition of Response Time (TR , TF): Note (4) Definition of Average Luminance of White (LAVE ): Measure the luminance of White at 5 points L (x) is corresponding to the luminance of the point X at Figure in Note (6) 12 o’clock direction θy+ = 90º 6 o’clock θy- = 90º θx- θx+ θy- θy+ x- y+ y- x+ Normal θx = θy = 0º θX+ = 90º θX- = 90º 100% 90% 10% Gray Level 63 Gray Level 0 Gray Level 63 Time TF Optical Response TR 66.67 ms 66.67 ms

Version 2.2 7. Nov, 2013 22 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Note (5) Measurement Setup: The LCD module should be stabilized at given temperature for 20 minutes to avoid abrupt temperature change during measuring. In order to stabilize the luminance, the measurement should be executed after lighting Backlight for 20 minutes in a windless room. CS - 2000T 500 mm LCD M odule LCD P anel Center of the S creen Light Shield Room ( Ambient L uminance < 2 l u x) USB2000 Note (6) Definition of White Variation (δW): Measure the luminance of gray level 63 at 5 points / 13 points δW 5p = { Minimum [L (1)~ L (5)] / Maximum [L (1)~ L (5)]} *100% δW 13p = { Minimum [L (1)~ L (13)] / Maximum [L (1)~ L (13)]} *100% 6 7 8 2 3 4 5 11 12 13 9 10 W H 10mm 10mm W/4 W/4 W/4 W/4 H/4 10mm H/4 H/4 H/4 10mm Active area : Test Point X=1 to 13 X or equivalent or equivalent

Version 2.2 7. Nov, 2013 23 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Note (7) The listed optical specifications refer to the initial value of manufacture, but the condition of the specifications after long-term operation will not be warranted. Note (8) Definition of color gamut (C.G%): C.G%= R G B / R0 G0 B0,*100%  R0, G0, B0 : color coordinates of red, green, and blue defined by NTSC, respectively. R, G, B : color coordinates of module on 63 gray levels of red, green, and blue, respectively. R0 G0 B0 : area of triangle defined by R0, G0, B0 /uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020/uniF020 R G B: area of triangle defined by R, G, B CIE 1931 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 0.2 0.4 0.6 0.8 R G B R 0 G 0 B 0

Version 2.2 7. Nov, 2013 24 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. 6. RELIABILITY TEST ITEM Test Item Test Condition Note High Temperature Storage Test 60ºC, 240 hours Low Temperature Storage Test -20ºC, 240 hours Thermal Shock Storage Test -20ºC, 0.5hou r←→60 ℃, 0.5hour; 100cycles, 1hour/cycle High Temperature Operation Test 50ºC, 240 hours Low Temperature Operation Test 0ºC, 240 hours High Temperature & High Humidity Operation Test 50° C, 80% RH, 240 hours (1) (2) ESD Test (Operation) 150pF, 330 Ω, 1sec/cycle Condition 1 : Contact Discharge, ±8KV Condition 2 : Air Discharge, ±15KV (1) Shock (Non-Operating) 220G, 2ms, half sine wave,1 time for each direction of ±X,±Y ,±Z (1)(3) Vibration (Non-Operating) 1.5G / 10-500 Hz, Sine wave, 30 min/cycle, 1cycle for each X, Y , Z (1)(3) Note (1) criteria : Normal display image with no obvious non-uniformity and no line defect. Note (2) Evaluation should be tested after storage at room temperature for more than two hour Note (3) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that the module would not be twisted or bent by the fixture.

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7.1 MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation. (a) Model Name: N156BGE - EA1 (b) Revision: C1. (c) Serial ID: X X X X X X X Y M D L N N N N (d) Production Location: MADE IN XXXX. XXXX stands for production location. (e) UL logo: “AAAA” especially stands for panel manufactured by INNOLUX China satisfying UL requirement. Product Line Year, Month, Date INNOLUX Internal Use Revision INNOLUX Internal Use Serial No.

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7.2 CARTON

Figure. 7-1 Packing method

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7.3 PALLET

Figure. 7-2 Packing method

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7.4 UN-PACKAGING METHOD

Figure. 7.3 Un-packing method

Version 2.2 7. Nov, 2013 29 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. 8. PRECAUTIONS

8.1 HANDLING PRECAUTIONS

(1) The module should be assembled into the system firmly by using every mounting hole. Be careful not to twist or bend the module. (2) While assembling or installing modules, it can only be in the clean area. The dust and oil may cause electrical short or damage the polarizer. (3) Use fingerstalls or soft gloves in order to kee display clean during the incoming inspection and assembly process. (4) Do not press or scratch the surface harder than a HB pencil lead on the panel because the polarizer is very soft and easily scratched. (5) If the surface of the polarizer is dirty, please clean it by some absorbent cotton or soft cloth. Do not use Ketone type materials (ex. Acetone), Ethyl alcohol, Toluene, Ethyl acid or Methyl chloride. It might permanently damage the polarizer due to chemical reaction. (6) Wipe off water droplets or oil immediately. Staining and discoloration may occur if they left on panel for a long time. (7) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of contacting with hands, legs or clothes, it must be washed away thoroughly with soap. (8) Protect the module from static electricity, it may cause damage to the C-MOS Gate Array IC. (9) Do not disassemble the module. (10) Do not pull or fold the LED wire. (11) Pins of I/F connector should not be touched directly with bare hands.

8.2 STORAGE PRECAUTIONS

(1) High temperature or humidity may reduce the performance of module. Please store LCD module within the specified storage conditions. (2) It is dangerous that moisture come into or contacted the LCD module, because the moisture may damage LCD module when it is operating. (3) It may reduce the display quality if the ambient temperature is lower than 10 ºC. For example, the response time will become slowly, and the starting voltage of LED will be higher than the room temperature.

8.3 OPERATION PRECAUTIONS

(1) Do not pull the I/F connector in or out while the module is operating. (2) Always follow the correct power on/off sequence when LCD module is connecting and operating. This can prevent the CMOS LSI chips from damage during latch-up. (3) The startup voltage of Backlight is approximately 1000 Volts. It may cause electrical shock while assembling with converter. Do not disassemble the module or insert anything into the Backlight unit.

Version 2.2 7. Nov, 2013 30 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Appendix. EDID DATA STRUCTURE The EDID (Extended Display Identification Data) data formats are to support displays as defined in the VESA Plug & Display and FPDI standards. Byte # (decimal) Byte # (hex) Field Name and Comments Value (hex) Value (binary) 0 0 Header 00 00000000 1 1 Header FF 11111111 2 2 Header FF 11111111 3 3 Header FF 11111111 4 4 Header FF 11111111 5 5 Header FF 11111111 6 6 Header FF 11111111 7 7 Header 00 00000000 8 8 EISA ID manufacturer name ("CMN") 0D 00001101 9 9 EISA ID manufacturer name AE 10101110 10 0A ID product code (LSB) BD 10111101 11 0B ID product code (MSB) 15 00010101 12 0C ID S/N (fixed "0") 00 00000000 13 0D ID S/N (fixed "0") 00 00000000 14 0E ID S/N (fixed "0") 00 00000000 15 0F ID S/N (fixed "0") 00 00000000 16 10 Week of manufacture (fixed week code) 1E 00011110 17 11 Year of manufacture (fixed year code) 17 00010111 18 12 EDID structure version ("1") 01 00000001 19 13 EDID revision ("4") 04 00000100 20 14 Video I/P definition ("Digital") 95 10010101 21 15 Active area horizontal (“34.4232cm“) 22 00100010 22 16 Active area vertical (“19.3536cm“) 13 00010011 23 17 Display Gamma (Gamma = "2.2") 78 01111000 24 18 Feature support ("RGB, Non-continous") 02 00000010 25 19 Rx1, Rx0, Ry1, Ry0, Gx1, Gx0, Gy1, Gy0 E5 11100101 26 1A Bx1, Bx0, By1, By0, Wx1, Wx0, Wy1, Wy0 65 01100101 27 1B Rx=0.573 92 10010010 28 1C Ry=0.346 58 01011000 29 1D Gx=0.341 57 01010111 30 1E Gy=0.595 98 10011000 31 1F Bx=0.161 29 00101001 32 20 By=0.115 1D 00011101 33 21 Wx=0.313 50 01010000 34 22 Wy=0.329 54 01010100 35 23 Established timings 1 00 00000000 36 24 Established timings 2 00 00000000 37 25 Manufacturer's reserved timings 00 00000000 38 26 Standard timing ID # 1 01 00000001 39 27 Standard timing ID # 1 01 00000001 40 28 Standard timing ID # 2 01 00000001 41 29 Standard timing ID # 2 01 00000001

Version 2.2 7. Nov, 2013 31 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. 42 2A Standard timing ID # 3 01 00000001 43 2B Standard timing ID # 3 01 00000001 44 2C Standard timing ID # 4 01 00000001 45 2D Standard timing ID # 4 01 00000001 46 2E Standard timing ID # 5 01 00000001 47 2F Standard timing ID # 5 01 00000001 48 30 Standard timing ID # 6 01 00000001 49 31 Standard timing ID # 6 01 00000001 50 32 Standard timing ID # 7 01 00000001 51 33 Standard timing ID # 7 01 00000001 52 34 Standard timing ID # 8 01 00000001 53 35 Standard timing ID # 8 01 00000001 54 36 Detailed timing description # 1 Pixel clock ("76.42MHz") DA 11011010 55 37 # 1 Pixel clock (hex LSB first) 1D 00011101 56 38 # 1 H active ("1366") 56 01010110 57 39 # 1 H blank ("226") E2 11100010 58 3A # 1 H active : H blank 50 01010000 59 3B # 1 V active ("768") 00 00000000 60 3C # 1 V blank ("32") 20 00100000 61 3D # 1 V active : V blank 30 00110000 62 3E # 1 H sync offset ("68") 44 01000100 63 3F # 1 H sync pulse width ("45") 2D 00101101 64 40 # 1 V sync offset : V sync pulse width ("4 : 7") 47 01000111 65 41 # 1 H sync offset : H sync pulse width : V sync offset : V sync width 00 00000000 66 42 # 1 H image size (“344 mm“) 58 01011000 67 43 # 1 V image size (“193 mm“) C1 11000001 68 44 # 1 H image size : V image size 10 00010000 69 45 # 1 H boarder ("0") 00 00000000 70 46 # 1 V boarder ("0") 00 00000000 71 47 # 1 Non-interlaced, Normal, no stereo, Separate sync, H/V pol Negatives 18 00011000 72 48 Detailed timing description # 2 00 00000000 73 49 # 2 Flag 00 00000000 74 4A # 2 Reserved 00 00000000 75 4B # 2 ASCII string Model name FE 11111110 76 4C # 2 Flag 00 00000000 77 4D # 2 1st character of name (“N”) 4E 01001110 78 4E # 2 2nd character of name (“1”) 31 00110001 79 4F # 2 3rd character of name (“5”) 35 00110101 80 50 # 2 4th character of name (“6”) 36 00110110 81 51 # 2 5th character of name (“B”) 42 01000010 82 52 # 2 6th character of name (“G”) 47 01000111 83 53 # 2 7th character of name (“E”) 45 01000101 84 54 # 2 8th character of name (“-”) 2D 00101101 85 55 # 2 9th character of name (“E”) 45 01000101 86 56 # 2 10th character of name (“A”) 41 01000001 87 57 # 2 11th character of name (“1”) 31 00110001

Version 2.2 7. Nov, 2013 32 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. 88 58 # 2 New line character indicates end of ASCII string 0A 00001010 89 59 # 2 Padding with “Blank” character 20 00100000 90 5A Detailed timing description # 3 00 00000000 91 5B # 3 Flag 00 00000000 92 5C # 3 Reserved 00 00000000 93 5D # 3 ASCII string Vendor FE 11111110 94 5E # 3 Flag 00 00000000 95 5F # 3 Character of string ("C") 43 01000011 96 60 # 3 Character of string ("M") 4D 01001101 97 61 # 3 Character of string ("N") 4E 01001110 98 62 # 3 New line character indicates end of ASCII string 0A 00001010 99 63 # 3 Padding with "Blank" character 20 00100000 100 64 # 3 Padding with "Blank" character 20 00100000 101 65 # 3 Padding with "Blank" character 20 00100000 102 66 # 3 Padding with "Blank" character 20 00100000 103 67 # 3 Padding with "Blank" character 20 00100000 104 68 # 3 Padding with "Blank" character 20 00100000 105 69 # 3 Padding with "Blank" character 20 00100000 106 6A # 3 Padding with "Blank" character 20 00100000 107 6B # 3 Padding with "Blank" character 20 00100000 108 6C Detailed timing description # 4 00 00000000 109 6D # 4 Flag 00 00000000 110 6E # 4 Reserved 00 00000000 111 6F # 4 ASCII string Model Name FE 11111110 112 70 # 4 Flag 00 00000000 113 71 # 4 1st character of name (“N”) 4E 01001110 114 72 # 4 2nd character of name (“1”) 31 00110001 115 73 # 4 3rd character of name (“5”) 35 00110101 116 74 # 4 4th character of name (“6”) 36 00110110 117 75 # 4 5th character of name (“B”) 42 01000010 118 76 # 4 6th character of name (“G”) 47 01000111 119 77 # 4 7th character of name (“E”) 45 01000101 120 78 # 4 8th character of name (“-”) 2D 00101101 121 79 # 4 9th character of name (“E”) 45 01000101 122 7A # 4 10th character of name (“A”) 41 01000001 123 7B # 4 11th character of name (“1”) 31 00110001 124 7C # 4 New line character indicates end of ASCII string 0A 00001010 125 7D # 4 Padding with “Blank” character 20 00100000 126 7E Extension flag 00 00000000 127 7F Checksum 88 10001000

Version 2.2 7. Nov, 2013 33 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Appendix. OUTLINE DRAWING

Version 2.2 7. Nov, 2013 34 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited.

Version 2.2 7. Nov, 2013 35 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Appendix. SYSTEM COVER DESIGN NOTICE 0. Permanent deformation of system cover after reliability test Definition System cover including front and rear cover may deform during reliability test. Permanent deformation of system front and rear cover after reliability test should not interfere with panel. Because it may cause issues such as pooling, abnormal display, white spot, and also cell crack. 1. Design gap A between panel & any components on s ystem rear-cover Definition Gap between panel’s maximum thickness boundary & system’s inner surface components such as wire, cable, extrusion is needed for preventing from backpack or pogo test fail. Because zero gap or interference may cause stress concentration. Issues such as pooling, abnormal display, white spot, and cell crack may occur. Flatness of panel and system rear-cover should be taken into account for gap design.

2 Design gap B1 & B2 between panel & protrusions

A : 0.6mm MIN

Version 2.2 7. Nov, 2013 36 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Definition Gap between panel & protrusions is needed to prevent shock test failure. Because protrusions with small gap may hit panel during the test. Issue such as cell crack, abnormal display may occur. 3 Design gap C between system front-cover & panel s urface. Definition Gap between system front-cover & panel surface is needed to prevent pooling or glass broken. Zero gap or interference such as burr and warpage from mold frame may cause pooling issue near system font-cover opening edge. This phenomenon is obvious during swing test, hinge test, knock test, or during pooling inspection procedure. To remain sufficient gap, design with system rib higher than maximum panel thickness is recommended. 4 Design gap D1 & D2 between system front-cover & PCB Assembly. Definition Same as point 2 and 3, but focus on PCBA side. B : 2.0mm MIN C : 0.1mm MIN D1 : 0.1mm MIN D2 : 2.0mm MIN

Version 2.2 7. Nov, 2013 37 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited.

5 Interference examination of antenna cable and Web Cam wire

Antenna cable or WebCam wire should not overlap with panel outline. Because issue such as abnormal display & white spot after backpack test, hinge test, twist test or pogo test may occur.

6 System rear-cover inner surface examination

Definition Burr at logo edge, steps, protrusions or PCB board may cause stress concentration. White spot or glass broken issue may occur during reliability test.

7 Tape/sponge design on system inner surface

Definition To prevent abnormal display & white spot after scuffing test, hinge test, pogo test, backpack test, tape/sponge should be well covered under panel rear-cover. Because tape/sponge in separate location may act as pressure concentration location.

8 Material used for system rear-cover

Version 2.2 7. Nov, 2013 38 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Definition System rear-cover material with high rigidity is needed to resist deformation during scuffing test, hinge test, pogo test, or backpack test. Abnormal display, white spot, pooling issue may occur if low rigidity material is used. Pooling issue may occur because screw’s boss positioning for module’s bracket are deformed during open-close test. Solid structure design of system rear-cover may also influence the rigidity of system rear-cover. The deformation of system rear-cover should not caused interference.

9 System base unit design near keyboard and mouse p ad

Definition To prevent abnormal display & white spot after scuffing test, hinge test, pogo test, backpack test, sharp edge design in keyboard surface may damage panel during the test. We suggest to use slope edge design, or to reduce the thickness difference of keyboard/mouse pad from the nearby surface.

10 Screw boss height design

Definition Screw boss height should be designed with respect to the height of bracket bottom surface to panel bottom surface + flatness change of panel itself. Because gap will exist between screw boss and bracket, if the screw boss height is smaller. As result while fastening screw, bracket will deformed and pooling issue may occur.

11 Assembly SOP examination for system front-cover with Hook design

Version 2.2 7. Nov, 2013 39 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Definition To prevent panel crack during system front-cover assembly process with hook design, it is not recommended to press panel or any location that related directly to the panel.

12 Assembly SOP examination for system front-cover with Double tape design

Definition To prevent panel crack during system front-cover assembly process with double tape design, it is only allowed to give slight pressure (MAX 3 Kgf/50mm2) with large contact area. This can help to distribute the stress and prevent stress concentration. We also suggest putting the system on a flat surface stage to prevent unequal stress distribution during the assembly.

13 System front-cover assembly reference with Doubl e tape design

Definition To prevent system front-cover peeling at double tape contact area, Height difference between system front-cover assembly reference such as wall or components stack (wire, spacer) and double tape top surface must be less than 0.05mm.

14 Touch Application : TP and LCD Module Combinatio n for White Line Prevention

Version 2.2 7. Nov, 2013 40 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. Polarizer edge to LCD AA distance can be derived by “AA~Outline” – “CF Pol~Outline” with respect to INX 2D Outline Drawing on each side. Definition For using in Touch Application: to prevent White Line appears between TP and LCD module combination, the maximum inspection angle location must not fall onto LCD polarizer edge, otherwise light line near edge of polarizer will be appear. Parameters such as TP VA to LCD AA distance, TP assembly tolerance, TP Ink printing tolerance, Sponge thickness and tolerance, and Maximum Inspection/Viewing Angle, must be considered with respect to LCD module’s Polarizer edge location and tolerance. This consideration must be taken at all four edges separately. The goal is to find parameters combination that allow maximum inspection angle falls inside polarizer black margin area. Note: Information for Polarizer edge location and its tolerance can be derived from INX 2D Outline Drawing (“AA ~Outline“ - “CF Pol~Outline”). Note: Please feel free to contact INX FAE Engineer. By providing value of parameters above on each side, we can help to verify and pass the white line risk feasibility for your reference. Appendix. LCD MODULE HANDLING MANUAL Purpose

• This SOP is prepared to prevent panel dysfunction p ossibility through incorrect handling procedure.
• This manual provides guide in unpacking and handling steps.
• Any person which may contact / related with panel, should follow guide stated in this manual to prevent panel loss. 1. Unpacking

Version 2.2 7. Nov, 2013 41 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited. 2. Panel Lifting 3. Do and Don’t

Version 2.2 7. Nov, 2013 42 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited.

Version 2.2 7. Nov, 2013 43 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited.

Version 2.2 7. Nov, 2013 44 / 44 The copyright belongs to InnoLux. Any unauthorized use is prohibited.