N140FGE-EA2 CHIMEI | Alldatasheet
Document overview
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- PDF pages: 34
Technical content
Datasheet sections
- 1.1 OVERVIEW
- 1.2 GENERAL SPECIFICA TI0NS
- 2.1 CONNECTOR TYPE
- 3.1 ABSOLUTE RA TINGS OF ENVIRONMENT
- 3.2 ELECTRICAL ABSOLUTE RA TINGS
- 3.2.1 TFT LCD MODULE
- 4.1 FUNCTION BLOCK DIAGRAM
- 4.3 ELECTRICAL CHARACTERISTICS
- 4.3.1 LCD ELETRONICS SPECIFICA TION
- 4.3.2 LED CONVERTER SPECIFICA TION
- 4.3.3 BACKLIGHT UNIT
- 4.4 DISPLAY PORT INPUT SIGNAL TIMING SPECIFICA TIONS
- 4.4.1 DISPLA Y PORT INTERFACE
- 4.4.2 COLOR DA TA INPUT ASSIGNMENT
- 4.5 DISPLAY TIMING SPECIFICA TIONS
- 4.6 POWER ON/OFF SEQUENCE
- 5.1 TEST CONDITIONS
- 5.2 OPTICAL SPECIFICA TIONS
- 7.1 MODULE LABEL
- 7.2 CARTON
- 7.3 PALLET
- 8.1 HANDLING PRECAUTIONS
- 8.2 STORAGE PRECAUTIONS
- 8.3 OPERA TION PRECAUTIONS
Version 1.1 25 February 2013 1 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Customer: CMI Common Spec APPROVED BY SIGNATURE Name / Title Note:Reference Only for MSI Please return 1 copy for your confirmation with your signature and comments. Doc. Number: □ Tentative Specification ▓ Preliminary Specification □ Approval Specification MODEL NO.: N140FGE SUFFIX: EA2 Approved By Checked By Prepared By
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REVISION HISTORY
Version Date Page Description 0.0 Jul 25, 2012 All Tentative Spec Ver.0.0 was first issued. 1.0 Dec 25, 2012 All Preliminary Spec Ver.0.0 was first issued. 1.1 Jan 31, 2013 P4 2. MECHANICAL SPECIFICATIONS P5 3.2.1 TFT LCD MODULE P8 4.3.1 LCD ELETRONICS SPECIFICATION P10 4.3.2 LED CONVERTER SPECIFICATION P15 4.5 DISPLAY TIMING SPECIFICATIONS P18 4.6 Timing Specifications: P26~28 Appendix. EDID DATA STRUCTURE P29~30 Appendix. OUTLINE DRAWING
Version 1.1 25 February 2013 4 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 1. GENERAL DESCRIPTION
1.1 OVERVIEW
N140FGE-EA2 is a 14.0” (1 4.0” diagonal) TFT Liquid Crystal Display module with LED Backlight unit and 30 pins eDP interface. This module supports 1600 x 900 HD+ mode and can display 262,144 colors. The optimum viewing angle is at 6 o’clock direction.
1.2 GENERAL SPECIFICATI0NS
Item Specification Unit Note Screen Size 14.0” diagonal Driver Element a-si TFT active matrix - - Pixel Number 1600 x R.G.B. x 900 pixel - Pixel Pitch 0.1935 (H) x 0.1935 (V) mm - Pixel Arrangement RGB vertical stripe - - Display Colors 262,144 color - Transmissive Mode Normally white - - Surface Treatment Hard coating (3H), Anti-Glare - - Luminance, White 250 Cd/m2 Note (1) The specified po wer consumption (with converter efficiency) is under the conditions at VCCS =
3.3 V, fv = 60 Hz, LED_VCCS = Typ, fPWM = 200 Hz, Duty=100% and Ta = 25 ± 2 ºC, whereas mosaic
pattern is displayed. 2. MECHANICAL SPECIFICATIONS Item Min. Typ. Max. Unit Note Horizontal (H) 319.9 320.4 320.9 mm Vertical (V) 204.6 205.1 205.6 mm Module Size Thickness (T) - - 3.0 mm (1) Horizontal 309.6 mm Active Area Vertical 174.15 mm Weight - 270 g Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
2.1 CONNECTOR TYPE
Please refer Appendix Outline Drawing for detail design. Connector Part No.: IPEX-20455-030E-12 or Tyco 5-2069716-2 or equivalent User’s connector Part No: IPEX-20453-030T-01 or equivalent Pin1 Pin30
Version 1.1 25 February 2013 5 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 3. ABSOLUTE MAXIMUM RATINGS
3.1 ABSOLUTE RATINGS OF ENVIRONMENT
Min. Max. Unit Note Storage Temperature TST -20 +60 ºC (1) Operating Ambient Temperature TOP 0 +50 ºC (1), (2) Note (1) (a) 90 %RH Max. (Ta <= 40 ºC). (b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC). (c) No condensation. Note (2) The temperature of panel surface should be 0 ºC min. and 60 ºC max.
3.2 ELECTRICAL ABSOLUTE RATINGS
3.2.1 TFT LCD MODULE
Min. Max. Unit Note Power Supply Voltage VCCS -0.3 +4.0 V Logic Input Voltage VIN -0.3 VCCS+0.3 V (1) Converter Input Voltage LED_VCCS -0.3 (26) V (1) Converter Control Signal Voltage LED_PWM, -0.3 (5) V 1) Converter Control Signal Voltage LED_EN -0.3 (5) V (1) Note (1) Stresses beyond those listed in above “ELECTRICAL ABSOLUTE RATINGS” may cause permanent damage to the device. N ormal operation should be restricted to the conditions described in “ELECTRICAL CHARACTERISTICS”. Storage Range Relative Humidity (%RH) Operating Range Temperature (ºC) 100 80 60 -20 40 0 20 -40
Version 1.1 25 February 2013 6 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 4. ELECTRICAL SPECIFICATIONS
4.1 FUNCTION BLOCK DIAGRAM
4.2. INTERFACE CONNECTIONS PIN ASSIGNMENT Pin Symbol Description Remark
1 NC No Connection (Reserved for CMI test)
2 H_GND High Speed Ground
3 NC No Connection (Reserved)
4 NC No Connection (Reserved)
5 H_GND High Speed Ground
6 ML0- Complement Signal-Lane 0
7 ML0+ True Signal-Main Lane 0
8 H_GND High Speed Ground
9 AUX+ True Signal-Auxiliary Channel
10 AUX- Complement Signal-Auxiliary Channel
11 H_GND High Speed Ground
12 VCCS Power Supply +3.3 V (typical) 13 VCCS Power Supply +3.3 V (typical)
14 NC No Connection (Reserved for CMI test)
15 GND Ground
16 GND Ground
17 HPD Hot Plug Detect
18 BL_GND BL Ground
19 BL_GND BL Ground
20 BL_GND BL Ground
21 BL_GND BL Ground
22 LED_EN BL_Enable Signal of LED Converter
23 LED_PWM PWM Dimming Control Signal of LED
24 NC No Connection (Reserved for CMI test)
25 NC No Connection (Reserved for CMI test)
DC/DC CONVERTER & REFERENCE VOLTAGE GENERATOR INPUT CONNECTOR LED CONVERTER Converter Input Signals
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26 LED_VCCS BL Power
27 LED_VCCS BL Power
28 LED_VCCS BL Power
29 LED_VCCS BL Power
30 NC No Connection (Reserved for CMI test)
Note (1) The first pixel is odd as shown in the following figure. 1,1 (odd) 1,2 (even) 1,3 (odd) 1,4 (even) 2,1 2,2 3,1 Ymax,1 Ymax, Xmax 1,Xmax Pitch Pitch
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4.3 ELECTRICAL CHARACTERISTICS
4.3.1 LCD ELETRONICS SPECIFICATION
Min. Typ. Max. Unit Note Power Supply Voltage VCCS (3.0) (3.3) (3.6) V (1)- High Level (2.25) - (2.75) V HPD Low Level (0) - (0.4) V Ripple Voltage VRP - (50) - mV (1)- Inrush Current IRUSH - - (1.5) A (1),(2) Mosaic (215) (240) mA (3)a Power Supply Current Black lcc Note (1) The ambient temperature is Ta = 25 ± 2 ºC. Note (2) IRUSH: the maximum current when VCCS is rising IIS: the maximum current of the first 100ms after power-on Measurement Conditions: Shown as the following figure. Test pattern: black. (High to Low) (Control Signal) +12V SW 1uF VCCS +3.3V 2SK1470 Q1 2SK1475 47K VR1 47K C2 0.01uF 1uF FUSE (LCD Module Input) VCCS rising time is 0.5ms
Version 1.1 25 February 2013 9 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Note (3) The specified power supply current is under the conditions at VCCS = 3.3 V, Ta = 25 ± 2 ºC, DC Current and fv = 60 Hz, whereas a power dissipation check pattern below is displayed. Active Area b. Black Pattern Active Area a. Mosaic Pattern
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4.3.2 LED CONVERTER SPECIFICATION
Min. Typ. Max. Unit Note Converter Input power supply voltage LED_Vccs (5.0) (12.0) (21.0) V Converter Inrush Current ILEDRUSH - - (1.5) A (1) Backlight On (2.2) - (5) V EN Control Level Backlight Off (0) - (0.6) V PWM High Level (2.2) - (5) V PWM Control Level PWM Low Level (0) - (0.6) V (10) - (100) % PWM Control Duty Ratio (1) - (100) % (2) PWM Control Permissiv e Ripple Voltage VPWM_pp - - (100) mV PWM Control Frequency fPWM (100) - (500) Hz (3) LED Power Current LED_VCCS =Typ. (215) (267) (290) (284) mA (4) Note (1) ILEDRUSH: the maximum current when LED_VCCS is rising, ILEDIS: the maximum current of the first 100ms after power-on, Measurement Conditions: Shown as the following figure. LED_VCCS = Typ, Ta = 25 ± 2 ºC, fPWM = 200 Hz, Duty=100%. (High to Low) (Control Signal) LED_VCCS(T yp) SW=24V 1uF LED_VCCS(T yp) IRL3303 Q1 IRL3303 47K VR1 47K C2 0.01uF 1uF FUSE (LED Converter Input)
Version 1.1 25 February 2013 11 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 90% 10% 0.5ms ILEDRush ILEDIS ILED LED_VCC 100ms LED_PWM LED_EN Note (2) If the PWM control duty ratio is less than 10%, the re is some possibility that acoustic noise or backlight flash can be found. And it is also difficult to control the brightness linearity. Note (3) If PWM control frequency is applied in the range less than 1KHz, the “waterfall” phenomenon on the screen ma y be found. To avoid the issue, it ’s a suggestion that PWM control frequency should follow the criterion as below. PWM control frequency fPWM should be in the range N : Integer )3( N f : Frame rate Note (4) The specified LED power supply current is under the conditions at “LED_VCCS = Typ.”, Ta = 25 ± 2 ºC, fPWM = 200 Hz, Duty=100%. VLED rising time is 0.5ms
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4.3.3 BACKLIGHT UNIT
Ta = 25 ± 2 ºC Value Parameter Symbol Min. Typ. Max. Unit Note LED Light Bar Power Supply Voltage VL 25 29 30 V LED Light Bar Power Supply Current IL -- (92) -- mA (1)(2)(Duty100%) Power Consumption PL (2.30) (2.67) (2.76) W (3) LED Life Time LBL 15000 - - Hrs (4) Note (1) LED current is measured by utilizing a high frequency current meter as shown below : Note (2) For better LED light bar driving quality, it is recommended to utilize the adaptive boost converter with current balancing function to drive LED light-bar. Note (3) PL = IL ×VL (Without LED converter transfer efficiency) Note (4) The lifetime of LED is defined as the time when it continues to operate under the conditions at Ta = 25 ±2 oC and IL = 23 mA(Per EA) until the brightness becomes 50% of its original value.≦ LED Light Bar VL, IL Light Bar Feedback Channels
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4.4 DISPLAY PORT INPUT SIGNAL TIMING SPECIFICATIONS
4.4.1 DISPLAY PORT INTERFACE
Parameter Symbol Min. Typ. Max. Unit Notes Differential Signal Common Mode Voltage(MainLink and AUX) VCM 0 2 V (1)(3) AUX AC Coupling Capacitor CAUX 75 200 nF (2) Note (1) Display port interface related AC coupled signals should follow VESA DisplayPort Standard Version1. Revision 1a and VESA Embedded DisplayPortTM Standard Version 1.1. (2) The AUX AC Coupling Capacitor should be placed on Source Devices. (3)The source device should pass the test criteria described in DisplayPortCompliance Test Specification (CTS) 1.1
4.4.2 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, g reen and blue) is based on the 6 -bit gray scale data input for the color. The higher the binary input the brighter the color. The table below provides the assignment of color versus data input. Data Signal Red Green Blue Color R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Basic Colors Black Red Green Blue Cyan Magenta Yellow White Gray Scale Of Red Red(0)/Dark Red(1) Red(2) Red(61) Red(62) Red(63) VCM |VID| Single Ended VD+ VD-
Version 1.1 25 February 2013 14 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Gray Scale Of Green Green(0)/Dark Green(1) Green(2) Green(61) Green(62) Green(63) Gray Scale Of Blue Blue(0)/Dark Blue(1) Blue(2) Blue(61) Blue(62) Blue(63) Note (1) 0: Low Level Voltage, 1: High Level Voltage
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4.5 DISPLAY TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram. Refresh rate 60Hz Signal Item Symbol Min. Typ. Max. Unit Note DCLK Frequency 1/Tc (97.02) (107.8) (113.2) MHz - Vertical Total Time TV (910) (926) (1100) TH - Vertical Active Display Period TVD 900 900 900 TH - Vertical Active Blanking Period TVB TV-TVD (26) TV-TVD TH - Horizontal Total Time TH (1920) (1940) (2500) Tc - Horizontal Active Display Period THD 1600 1600 1600 Tc - DE Horizontal Active Blanking Period THB TH-THD (340) TH-THD Tc - INPUT SIGNAL TIMING DIAGRAM TH TC DCLK THD TVD Tv DE DE DATA
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4.6 POWER ON/OFF SEQUENCE
Restart Power On Power Off 10% t10 t2 90% 10% 90% Black Video t11 10% Black Video Video from Source AUX Channel Operational Link Training Idle Valid Video Data tA tC tE tB Idle or off t5 t6 t8 t9 -Power Supply for LCD, VCCS 0V 90% 10% tF tD -eDP Display -HPD from Sink -AUX Channel -Main Link Data - Power Supply for LED Converter, LED_VCCS - LED Converter Dimming Signal, LED_PWM / SM_Bus 90% 10% - LED Converter Enable Signal, LED_EN
Version 1.1 25 February 2013 17 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Timing Specifications: Value Parameter Description Reqd. By Min Max Unit Notes t1 Power rail rise time, 10% to 90% Source (0.5) (10) ms - t2 Delay from LCD,VCCS to black video generation Sink (0) (200) ms Prevents display noise until valid video data is received from the Source t3 Delay from LCD,VCCS to HPD high Sink (0) (200) ms Sink Aux Channel must be operational upon HPD high t4 Delay from HPD high to link training initialization Source - - ms Allows for Source to read Link capability and initialize t5 Link training duration Source - - ms Dependant on Source link training protocol t6 Link idle Source - - ms Min accounts for required BS-Idle pattern. Max allows for Source frame synchronization t7 Delay from valid video data from Source to video on display Sink (0) (50) ms Max allows Sink validate video data and timing t8 Delay from valid video data from Source to backlight on Source - - ms Source must assure display video is stable t9 Delay from backlight off to end of valid video data Source - - ms Source must assure backlight is no longer illuminated t10 Delay from end of valid video data from Source to power off Source (0) (500) ms - t11 VCCS power rail fall time, 90% to 10% Source (0.5) (10) ms - t12 VCCS Power off time Source (500) - ms - tA LED power rail rise time, 10% to 90% Source (0.5) (10) ms - tB LED power rail fall time, 90% to 10% Source (0) (10) ms - tC Delay from LED power rising to LED dimming signal Source (1) - ms - tD Delay from LED dimming signal to LED power falling Source (1) - ms - tE Delay from LED dimming signal to LED enable signal Source (1) - ms - tF Delay from LED enable signal to LED dimming signal Source (1) - ms - Note (1) Please don’t plug or unplug the interface cable when system is turned on. Note (2) Please avoid floating state of the interface signal during signal invalid period. Note (3) It is recommended that the backlight power must be turned on after the power supply for LCD and the interface signal is valid.
Version 1.1 25 February 2013 18 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 5. OPTICAL CHARACTERISTICS
5.1 TEST CONDITIONS
Ambient Temperature Ta 252 oC Ambient Humidity Ha 5010 %RH Supply Voltage VCC 3.3 V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS" LED Light Bar Input Current IL (92) mA The measurement methods of optical characteristics are shown in Section 5.2. The following items should be measured under the test conditions described in Section 5.1 and stable environment shown in Note (5). 5 .2 OPTICAL SPECIFICATIONS Item Symbol Condition Min. Typ. Max. Unit Note Contrast Ratio CR 350 500 - - (2), (5),(7) TR - (3) (8) ms Response Time TF - (7) (12) ms (3),(7) Average Luminance of White LAVE 212 250 - cd/m2 (4), (6),(7) Gx (0.325) - Green Gy (0.561) - Bx (0.153) - Blue By (0.144) - Wx 0.313 - Color Chromaticity White Wy x=0, Y =0 Viewing Normal Angle Typ – 0.03 0.329 Typ + 0.03 (1),(7) x+ 40 45 Horizontal x- 40 45 - Y+ 15 20 - Viewing Angle Vertical Y- CR10 40 45 - Deg. (1),(5), (7) White Variation of 5 Points W5p x=0, Y =0 80 - - % (5),(6), (7) Note (1) Definition of Viewing Angle (x, y): 12 o’clock direction y+ = 90º 6 o’clock y- = 90º x x x- y+ y- x+ Normal x = y = 0º X+ = 90º X- = 90º
Version 1.1 25 February 2013 19 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Note (2) Definition of Contrast Ratio (CR): The contrast ratio can be calculated by the following expression. Contrast Ratio (CR) = L63 / L0 L63: Luminance of gray level 63 L 0: Luminance of gray level 0 CR = CR (1) CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (6). Note (3) Definition of Response Time (TR, TF): Note (4) Definition of Average Luminance of White (LAVE): Measure the luminance of White at 5 points L (x) is corresponding to the luminance of the point X at Figure in Note (6) 100% 90% 10% Gray Level 63 Gray Level 0 Gray Level 63 Time TF Optical Response TR 66.67 ms 66.67 ms
Version 1.1 25 February 2013 20 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Note (5) Measurement Setup: The LCD module should be stabilized at given temperature for 20 minutes to avoid abrupt temperature change during me asuring. In order to stabilize the luminance, t he measurement should be executed after lighting Backlight for 20 minutes in a windless room. CS - 2000T 500 mm LCD M odule LCD P anel Center of the S creen Light Shield Room ( Ambient L uminance < 2 l u x) USB2000 Note (6) Definition of White Variation (W): Measure the luminance of White at 5 points W5p = {Minimum [L (1)~L (5)] / Maximum [L (1)~ L (5)]}*100% 6 7 8 2 3 4 5 11 12 13 9 10 W H 10mm 10mm W/4 W/4 W/4 W/4 H/4 10mm H/4 H/4 H/4 10mm Active area Note (7) The listed optical specifications refer to the initial value of manufacture, but the condition of the specifications after long-term operation will not be warranted. : Test Point X=1 to 13 X or equivalent or equivalent
Version 1.1 25 February 2013 21 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 6. RELIABILITY TEST ITEM Test Item Test Condition Note High Temperature Storage Test 60ºC, 240 hours Low Temperature Storage Test -20ºC, 240 hours Thermal Shock Storage Test -20ºC, 0.5hour←→60℃, 0.5hour; 100cycles, 1hour/cycle High Temperature Operation Test 50ºC, 240 hours Low Temperature Operation Test 0ºC, 240 hours High Temperature & High Humidity Operation Test 50°C, 80% RH, 240 hours (1) (2) ESD Test (Operation) 150pF, 330Ω, 1sec/cycle Condition 1 : Contact Discharge, ±8KV Condition 2 : Air Discharge, ±15KV (1) Shock (Non-Operating) 220G, 2ms, half sine wave,1 time for each direction of ±X,±Y,±Z (1)(3) Vibration (Non-Operating) 1.5G / 10-500 Hz, Sine wave, 30 min/cycle, 1cycle for each X, Y, Z (1)(3) Note (1) criteria : Normal display image with no obvious non-uniformity and no line defect. Note (2) Evaluation should be tested after storage at room temperature for more than two hour Note (3) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that the module would not be twisted or bent by the fixture.
Version 1.1 25 February 2013 22 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 7. PACKING
7.1 MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation. (a) Model Name: N140FGE - EA2 (b) Revision: Rev. XX, for example: C1, C2 …etc. (c) Serial ID: X X X X X X X Y M D L N N N N (d) Production Location: MADE IN XXXX. (e) UL/CB logo: XXXX is UL factory ID. Serial ID includes the information as below: (a) Manufactured Date: Year: 0~9, for 2010~2019 Month: 1~9, A~C, for Jan. ~ Dec. Day: 1~9, A~Y, for 1 st to 31st, exclude I , O and U (b) Revision Code: cover all the change (c) Serial No.: Manufacturing sequence of product (d) Product Line: 1 -> Line1, 2 -> Line 2, …etc. Product Line Year, Month, Date CMI Internal Use Revision CMI Internal Use Serial No. N140FGE-EA2 Rev.xx
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7.2 CARTON
Figure. 7-2 Packing method
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7.3 PALLET
Figure. 7-3 Packing method
Version 1.1 25 February 2013 25 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 8. PRECAUTIONS
8.1 HANDLING PRECAUTIONS
(1) The module should be assembled into the system firmly by using every mounting hole. Be careful not to twist or bend the module. (2) While assembling or installing modules, it can only be in the clean area. The dust and oil may cause electrical short or damage the polarizer. (3) Use fingerstalls or soft gloves in order to keep display clean during the incoming inspection and assembly process. (4) Do not press or scratch the surface harder than a HB pencil lead on the panel because the polarizer is very soft and easily scratched. (5) If the surface of the polarizer is dirty, please clean it by some absorbent cotton or soft cloth. Do not use Ketone type materials (ex. Acetone), Ethyl alcohol, Toluene, Ethyl acid or Methyl chloride. It might permanently damage the polarizer due to chemical reaction. (6) Wipe off water droplets or oil immediately. Staining and discoloration may occur if they left on pa nel for a long time. (7) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of contacting with hands, legs or clothes, it must be washed away thoroughly with soap. (8) Protect the module from static electricity, it may cause damage to the C-MOS Gate Array IC. (9) Do not disassemble the module. (10) Do not pull or fold the LED wire. (11) Pins of I/F connector should not be touched directly with bare hands.
8.2 STORAGE PRECAUTIONS
(1) High temperature or humidity may reduce the performance of module. Please store LCD module within the specified storage conditions. (2) It is dangerous that moisture come into or contacted the LCD module, because the moisture may damage LCD module when it is operating. (3) It may reduce the display quality if the ambient temperature is lower than 10 ºC. For example, the response time will become slowly, and the starting voltage of LED will be higher than the room temperature.
8.3 OPERATION PRECAUTIONS
(1) Do not pull the I/F connector in or out while the module is operating. (2) Always follow the correct power on/off sequence when LCD module is connecting and operating. This can prevent the CMIS LSI chips from damage during latch-up. (3) The startup voltage of Backlight is appr oximately 1000 Volts. It may cause electrical shock while assembling with converter. Do not disassemble the module or insert anything into the Backlight unit.
Version 1.1 25 February 2013 26 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Appendix. EDID DATA STRUCTURE The EDID (Extended Display Identification Data) data formats are to support displays as defined in the VESA Plug & Display and FPDI standards. Byte # (decimal) Byte # (hex) Field Name and Comments Value (hex) Value (binary) 0 0 Header 00 00000000 1 1 Header FF 11111111 2 2 Header FF 11111111 3 3 Header FF 11111111 4 4 Header FF 11111111 5 5 Header FF 11111111 6 6 Header FF 11111111 7 7 Header 00 00000000 8 8 EISA ID manufacturer name ("CMN") 0D 00001101 9 9 EISA ID manufacturer name (Compressed ASCII) AE 10101110 10 0A ID product code (N140FGE-EA2) 82 10000010 11 0B ID product code (hex LSB first; N140FGE-EA2) 14 00010100 12 0C ID S/N (fixed "0") 00 00000000 13 0D ID S/N (fixed "0") 00 00000000 14 0E ID S/N (fixed "0") 00 00000000 15 0F ID S/N (fixed "0") 00 00000000 16 10 Week of manufacture ("31") 1F 00011111 17 11 Year of manufacture ("2012") 16 00010110 18 12 EDID structure version # ("1") 01 00000001 19 13 EDID revision # ("4") 04 00000100 20 14 Video I/P definition("digital") 95 10010101 21 15 Max H image size ("31cm") 1F 00011111 22 16 Max V image size ("17"cm") 11 00010001 23 17 Display Gamma (Gamma = "2.2") 78 01111000 24 18 Feature support (Active off, RGB Color) 02 00000010 25 19 Rx1, Rx0, Ry1, Ry0, Gx1, Gx0, Gy1, Gy0 C6 11000110 26 1A Bx1, Bx0, By1, By0, Wx1, Wx0, Wy1, Wy0 75 01110101 27 1B Rx=0.593 97 10010111 28 1C Ry=0.344 58 01011000 29 1D Gx=0.325 53 01010011 30 1E Gy=0.561 8F 10001111 31 1F Bx=0.153 27 00100111 32 20 By=0.144 24 00100100 33 21 Wx=0.313 50 01010000 34 22 Wy=0.329 54 01010100 35 23 Established timings 1 00 00000000 36 24 Established timings 2 00 00000000 37 25 Manufacturer’s reserved timings 00 00000000 38 26 Standard timing ID # 1 01 00000001 39 27 Standard timing ID # 1 01 00000001 40 28 Standard timing ID # 2 01 00000001 41 29 Standard timing ID # 2 01 00000001
Version 1.1 25 February 2013 27 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 42 2A Standard timing ID # 3 01 00000001 43 2B Standard timing ID # 3 01 00000001 44 2C Standard timing ID # 4 01 00000001 45 2D Standard timing ID # 4 01 00000001 46 2E Standard timing ID # 5 01 00000001 47 2F Standard timing ID # 5 01 00000001 48 30 Standard timing ID # 6 01 00000001 49 31 Standard timing ID # 6 01 00000001 50 32 Standard timing ID # 7 01 00000001 51 33 Standard timing ID # 7 01 00000001 52 34 Standard timing ID # 8 01 00000001 53 35 Standard timing ID # 8 01 00000001 54 36 Detailed timing description # 1 Pixel clock ( "107.8"MHz, According to VESA CVT Rev1.4 ) 1C 00011100 55 37 # 1 Pixel clock (hex LSB first) 2A 00101010 56 38 # 1 H active ("1600") 40 01000000 57 39 # 1 H blank ("340") 54 01010100 58 3A # 1 H active : H blank ("1600 : 340") 61 01100001 59 3B # 1 V active ("900") 84 10000100 60 3C # 1 V blank ("26") 1A 00011010 61 3D # 1 V active : V blank ("900 : 26") 30 00110000 62 3E # 1 H sync offset ("48") 30 00110000 63 3F # 1 H sync pulse width ("32") 20 00100000 64 40 # 1 V sync offset : V sync pulse width ("3 : 5") 35 00110101 65 41 # 1 H sync offset : H sync pulse width : V sync offset : V sync width 00 00000000 66 42 # 1 H image size ("309 mm") 35 00110101 67 43 # 1 V image size ("174 mm") AE 10101110 68 44 # 1 H image size : V image size ("309 : 174") 10 00010000 69 45 # 1 H boarder ("0") 00 00000000 70 46 # 1 V boarder ("0") 00 00000000 71 47 # 1 Non-interlaced, Normal, no stereo, Separate sync, H/V pol Negatives 18 00011000 72 48 Detailed timing description # 2 00 00000000 73 49 # 2 Flag 00 00000000 74 4A # 2 Reserved 00 00000000 75 4B # 2 FE (hex) defines ASCII string (Model Name "N140FGE-EA2", ASCII) FE 11111110 76 4C # 2 Flag 00 00000000 77 4D # 2 1st character of name ("N") 4E 01001110 78 4E # 2 2nd character of name ("1") 31 00110001 79 4F # 2 3rd character of name ("4") 34 00110100 80 50 # 2 4th character of name ("0") 30 00110000 81 51 # 2 5th character of name ("F") 46 01000110 82 52 # 2 6th character of name ("G") 47 01000111 83 53 # 2 7th character of name ("E") 45 01000101 84 54 # 2 8th character of name ("-") 2D 00101101 85 55 # 2 9th character of name ("E") 45 01000101
Version 1.1 25 February 2013 28 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. 86 56 # 2 10th character of name ("A") 41 01000001 87 57 # 2 11th character of name ("2") 32 00110010 88 58 # 2 New line character indicates end of ASCII string 0A 00001010 89 59 # 2 Padding with "Blank" character 20 00100000 90 5A Detailed timing description # 3 00 00000000 91 5B # 3 Flag 00 00000000 92 5C # 3 Reserved 00 00000000 93 5D # 3 FE (hex) defines ASCII string (Vendor "CMN", ASCII) FE 11111110 94 5E # 3 Flag 00 00000000 95 5F # 3 1st character of string ("C") 43 01000011 96 60 # 3 2nd character of string ("M") 4D 01001101 97 61 # 3 3rd character of string ("N") 4E 01001110 98 62 # 3 New line character indicates end of ASCII string 0A 00001010 99 63 # 3 Padding with "Blank" character 20 00100000 100 64 # 3 Padding with "Blank" character 20 00100000 101 65 # 3 Padding with "Blank" character 20 00100000 102 66 # 3 Padding with "Blank" character 20 00100000 103 67 # 3 Padding with "Blank" character 20 00100000 104 68 # 3 Padding with "Blank" character 20 00100000 105 69 # 3 Padding with "Blank" character 20 00100000 106 6A # 3 Padding with "Blank" character 20 00100000 107 6B # 3 Padding with "Blank" character 20 00100000 108 6C Detailed timing description # 4 00 00000000 109 6D # 4 Flag 00 00000000 110 6E # 4 Reserved 00 00000000 111 6F # 4 FE (hex) defines ASCII string (Model Name "N140FGE-EA2", ASCII) FE 11111110 112 70 # 4 Flag 00 00000000 113 71 # 4 1st character of name ("N") 4E 01001110 114 72 # 4 2nd character of name ("1") 31 00110001 115 73 # 4 3rd character of name ("4") 34 00110100 116 74 # 4 4th character of name ("0") 30 00110000 117 75 # 4 5th character of name ("F") 46 01000110 118 76 # 4 6th character of name ("G") 47 01000111 119 77 # 4 7th character of name ("E") 45 01000101 120 78 # 4 8th character of name ("-") 2D 00101101 121 79 # 4 9th character of name ("E") 45 01000101 122 7A # 4 10th character of name ("A") 41 01000001 123 7B # 4 11th character of name ("2") 32 00110010 124 7C # 4 New line character indicates end of ASCII string 0A 00001010 125 7D # 4 Padding with "Blank" character 20 00100000 126 7E Extension flag 00 00000000 127 7F Checksum 0E 00001110
Version 1.1 25 February 2013 29 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Appendix. OUTLINE DRAWING
Version 1.1 25 February 2013 30 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited.
Version 1.1 25 February 2013 31 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Appendix. SYSTEM COVER DESIGN NOTICE 1. Design gap A between panel & any components on system cover Definition a). Sufficient gap between panel & system is a must for prev enting from backpack or pogo test fail. b). Zero gap from panel's maximum thickness boundary to any components, foreign objects, wire, cable or extrusion on system cover inner surface is forbidden.
2 Design gap B1 & B2 between panel & protrusions
2.0mm min. gap is recommended between panel & protrusions for preventing from shock related failures. 3 Design gap C between system front bezel & panel surface.
Version 1.1 25 February 2013 32 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Definition a). Sufficient gap between system front bezel & panel surface is a m ust for preventing from pooling or glass broken. b). Zero gap or interference is forbidden. 4 Design gap D1 & D2 between system front bezel & PCB Assembly. Definition a). Sufficient gap between system front bezel & PCB assembly is a must for preventing from abnormal display after backpack test, hinge test, twist test or pogo test. b). Zero gap or interference is forbidden.
5 Interference examination of antenna cable and WebCam wire
a). Antenna cable or WebCam wire overlap with panel outline is forbidden for preventing from abnormal display & white spot after backpack test, hinge test, twist test or pogo test. b). Antenna cable or WebCam wire bypass panel outline is recommended.
6 System inner surface examination
Version 1.1 25 February 2013 33 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Definition a). Burr at logo edge, step, protrusion or PCB board will easily cause white spot or glass broken. b). Keeping flat surface underneath backlight is recommended.
7 Tape/sponge design on system inner surface
Definition a) To prevent abnormal display & white spot after scuffing test, hinge test, pogo test, backpack test, it is not recommended to add tape/sponge in separate location. Since each tape/sponge may act as pressure concentration location. b) We suggest to design a tape/sponge that well covered under panel rear cover.
8 Assembly SOP examination
Definition To prevent panel crack during system front bezel assembly process with hook design, it is prohibited to press panel or any location that related directly to the panel.
9 Material used for system rear bezel
Version 1.1 25 February 2013 34 / 34 The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited. Definition To prevent panel crack during system front bezel assembly process without hook design, it is only allowed to give slight pressure with large contact area. This can help to distribute the stress to prevent point concentration, also it is suggest to put the system on a flat surface stage during the assembly.
10 Material used for system rear bezel
Definition a) To prevent abnormal display & white spot after scuffing test, hinge test, pogo test, backpack test, as the poor rigidity result from deformation of system rear cover during the test. b) We suggest to use aluminum-magnesium alloy as the rear frame mate rial with thickness min 1.5mm, instead of using PC/ABS.
11 System base unit design near keyboard and mouse pad
Definition To prevent abnormal display & white spot after scuffing test, hinge test, pogo test, backpack test, no sharp edge design is allowed in any area that may damage the panel during the test. We suggest to remove all sharp edges, or to reduce the thickness difference of keyboard/mouse pad from the nearby surface.