MSM66585 OKI | Alldatasheet

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¡ Semiconductor MSM66585/586/587/P587/Q587 ¡ Semiconductor MSM66585/586/587/P587/Q587 Built-in 16 bit PWM and 8 bit A/D Converter, High-speed High-preformance 16 bit Microcontroller Preliminary GENERAL DESCRIPTION MSM66585/586/587 are high-performance CMOS 16-bit microcontrollers that integrate a 16- bit CPU, ROM, RAM, 8-bit A/D converter, serial port, timers, and PWM. They also allow ROM and RAM to be expanded externally. The MSM66P587 is of OTP (One-Time PROM) version and the MSM66Q587 is of Flash EEPROM version.

FEATURES

  • Powerful instruction set Instruction set superior in orthogonal matrics 8/16-bit arithmetic instructions Multiply/divide instructions Bit manipulation instructions Bit logical operation instructions ROM table reference instructions
  • Abandant addressing modes Register addressing Page addressing Pointer register indirect addressing Stack addressing Immediate addressing
  • Minimum instruction cycle 100 ns at 20 MHz (4.5V-5.5V) 200 ns at 10 MHz (2.7V-5.5V)
  • Program memory (ROM) Internal:

64 KB (M66587/M66P587/M66Q587), 48 KB (M66585/586)

External:

1 MB, EA pin active

  • Data memory (RAM) Internal: 2 KB External: 1022 KB
  • I/O ports Analog input-only port: 4 lines (test pins for M66585) Input/output port: Maximum 80 lines (40 lines with programmable pull-up)
  • Timers Free-running counter: 16-bit ¥ 1 Realtime output: 16-bit ¥ 2 General autoreload timer: 8-bit ¥ 1
  • 16-bit PWM Input clock divider: 1 divider
  • 8-bit serial port Synchronous with BRG: 1 port E2E1033 -27-Y6 This version: Jan. 1998 Previous version: Nov. 1996

¡ Semiconductor MSM66585/586/587/P587/Q587

  • A/D converter 8-bit resolution: 4 channels
  • Interrupts Non-maskable: 1 interrupt Maskable: 9 internal, 4 external (12 vectors) 3-level priority
  • ROM window function
  • Standby modes Halt mode Stop mode
  • Package 100-pin TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM66585TS-K) (Product name : MSM66586TS-K) (Product name : MSM66587TS-K) (Product name : MSM66P587TS-K) (Product name : MSM66Q587TS-K)

¡ Semiconductor MSM66585/586/587/P587/Q587 BLOCK DIAGRAM SSP LRB PSW PC ALU ALU Control ACC System Control Instruction Decoder ROM 64 KB Memory Control Pointing R Local R. RAM 2 KB EA ALE/P5_5 PSEN/P5_4 RD/P7_1 WR/P7_0 WAIT/P7_2 AD0/P0_0 AD7/P0_7 A8/P1_0 A15/P1_7 A16/P9_0 A19/P9_3 Control Registers CPU Core 16-bit RTO/PWM Timer Serial Port PWM A to D Converter Event Timer Interrupt Peripheral Port Control DSR TSR CSR RES OSC1 OSC0 P12 P10 Bus Port Control P2_4/RT08 P2_5/RTO9 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 P7_4/PWM0 VREF AGND AI0 AI3 P4_0/ETMCK P6_0/INTO P6_1/INT1 P12_2/INT2 P12_3/INT3 NMI P7_3/CLKOUT *1. 48KB for M66585 and M66586. *2. M66585 has no internal A/D converter.

¡ Semiconductor MSM66585/586/587/P587/Q587 PIN CONFIGURATION (TOP VIEW) 100 ALE/P5_5 P5_4PSEN/P5_4 WR/P7_0 RD/P7_1 WAIT/P7_2 CLKOUT/P7_3 PWM0/P7_4 P7_5 P7_6 P7_7 GND OSC1 OSC0 VDD EA NMI RES P8_7 P8_6 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P9_7 P2_0 P2_1 P2_2 P2_3 P2_4/RT08 P2_5/RT09 P2_6 P2_7 P10_0 P10_1 P10_2 P10_3 P10_4 P10_5 P10_6 P10_7 VDD GND P6_0/INT0 P6_1/INT1 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 12_0 P9_4 P9_3/A19 P9_2/A18 P9_1/A17 P9_0/A16 GND VDD P1_7/A15 P1_6/A14 P1_5/A13 P1_4/A12 P1_3/A11 P1_2/A10 P1_1/A9 P1_0/A8 P0_7/AD7 P0_6/AD6 P0_5/AD5 P0_4/AD4 P0_3/AD3 P0_2/AD2 P0_1/AD1 P0_0/AD0 P12_1 INT2/P12_2 INT3/P12_3 P12_4 P12_5 P12_6 P12_7 VDD *(VDD) VREF (GND) AGND (TEST0) AI0 (TEST1) AI1 (TEST2) AI2 (TEST3) AI3 GND VDD ETMCK/P4_0 P4_1 P4_2 P4_3 P4_4 P4_5 P4_6 P4_7 P9_6 P9_5 For MSM66585, pin name is in parentheses ( ).

¡ Semiconductor MSM66585/586/587/P587/Q587 PIN DESCRIPTIONS Symbol Type

Description

P0_0-P0_7/ AD0-AD7 I/O P1_0-P1_7/ A8-A15 I/O P2_0-P2_3 P2_4-P2_5/ RT08-RT09 P2_6-P2_7 I/O P4_0/ETMCK P4_1-P4_7 I/O P5_4/PSEN P5_5/ALE I/O Port 0 is 8 input/output pins. Input or output can be specified for each bit with the Port 0 Mode Register (P0IO). Pull-up resistors can be specified for each bit with the Port 0 Pull-Up Register (P0PUP). These pins also function as time-multiplexed address outputs and data input/output pins (AD0-AD7) when accessing memory that has been expanded externally (program or data memory). After reset (by RES signal input, BRK instruction execution, or op code trap), P0 will be high-impedance inputs. Port 1 is 8 input/output pins. Input or output can be specified for each bit with the Port 1 Mode Register (P1IO). Pull-up resistors can be specified for each bit with the Port 1 Pull-Up Register (P1PUP). P1_0-P1_7 also have a secondary function as input/output pins for internal operation. Their secondary function can be set for each bit with the Port 1 Secondary Function Control Register (P1SF). The input/output settings by P1IO will be ignored for pins that have been set to the secondary function by P1SF. These pins function as output pins for address A8-A15 when accessing program memory or data memory that has been expanded externally. When the EA pin is low, A8-A15 will be output regardless of P1SF settings. After reset (by RES signal input, BRK instruction execution, or op code trap), P1 will be high-impedance inputs. P2_4 and P2_5 also have a secondary function as input/output pins for internal operation. Their secondary function can be set for each bit with the Port 2 Secondary Function Control Register (P2SF). The input/output settings of P2IO will be ignored for pins that have been set to the secondary function by P2SF. These pins output a previously set level when the value of Timer Registers 8 and 9 match a selected counter value. After reset (by RES signal input, BRK instruction execution, or op code trap), P2 will be high-impedance inputs. Port 4 is 8 input/output pins. Input or output can be specified for each bit with the Port 4 Mode Register (P4IO). Pull-up resistors can be specified for each bit with the Port 4 Pull-Up Register (P4PUP). P4_0 also has a secondary function as an input pin for internal operation. Its secondary function can be set for the bit with the Port 4 Secondary Function Control Register (P4SF). The input/output settings by P4IO will be ignored for pins that have been set to the secondary function by P4SF. This is the external clock input pin for the counter of a general 8-bit timer. After reset (by RES signal input, BRK instruction execution, or op code trap), P4 will be high-impedance inputs. Port 5 is 2 input/output pins. Input or output can be specified for each bit with the Port 5 Mode Register (P5IO). P5_4 and P5_5 also have a secondary function as output pins for internal operation. Their secondary function can be set for each bit with the Port 5 Secondary Function Control Register (P5SF). The input/output settings of P5IO will be ignored for pins that have been set to the secondary function by P5SF. PSEN (P5_4): This pin outputs the strobe signal for read operations when external program memory is accessed. Operation will automatically switch to the secondary function when the EA pin is low. This pin will be pulled up when both the EA pin and RESET pin are low. ALE (P5_5): This pin outputs the strobe for externally latching the lower 8 address bits output from P0 when external memory is accessed. Operation will automatically switch to the secondary function when the EA pin is low. This pin will be pulled up when both the EA pin and RESET pin are low. After reset (by RES signal input, BRK instruction execution, or op code trap), P5 will be high-impedance inputs.

¡ Semiconductor MSM66585/586/587/P587/Q587 PIN DESCRIPTIONS (Continued) Symbol Type P6_0/INT0 P6_1/INT1 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 Port 6 is 6 input/output pins. Input or output can be specified for each bit with the Port 6 Mode Register (P6IO). P6_0-P6_5 also have a secondary function as input/output pins for internal operation. Their secondary function can be set for each bit with the Port 6 Secondary Function Control Register (P6SF). The input/output settings of P6IO will be ignored for pins that have been set to the secondary function by P6SF. INT0 (P5_0), INT1 (P6_1): These pins input external interrupts 0 and 1. RXD1 (P6_2): This pin inputs receive data to the Serial Port 1 receive circuit. TXD1 (P6_3): This pin outputs transmit data to the Serial Port 1 transmit circuit. RXC1 (P6_4): This pin outputs the shift clock when the Serial Port 1 receive circuit is in master mode. It inputs the shift clock when the receive circuit is in slave mode. TXC1 (P6_4): This pin outputs the shift clock when the Serial Port 1 transmit circuit is in master mode. It inputs the shift clock when the transmit circuit is in slave mode. After reset (by RES signal input, BRK instruction execution, or op code trap), P6 will be high-impedance inputs. I/O P7_0/WR P7_1/RD P7_2/WAIT P7_3/CLKOUT P7_4/PWM0 P7_5-P7_7 Port 7 is 8 input/output pins. Input or output can be specified for each bit with the Port 7 Mode Register (P7IO). P7_0-P7_4 also have a secondary function as input/output pins for internal operation. Their secondary function can be set for each bit with the Port 7 Secondary Function Control Register (P7SF). The input/output settings of P7IO will be ignored for pins that have been set to the secondary function by P7SF. WR (P7_0): This pin outputs the strobe signal for write operations when external data memory is accessed. RD (P7_1): This pin outputs the strobe signal for read operations when external data memory is accessed. WAIT (P7_2): This pin inputs a wait to the internal CPU when external data memory with a slow access time is accessed. CPU is driven to "WAIT" state during WAIT pin high. CLKOUT (P7_3): This pin outputs the clock pulses set by the Peripheral Control Register (PRPHF). PWM0 (P7_4): This pin outputs PWM0. After reset (by RES signal input, BRK instruction execution, or op code trap), P7 will be high-impedance inputs. When P7_0 and P7_1 are used as their secondary functions (WR, RD), they need to be connected externally to pull-up resistors. I/O P8_0-P8_7 I/O Port 8 is 8 input/output pins. Input or output can be specified for each bit with the Port 8 Mode Register (P8IO). After reset (by RES signal input, BRK instruction execution, or op code trap), P8 will be high-impedance inputs.

¡ Semiconductor MSM66585/586/587/P587/Q587 PIN DESCRIPTIONS (Continued) Symbol Type P9_0P9_3/ A16-A19 P9_4-P9_7 I/O P10_0-P10_7 Port 10 is 8 input/output pins. Input or output can be specified for each bit with the Port 10 Mode Register (P10IO). Pull-up resistors can be specified for each bit with the Port 10 Pull-Up Register (P10PUP). After reset (by RES signal input, BRK instruction execution, or op code trap), P10 will be high-impedance inputs. I/O P12_0-P12_1 P12_2-P12_3/ INT2-INT3 P12_4-P12_7 I/O Port 9 is 8 input/output pins. Input or output can be specified for each bit with the Port 9 Mode Register (P9IO). Pull-up resistors can be specified for each bit with the Port 9 Pull-Up Register (P9PUP). P9_0-P9_3 also have a secondary function as output pins for internal operation. Their secondary function can be set for each bit with the Port 9 Secondary Function Control Register (P9SF). The input/output settings of P9IO will be ignored for pins that have been set to the secondary function by P9SF. These pins function as output pins for address A16-A19 when accessing program memory or data memory that has been expanded externally. Note that program memory address A16-A19 will be output even when accessing data memory that has been expanded externally. When the EA pin is low and program memory that has been expanded externally is accessed, A16-A19 will be output regardless of P9SF settings. After reset (by RES signal input, BRK instruction execution, or op code trap), P9 will be high-impedance inputs. Port 12 is 8 input/output pins. Input or output can be specified for each bit with the Port 12 Mode Register (P12IO). P12_2 and P12_3 also have a secondary function as input pins for internal operation. Their secondary function can be set for each bit with the Port 12 Secondary Function Control Register (P12SF). The input/output settings of P12IO will be ignored for pins that have been set to the secondary function by P12SF. INT2 (P12_2), INT3 (P12_3): These pins input external interrupts 2 and 3. After reset (by RES signal input, BRK instruction execution, or op code trap), P12 will be high-impedance inputs. AI0-AI3 These are analog input pins for the A/D converter (test pins for MSM66585). I VREF This is the reference voltage pin for the A/D converter (VDD for MSM66585). I AGND This is the ground input pin for the A/D converter (GND for MSM66585). I OSC0 This pins connect to a crystal oscillator, ceramic oscillator, or capacitors for base clock oscillation. When the base clock is to be supplied externally, it should be input on the OSC0 pin with the OSC1 pin left open. I NMI This input pin requests a non-maskable interrupt. I RES This is an active-low reset input pin. I EA I VDD These are voltage pins. All VDD pins (9, 17, 37, 67, 93) should be connected to the supply voltage (for MSM66585 connect pins 9, 10, 17, 37, 67, 93). I GND These are ground pins. All GND pins (16, 40, 68, 94) should be connected to ground (for MSM66585 connect pins 11, 16, 40, 68, 94). I When this pin is high, program addresses 0H-FFFFH will access internal program memory and program addresses 10000H-FFFFFH will access external program memory. To access external program memory, P1, P5, and P9 must be set with their secondary function control registers. When this pin is low, all program addresses will access external program memory. OSC1 O

¡ Semiconductor MSM66585/586/587/P587/Q587 MEMORY MAP Program Area 17FFH 1800H FFFFH 0FFFH 1000H 0069H 006AH 0049H 004AH 0000H Vector table area 74 bytes VCAL table area 32 bytes ACAL area 2 KB ACAL area 2 KB 17FFH 1800H FFFFH 0FFFH 1000H 0000H External ROM area Segment 0 Segment 1 to 15 Internal ROM area Vector table area 8 bytes 0071H 0072H * For M66585 and M66586 addresses 0C000H to 0FFFFH of segment 0 are external ROM area.

¡ Semiconductor MSM66585/586/587/P587/Q587 Data Area 0000H 00FFH 0100H 01FFH 0200H 02FFH 0300H 09FFH 0A00H 0FFFH 1000H External memory area SFR area Expanded SFR area Segment 0 Segment 1-15 Internal RAM area Local register setting area ROM window setting area External memory area Common area 1FFFH 3FFFH 7FFFH 03FFH BCB Common range 0-03FFH 0-1FFFH 0-3FFFH 0-7FFFH SFR area Expanded SFR area FIX area USP DP USP USP DP USP DP Pointing register sets SCB=0 SCB=1 SCB=7 Expanded SFR area SBA area 64 bytes Fixed page area The SBA area that can be accessed using SB, RB, JBS, and JBR instruction. 01FFH 0200H 0208H 0210H 0238H 0240H 02C0H 0300H 0000H 0FFFH 1000H FFFFH 7FFFH 8000H FFFFH ROM window setting area FIX area

¡ Semiconductor MSM66585/586/587/P587/Q587 Area For Setting Local Registers ER0 ER1 ER2 ER3 ER0 0200H 0208H 0A00H LRBL= 00H LRBL= 01H LRBL= FFH ER3 Area for setting local registers: Specify 8-byte block with 8-bits of LRBL 0000H 0100H 0200H 0300H 0A00H FIX area Expanded SFR area SFR area Internal RAM area External RAM area FFFFFH

¡ Semiconductor MSM66585/586/587/P587/Q587 ABSOLUTE MAXIMUM RATINGS Digital power supply voltage Symbol Units Conditions Parameter Rating Input voltage Output voltage Analog power supply voltage Analog reference voltage Analog input voltage Power dissipation Storage temperature VDD VI VO AVDD VREF VAI PD TSTG GND=AGND=0V Ta=25°C Ta=70°C Per package Per output –0.3 to +7.0 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –0.3 to AVDD+0.3 –0.3 to VREF –50 to +150 V V V V V V mW mW 650 Note: Power and ground connections must be made to all external VDD and GND pins. ALLOWABLE OUTPUT CURRENT "H" output pin (1 pin) Symbol Units Pin Parameter Min. "H" output pin (total) "L" output pin (1 pin) "L" output pin (total) IOH SIOH IOL SIOL mA All output pins Total of all output pins All output pins Total of P0, P1, P5 and P7 Total of P2, P9 and P10 Total of P4 and P8 Total of all output pins Total of P6 and P12 Typ. Max. –40 100 (VDD=2.7 to 5.5V, Ta=–30 to +70°C) RECOMMENDED OPERATING CONDITIONS Symbol Units Conditions Parameter Range Analog reference voltage Analog input voltage Memory hold voltage Operating frequency Temperature range Fan-out VREF VAI VDDH fOSC Ta N TTL loads P0, P5_4, P5_5, P7_0, P7_1 P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12 AVDD–0.3 to AVDD AGND to VREF 2.0 to 5.5 2 to 20 –30 to +70 V V V MHz fOSC=0Hz VDD=5V±10% VDD V fOSC£20MHz 4.5 to 5.5 Digital power supply voltage MOS loads fOSC£10MHz 2.7 to 5.5 VDD=2.7 to 5.5V 2 to 10 MHz

¡ Semiconductor MSM66585/586/587/P587/Q587

ELECTRICAL CHARACTERISTICS

DC Characteristics (VDD=5V±10%) Input high voltage Symbol Units Conditions Parameter Min Input low voltage Input low voltage Output high voltage VIH VIL VOH V (Ta=–30 to +70°C) Input high voltage 0.44VDD Typ Max 2, 4, 5, 6, 7 2, 4, 5, 6, 7 1, 4 VDD+0.3 0.80VDD VDD+0.3 –0.3 0.16VDD –0.3 0.2VDD VDD–0.4 Output high voltage VDD–0.4 IO=–400mA IO=–200mA Output low voltage VOL 1, 4 0.4 Output low voltage 0.8 IO=3.2mA IO=1.6mA Input leakage current Input current Input current IIH/IIL 3, 6 VI=VDD/0V 1/–1 1/–250 15/–15 mA Output leakage current 1, 2, 4 ±10 ILO VO=VDD/0V mA Input capacitance Output capacitance CI CO f=1MHz, Ta=25°C pF A/D conversion operating A/D conversion stopped mA mA IREF Analog reference power supply current 0.2 100 VDD=2V, Ta=25°C* mA IDDS Supply current (stop mode) Supply Current (halt mode) Supply Current IDDH IDD fOSC=20MHz, No Load mA Pull-up resistor Rpull VI=0V kW 100 IO=–2.0 mA IO=–2.0 mA VDD–0.6 VDD–0.6 IO=5.0mA IO=5.0mA 0.4 0.8 1. Applies to P0. 2. Applies to P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12. 3. Applies to Ain. 4. Applies to P5_4, P5_5, P7_0, P7_1. 5. Applies to RES. 6. Applies to EA, NMI. 7. Applies to OSC0. For input ports, VDD or 0 V. For other cases, unloaded.

¡ Semiconductor MSM66585/586/587/P587/Q587 DC Characteristics (2.7V £ VDD £ 5.5V) Input high voltage Symbol Units Conditions Parameter Min Input low voltage Input low voltage Output high voltage VIH VIL VOH V (Ta=–30 to +70°C) Input high voltage 0.44VDD Typ Max 2, 4, 5, 6, 7 2, 4, 5, 6, 7 1, 4 VDD+0.3 0.80VDD VDD+0.3 –0.3 0.16VDD –0.3 0.2VDD VDD–0.4 Output high voltage VDD–0.4 IO=–400mA IO=–200mA Output low voltage VOL 1, 4 0.5 Output low voltage 0.5 IO=3.2mA IO=1.6mA Input leakage current Input current Input current IIH/IIL 3, 6 VI=VDD/0V 1/–1 1/–250 15/–15 mA Output leakage current 1, 2, 4 ±10 ILO VO=VDD/0V mA Input capacitance Output capacitance CI CO f=1MHz, Ta=25°C pF A/D conversion operating A/D conversion stopped mA mA IREF Analog reference power supply current 0.2 100 VDD=2V, Ta=25°C* mA IDDS Supply current (stop mode) Supply current (halt mode) Supply current IDDH IDD fOSC=10MHz, No Load mA Pull-up resistor Rpull VI=0V,VDD=5V±10% kW 100 IO=–2.0 mA IO=–2.0 mA IO=5.0mA IO=5.0mA VDD–0.6 VDD–0.8 0.9 1.2 VI=0V, VDD=3V±10% 100 VDD=5.5V VDD=3.3V VDD=5.5V VDD=3.3V VDD=5V±10% VDD=3V±10% VDD=5V±10% VDD=3V±10% 200 1. Applies to P0. 2. Applies to P1, P2, P4, P6, P7_2-P7_7, P8-P10, P12. 3. Applies to Ain. 4. Applies to P5_4, P5_5, P7_0, P7_1. 5. Applies to RES. 6. Applies to EA, NMI. 7. Applies to OSC0. For input ports, VDD or 0 V. For other cases, unloaded.

¡ Semiconductor MSM66585/586/587/P587/Q587 AC Characteristics (VDD=5V±10%)

  • External Program Memory Control ALE pulse width Symbol Units Conditions Parameter Min PSEN pulse width PSEN pulse delay time Low address setup time Low address hold time High address setup time tfW tALS ns (Ta=–30 to +70°C) Clock (OSC) pulse width CL=50pF 2tfW–2 2tfW–5 tfW–3 2tfW–3 tfW–3 4tfW–3 High address hold time Instruction setup time Instruction hold time Max tfW+3 2tfW+3 tfW+3 4tfW+3 tfW+3 tfW–3 tAW tPW tPAD tALH tIS tAHS tAPH tIH CLK ALE tfW tfW PSEN tAW tPAD tPW AD 0-AD7 PC 0-7 INST 0-7 tALS tALH tIS tIH A 8-A19 PC 8-19 tAHS tAPH

¡ Semiconductor MSM66585/586/587/P587/Q587

  • External Data Memory Control ALE pulse width Symbol Units Conditions Parameter Min RD pulse width WR pulse width RD pulse delay time WR pulse delay time Low address setup time tfW tRAD ns (Ta=–30 to +70°C) Clock (OSC) pulse width CL=50pF 2tfW–2 2tfW–5 2tfW–5 tfW–3 tfW–3 2tfW–3 Low address hold time tfW–3 High address setup time 3tfW–3 High address hold time tfW–3 Max tfW+3 tfW+3 2tfW+3 tfW+3 3tfW+3 tfW+3 tAW tRW tWW tWAD tAHS tALS tALH tAHH Memory data setup time Memory data hold time Data delay time tALH–0 Data hold time tfW–3 tfW–3 tALH+5 tfW+3 tDD tMS tMH tDH CLK ALE tfW tfW tAW RD tRAD tRW AD 0-AD7 RAP 0-7 DIN 0-7 tALS tALH tMS tMH A 8-A19 RAP 8-19 tAHS tAHH WR tWAD tWW AD 0-AD7 RAP 0-7 DOUT 0-7 tALS tALH tDH A 8-A19 RAP 8-19 tAHS tAHH tDD

¡ Semiconductor MSM66585/586/587/P587/Q587

  • Serial Port Contorl Master mode Serial clock cycle time Symbol Units Conditions Parameter Min. Output data setup time Output data hold time Input data setup time Input data hold time tfW tSRMXS ns (Ta=–30 to +70°C) Clock (OSC) pulse width CL=50pF 8tfW 4tfW–5 3tfW–10 Typ. tSCKC tSTMXS tSTMXH tSRMXH Max. tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS SCK tSTMXS tSRMXH Valid Valid

¡ Semiconductor MSM66585/586/587/P587/Q587 AC timing mesurement point Slave mode Serial clock cycle time Symbol Units Conditions Parameter Min. Output data setup time Output data hold time Input data setup time Input data hold time tfW tSRMXS ns (Ta=–30 to +70°C) Clock (OSC) pulse width CL=50pF 8tfW 2tfW–15 4tfW–10 Typ. tSCKC tSTMXS tSTMXH tSRMXH Max. tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS SCK tSTMXS tSRMXH Valid Valid VDD 0.8VDD 0.8VDD 0.2VDD 0.2VDD

¡ Semiconductor MSM66585/586/587/P587/Q587 AC Characteristics (2.7V £ VDD £ 5.5V)

  • External Program Memory Control ALE pulse width Symbol Units Conditions Parameter Min PSEN pulse width PSEN pulse delay time Low address setup time Low address hold time High address setup time tfW tALS ns (Ta= –30 to +70°C) Clock (OSC) pulse width CL=50pF 2tfW–4 2tfW–10 tfW–6 2tfW–6 tfW–6 4tfW–6 High address hold time Instruction setup time Instruction hold time Max tfW+6 2tfW+6 tfW+6 4tfW+6 tfW+6 tfW–6 tAW tPW tPAD tALH tIS tAHS tAPH tIH CLK ALE tfW tfW PSEN tAW tPAD tPW AD 0-AD7 PC 0-7 INST 0-7 tALS tALH tIS tIH A 8-A19 PC 8-19 tAHS tAPH

¡ Semiconductor MSM66585/586/587/P587/Q587

  • External Data Memory Control ALE pulse width Symbol Units Conditions Parameter Min RD pulse width WR pulse width RD pulse delay time WR pulse delay time Low address setup time tfW tRAD ns (Ta= –30 to +70°C) Clock (OSC) pulse width CL=50pF 2tfW–4 2tfW–10 2tfW–10 tfW–6 tfW–6 2tfW–6 Low address hold time tfW–6 High address setup time 3tfW–6 High address hold time tfW–6 Max tfW+6 tfW+6 2tfW+6 tfW+6 3tfW+6 tfW+6 tAW tRW tWW tWAD tAHS tALS tALH tAHH Memory data setup time Memory data hold time Data delay time tALH–0 Data hold time tfW–6 tfW–6 tALH+10 tfW+6 tDD tMS tMH tDH CLK ALE tfW tfW tAW RD tRAD tRW AD 0-AD7 RAP 0-7 DIN 0-7 tALS tALH tMS tMH A 8-A19 RAP 8-19 tAHS tAHH WR tWAD tWW AD 0-AD7 RAP 0-7 DOUT 0-7 tALS tALH tDH A 8-A19 RAP 8-19 tAHS tAHH tDD

¡ Semiconductor MSM66585/586/587/P587/Q587

  • Serial Port Control Master mode Serial clock cycle time Symbol Units Conditions Parameter Min. Output data setup time Output data hold time Input data setup time Input data hold time tfW tSRMXS ns (Ta=–30 to +70°C) Clock (OSC) pulse width CL=50pF 8tfW 4tfW–10 3tfW–20 Typ. tSCKC tSTMXS tSTMXH tSRMXH Max. tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS SCK tSTMXS tSRMXH Valid Valid

¡ Semiconductor MSM66585/586/587/P587/Q587 Slave mode AC timing mesurement point Serial clock cycle time Symbol Units Conditions Parameter Min. Output data setup time Output data hold time Input data setup time Input data hold time tfW tSRMXS ns (Ta= –30 to +70°C) Clock (OSC) pulse width CL=50pF 8tfW 2tfW–30 4tfW–20 Typ. tSCKC tSTMXS tSTMXH tSRMXH Max. tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS SCK tSTMXS tSRMXH Valid Valid VDD 0.8VDD 0.8VDD 0.2VDD 0.2VDD

¡ Semiconductor MSM66585/586/587/P587/Q587 A/D Converter Characteristics Recommended Circuit Linearity error Symbol Units Conditions Item Min Differential linearity error Zero scale error Full scale error Conversion time EL EFS LSB (Ta=–30 to +70°C, VDD=VREF=5V±10%, AGND=GND=0V, fOSC=20MHz) Resolution Refer to the recommended circuit Analog input source impedance RI£5kW tCONV=19.2msec Typ Max ms/CH Bit 6.4 19.2 n ED EZS tCONV by ADTM set data A/D Converter Characteristics Linearity error Symbol Units Conditions Item Min Differential linearity error Zero scale error Full scale error Conversion time EL EFS LSB (Ta=–30 to +70°C, VDD=VREF=3V±10%, AGND=GND=0V, fOSC=10MHz) Resolution Refer to the recommended circuit Analog input source impedance RI£5kW tCONV=38.4msec Typ Max ms/CH Bit 38.4 n ED EZS tCONV ADTM=00b (384CLK selection) ±0.5 Reference Voltage Analog Voltage CI 0.1 mF mF VREF AI0~ AI3 AGND GND VDD 0.1 mF mF +5V RI (analog input source impedance) £ 5kW Cl = 0.1 mF RI 0.1 mF

¡ Semiconductor MSM66585/586/587/P587/Q587 Definition of terms

  • Resolution Resolution is the minimum input analog value that can be resolved. With 8 bits, 28=256 so resolution can be to (VREF-AGND) ÷ 256.
  • Linearity error Linearity error is the difference between actual conversion characteristics and ideal conversion characteristics of an 8-bit A/D converter (so this does not include quantization error). Ideal conversion characteristics would be to divide the voltage between VREF and AGND into 256 equal steps.
  • Differential linearity error Differential linearity error indicates slope of conversion characteristics. The change in analog input voltage value that would change the digital output by one bit is ideally 1 LSB = (VREF-AGND) ÷ 256, so differential linearity error is the difference between this ideal bit size and the actual bit size anywhere in the conversion range.
  • Zero scale error Zero scale error is the difference between actual conversion characteristics and ideal conversion characteristics at the point where digital output switches from 00H to 01H.
  • Full scale error Full scale error is the difference between actual conversion characteristics and ideal conversion characteristics at the point where digital output switches from FEH to FFH.

¡ Semiconductor MSM66585/586/587/P587/Q587 (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). TQFP100-P-1414-0.50-K Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP. Mirror finish