MSC1205 OKI | Alldatasheet

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¡ Semiconductor MSC1205 ¡ Semiconductor MSC1205 32-Bit Duplex Controller/Driver with Digital Dimming Function GENERAL DESCRIPTION The MSC1205 is a Bi-CMOS display driver for a 1/2-duty vacuum fluorescent display tube. It consists of a 64-bit shift register, latch circuits, a digital diming circuit, and drivers. The MSC1205 provides an interface with a microcomputer only by three signal lines: LOAD, DATA, and CLOCK.

FEATURES

  • Power Supply Voltage: 8 to 18V (built-in 5V regulator for logic)
  • Built-in 1-terminal RC oscillation circuit (with external capacitor)
  • Built-in digital dimming circuit 10-bit resolution Programmable in the duty range of 0/2048 (0%) to 1015.5/2048 (49.6%).
  • Can directly drive 32 · 2 display anodes.
  • Built-in power-on reset circuit
  • Package options: 42-pin plastic DIP (DIP42-P-600-2.54) (Product name: MSC1205-RS) 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSC1205GS-2K) E2C0018-27-Y3 This version: Nov. 1997 Previous version: Jul. 1996

¡ Semiconductor MSC1205 BLOCK DIAGRAM GRID1 GRID2 VDD VSS VOLTAGE REGU- LATOR SEG32 SEG31 SEG2 SEG1 DRIVER 32 bits 8 to 18V 5V32 bits LEVEL SHIFTER BL ST MULTIPLEXER 32 bits 32 bits LATCHL 64 bitsLATCHL Q1-Q10 Q1-Q64 D Q1-Q64 (64 bits) SHIFT REGISTER D (2 bits) DATA CLOCK (POR) LOAD TIMING CONTROL (DIMLD) (SEGLD) 10 bits OSC (fosc) Rbo 10 bits COMPA- RATOR (bo) TIMING GENE- RATOR DOWN COUNTER BLANK OSC LOAD TEST LATCH L

¡ Semiconductor MSC1205 INPUT AND OUTPUT CONFIGURATION

  • Schematic Diagrams of Logic Portion Input Circuit 1
  • Schematic Diagrams of Logic Portion Input Circuit 2
  • Schematic Diagrams of Logic Portion Input Circuit 3
  • Schematic Diagrams of Driver Output Circuit VSS VDD VSS INPUT (5V Reg.) VSS (5V Reg.)VDD VSS BLANK VSS (5V Reg.)VDD VSS TEST VSS VDD VSS OUTPUT VDD

¡ Semiconductor MSC1205 PIN CONFIGURATION (TOP VIEW) DATA V SS CLOCK TEST LOAD OSC SEG1 BLANK SEG2 GRID2 SEG3 GRID1 SEG4 V DD SEG5 SEG32 SEG6 SEG31 SEG7 SEG30 SEG8 SEG29 SEG9 SEG28 SEG10 SEG27 SEG11 SEG26 SEG12 SEG25 SEG13 SEG24 SEG14 SEG23 SEG15 SEG22 SEG16 SEG21 SEG17 SEG20 SEG18 SEG19 1 42 24 1 3 40 4 39 53 8 63 7 7 36 83 5 9 34 10 33 11 32 12 31 13 30 14 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 42-Pin Plastic DIP

¡ Semiconductor MSC1205 PIN CONFIGURATION (TOP VIEW) SEG24 SEG14 SEG15 SEG16 SEG17 SEG18 NC SEG19 SEG20 SEG21 SEG22 SEG23 SEG2 SEG1 LOAD CLOCK DATA NC V SS TEST OSC BLANK GRID2 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 V DD GRID1 NC : No-connection pin 44-Pin Plastic QFP /#03/#05

¡ Semiconductor MSC1205 PIN DESCRIPTION Symbol DATA LOAD

Description

Serial data input pin. This pin receives display data, dimming data, enable bit and mode bit. Shift clock input pin with Schmitt circuit. Serial data is clocked in this pin at the rising edge of the shift clock pulse. Load pulse input pin. The load signal is input when dimming data and segment data transfer is finished. Power supply voltage. This pin is connected to a power supply of 8 to 18V. Grid driver output pin. When this pin is set to "L", the display is turned on. This pin is connected to external PNP transistor. The segment data of the first bit (S1) to the 32nd bit (S32) is valid in the segment data of 64 bits. Display blank input pin with a pull-up resistor. When this pin is set to "L", the display is turned off (SEGn = "L") Segment driver output pins. These pins provide large current driving (I OH = –5.5mA at VDD = 12V) and small current driving (IOH = –1.8mA at VDD = 12V). Oscillation input pin. This pin is connected to an external capacitor of 82pF. A standard oscillation frequency is 512kHz. CLOCK SEG1 -SEG32 VDD GRID1 Test input pin with a pull-down resistor. Normally this pin should be left open or should be connected to ground. Ground pin. This pin is connected to ground (VSS = 0) OSC TEST VSS GRID2 BLANK Grid driver output pin. When this pin is set to "L", the display is turned on. This pin is connected to external PNP transistor. The segment data of the 33rd bit (S33) to the 64th bit (S64) is valid in the segment data of 64 bits. Type I I I O O O I I I

¡ Semiconductor MSC1205 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Ta = 25°CSupply Voltage V DD –0.3 to +20 V Ta = 25°CInput Voltage V IN –0.3 to +6.0 V —Storage Temperature Range T STG –65 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit —Power Supply Voltage V DD 8 to 18 V —Operating Temperature Range T op –40 to +85 °C

ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition Min. Max. Applicable pin (Ta = –40 to +85˚C, VDD = 8 to 18V) High Level Output Voltage (1) (Small Current Driver) V IH VIL IIH1 IIH3 VI = 5V 3.8 –0.3 0.8 –100 Low Level Output Voltage VDD = 12V, IOH5 = –5.5mA High Level Input Current Low Level Input Current IIL1 IIL2 –500 5.5

1 DATA, LOAD

Voltage (2) (Large Current Driver) High Level Output Voltage (3) Current Consumption IIL3 VI = 5V VI = 0V VI = 0V VI = 0V VDD = 9.5V, IOH1 = –1.3mA VDD = 12V, IOH2 = –1.8mA VDD = 15V, IOH3 = –2.3mA VDD = 9.5V, IOH4 = –4.1mA VDD = 15V, IOH6 = –7.0mA VDD = 9.5V, IOL1 = 1mA VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOL1 VOH7 IDD VDD = 9.5V, IOH7 = –0.8mA fOSC = 512kHz, no load VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 500 Unit V V mA V V V V mA mA mA V V V V mA mA TEST DATA, LOAD CLOCK BLANK TEST SEG (2n) n = 1-16 SEG (2n-1) n = 1-16 SEG1-SEG32 GRID1, GRID2 GRID1, GRID2 VDD = 9.5V, IOL2 = 500mA VDD = 9.5V, IOL3 = 2mA 0.3 V—VOL2 V—VOL3

¡ Semiconductor MSC1205 AC Characteristics GRIDn SEGn SEGMENT DATA DIMMING DATA 3.8V 0.8V 3.8V 0.8V 3.8V 0.8V 0.9VDD 0.1VDD CLOCK DATA LOAD DATA CLOCK LOAD fC tDS tDH tCW tCW tcr tCL tcf tLC tLW tr tf Parameter Symbol Condition Min. Typ. Max. Unit (Ta = –40 to +85˚C, VDD = 8 to 18V) Clock Frequency f C(1/tclock) tCW tcr, tcf tDS MHz 500 200 500 200 Clock fi Load Time tDH Clock Pulse Width Clock Rise/Fall Time DATA Setup Time DATA Hold Time Load fi Clock Time Load Pulse Width SEGn Rise/Fall Time Large Current Small Current Grid Frequency Oscillation Frequency CL = 20pF CL = 20pF CL = 82pF±5% tCL tLC tLW tr, tf tr, tf fGRID fOSC 1.3 100 150 307.2 250 512 400 400 350 716.8 ns ms ns kHz Hz ns ns ns ns ns ns

This device uses 10-bit dimming and 64-bit segment data. In order to transfer this data, the enable bit (M0) and mode bit (M1) should be set to an initial state. The data format is shown below. Figure 1. Data Transfer Timing M0 : This bit is an enable bit. M0 = "0" : Subsequent data is disabled; preceding data is held. M0 = "1" : The beginning of data transfer. The following data is clocked in sequentially. M1 : This bit is used to select the mode. M1 = "0" : Subsequent data is handled as the segment data. M1 = "1" : Subsequent data is handled as the dimming data. S1 : data for grid1 of SEG1. S2 : data for grid1 of SEG2.... S32 : data for grid1 of SEG32. S33 : data for grid2 of SEG1.... S64 : data for grid2 of SEG32. data coming next is handled as the enable bit.

  1. If the number of the data bits applied is greater (for example, 67 bits are applied

that they are applied, and thus S1, S2, and S3 are ignored.

  1. If the number of the data bits applied is smaller (for example, 62 bits are applied

DATA is shifted at the rising edge of the clock. segment data transfer is finished, the display is turned on. The relationship between this data transfer and the display is shown in Figure 2. off (the segment output is "L"). transfer and the display is shown in Figure 2. Figure 2. Relationship Between Data Transfer and Display

The duty cycle of grid output can be changed in 1/2048 step with respect to 10-bit dimming data. Table 1 shows the relationship between dimming data and duty ratio. Table 1. Dimming Data and Duty Ratio Note: Setting for address 3FF H is invalid. Duty ratios are programmable within the range of 0/2048 (0%) to 1015.5/2048 (49.6%).

¡ Semiconductor MSC1205 APPLICATION CIRCUIT 45 35 SEG1 SEG32 SEG2 DATA CLOCK LOAD GRID1 GRID2 MSC1205 CPU

40 OSC

V SS VDD 82pF 42 36 VFD SEG1-SEG32

¡ Semiconductor MSC1205 (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). DIP42-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.20 TYP.

¡ Semiconductor MSC1205 (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. QFP44-P-910-0.80-2K Mirror finish