MR27V6466F

MR27V6466F OKI | Alldatasheet

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This version: Jul. 2001 Previous version: Jun. 2001 MR27V6466F Preliminary 4,194,304-Word x 16-Bit or 2,097,152-Word x 32-Bit Synchronous One Time PROM GENERAL DESCRIPTION The MR27V6466F is a 64 Mbit One Time Programmable Synchronous Read Only Memory whose configuration can be electrically switched between 4,194,304 x 16 bit (word mode) and 2,097,152 x 32 bit (double word mode) by the state of the WORD pin. The MR27V6466F supports high speed synchronous read operation using a single 3.3 V power supply. FEATURES ON READ

3.3 V power supply

LVTTL compatible with multiplexed address Dual electrically switchable configuration 4M x 16 (word mode) / 2M x 32 (double word mode) All inputs are sampled at the rising edge of the system clock. High speed read operation

100 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles

66 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles

50 MHz : CAS Latency = 4, 5, 6 tRCD min: 1 clock cycles

Burst length (4, 8) Data scramble (sequential, interleave) DQM for data out masking No Precharge operation is required. No Refresh operation is required. No power on sequence is required. Mode register is automatically initialized to the default state after power on. “Row Active” or “Mode Register Set” command is applicable as the first command just after power on. Single Bank operation FEATURES ON PROGRAMMING

8.0 V programming power supply

Programming algorithm is compatible with conventional asynchronous OTP. MR27V6466F can be programmed with conventional EPROM programmers. Synchronous Burst read or Static Programming Operation is selected by the state of STO pin. High STO level enables full static programming. (Program, Program Verify, Asynchronous Read) Low STO level enables synchronous burst read. Exclusive 86-pin socket adapters are available from OKI to support programming requirements. The socket adapter is used on a 48-DIP socket on the programmer. The socket adapter for 64M synchronous OTP is distinguished from the socket adapter for 32M SOTP. The socket adapter is designed with the STO pin connected to VCC in order to program MR27V6466F as conventional OTP. EPROM programmer must have the algorithm for MR27V6466F on the exclusive socket adapter. *Device damage can occur if improper algorithm is used. Programming with address multiplexed input is also available. High speed programming 25 µs programming pulse per word allows high speed programming.

2 M x 32 or 4 M x 16

& Program Bias A12 Column Decoder Column Address Latch Address Buffer Data Output Latch Data Input Buffer Command Controller Mode Register Burst sequence Controller Data Output Selector CLK Buffer Data Output / Input Buffer & Data Output / Address Buffer Program Mode Controller CS RAS CAS MR WORD CKE CLK CE AMPX OE STO DQ16 to DQ22 DQ23 to DQ31 CAP0 to CAP8 DQ0 to DQ15

DC (Don’t Care) : Logical input level is ignored. However the pin is connected to the input buffer of OTP. TOP VIEW Programming in Static Operation (STO is high) Synchronous Read (STO is VSS or open) VCC DQ0 VCCQ DQ16 DQ1 VSSQ DQ17 DQ2 VCCQ DQ18 DQ3 VSSQ DQ19 MR VCC DQM NC CAS RAS CS WORD A12 A11 A10 NC VCC NC DQ4 VSSQ DQ20 DQ5 VCCQ DQ21 DQ6 VSSQ DQ22 DQ7 VCCQ DQ23 VCC VSS DQ31 VSSQ DQ15 DQ30 VCCQ DQ14 DQ29 VSSQ DQ13 DQ28 VCCQ DQ12 NC VSS DC DC DC CLK CKE DC VSS DC DQ27 VCCQ DQ11 DQ26 VSSQ DQ10 DQ25 VSSQ DQ9 DQ24 VCCQ DQ8 VSS VCC DQ0 VCCQ DC DQ1 VSSQ DC DQ2 VCCQ DC DQ3 VSSQ DC DC VCC DC NC CAS RAS DC WORD A12 A11 A10 NC VCC NC DQ4 VSSQ DC DQ5 VCCQ DC DQ6 VSSQ DC DQ7 VCCQ CAP8 VCC VSS CAP0 VSSQ DQ15 CAP1 VCCQ DQ14 CAP2 VSSQ DQ13 CAP3 VCCQ DQ12 NC VSS VPP CE OE DC DC AMPX VSS STO CAP4 VCCQ DQ11 CAP5 VSSQ DQ10 CAP6 VCCQ DQ9 CAP7 VSSQ DQ8 VSS

PIN FUNCTION FOR SYNCHRONOUS READ OPERATION (STO pin is low level or open) Pin Name Function

Description

Must be low for synchronous operation. Internal resistance (around 10k ohms) pulls the input level down to VSS when this pin is open. High level STO enables programming operation compatible with standard OTPs. CLK System Clock All inputs are sampled at the rising edge. CS Chip Select Enables command sampling by the CLK signal with a low level on the CS input. CKE Clock Enable Masks internal system clock to freeze the CLK operation of subsequent CLK cycle. CKE must be enabled for command sampling cycles. CLK is disabled for two types of operations. 1) Clock Suspend 2) Power Down A0 to A12 Address Row and column addresses are multiplexed on the same pins. Row address: RA0 to RA12 Column address: CA0 to CA7 (x32) /CA0 to CA8 (x16) LSB:CA0(Both x32 and x16) RAS Row Address Strobe CAS Column Address Strobe MR Mode Register Set Functionality depends on the combination. See the function table. DQ0 to DQ31 Data Output Data outputs are valid at the rising edge of CLK for read cycles. Except for read cycles DQn is high-Z state. DQM Data Output Masking Data outputs are masked after two cycles from when high level DQM is applied. WORD x32/x16 Organization Selection The WORD pin defines the organization of each read command to be x16 (word mode) or x32 (double word mode). High = x32 Low = x16 When WORD is low (x16,word mode) ,DQ16 to DQ31 are held on High-Z state. VCC Power Supply

3.3 V Power supply to DQ0-DQ31

Don't Care Logical input level is ignored.

PIN FUNCTION FOR PROGRAMMING OPERATION (STO pin is high level) Pin Name Function Must be set high for programming operation. Internal resistance (around 10 k ohms) pulls the input level down to VSS for open state condition to be low level for synchronous read operation. AMPX Address Multiplex When AMPX is low, the addresses are not multiplexed and all address bits must be supplied to A0 to A12 (Row Address) and CAP0 to CAP8 (Column Address) simultaneously. When AMPX is high, multiplexed address inputs are enabled on A0 to A12. A0 to A12 Address Row address input. RAS Row Address Strobe When AMPX is high, row address is latched at the rising egde of RAS. When AMPX is low, input is not used. CAS Column Address Atrobe When AMPX is high, column address is latched at the rising egde of CAS. When AMPX is low, input is not used. DQ0 to DQ15 Data Input/Output Input of data for programming and output for program verify and read data. WORD x32/x16 Organization Selection The WORD pin defines the organization to be x16 (word mode) or x32 (double word mode). High = x32 Low = x16 This pin must be set low for programming operation. CAP0 to CAP8 Address Input When WORD is low, High-Z state on CAP0 to CAP8 is held to be input pins. When AMPX is low, column address input. When AMPX is high, input is not used. OE Output Enable Control signal input for programming. OE of conventional OTPs. CE Chip Enable Control signal input for programming. Function for programming is associated with conventional OTPs. VCC/VSS Power Supply/Ground Power and ground for the input buffers and the core logic. VCCQ/VSSQ Data Output Power/Ground Power and ground for output. Vpp Program Power Supply High voltage program power is supplied through VPP pin. When VPP is higher than a predetermined voltage level between VCC + 0.5 V and VCC + 2 V, pin function alters to high VPP mode. To keep stable static read operation VPP pin must be kept lower than VCC + 0.5 V. The persons who design socket adapter or make programming algorithm on the condition of omitting socket adapter provided with OKI study this table. Other persons can ignore this table. The functionality of programming must be checked with the specification of socket adapter that will be supplied by OKI. MR27V6466F on the socket adapter is the same programming functionality as conventional OTPs.

FUNCTION COMMAND TABLE FOR SYNCHRONOUS READ Command Name Function CKEN-1 CKEN CS RAS CAS MR DQM Add. WORD STO Note Mode Register Set Mode Register Set H X L L L L X Code X L Row Active Row Address Latch H X L L H H X RA X L Read Word (x16) Column Address Latch Trigger Burst Read H X L H L H X CA L L Read Double Word (x32) Column Address Latch Trigger Burst Read H X L H L H X CA H L Burst Stop Burst Stop H X L H H L X X X L Precharge Burst Stop H X L L H L X X X L Entry H L H X X X X X X L Clock Suspend (on Read) Exit L H X X X X X X X L Entry H L H X X X X X X L Power Down (on Active Standby) Exit L H X X X X X X X L Read Output Output Enable H X X X X X L X X L Mask Output High-Z Output H X X X X X H X X L Write on SDRAM H X L H L L X X X L Illegal on SDRAM H H L L L H X X X L H X H X X X X X X L No Operation H X L H H H X X X L ( H = Logical high, L = Logical low, X = Don't Care, L of STO includes pin open due to internal pull down resistor) (CKEN expresses the logical level at the simultaneous cycle with a command. ) Notes: Refer to "Mode Register Field Table" for Address Codes, and Mode Transition Chart for operational state. After power on, any command can be sampled at any cycle in Active Standby state. After "Mode Register Set" command is sampled, no new command can be accepted for 3 CLK cycles. The CS input must be kept high for the 3 CLK cycles to prevent unexpected sampling of a command. The "Row Active" command is effective till new "Row Active" command is implemented. The WORD input is sampled simultaneously with "Read" command to select data width. A Double Word Burst (x32) or a Word Burst (x16) is selected by the WORD input for each "Read" command. On condition of constant voltage level on WORD pin, the organization is fixed to either x16 or x32. "Read" command ends it's implementation by itself at the finishing cycle of the burst read. Since OTP technology uses static sense amplifiers, the "Precharge" command is not required. However, due to customer request for the similarity of logical input code with SDRAM command, the name of "Precharge" is adopted. The function of "Precharge" command and "Burst Stop" command is only to stop the burst read cycles delayed by CAS Latency. Sampled low level CKE disables CLK buffer to suspend internal clock signals at the next rising edge of CLK. Sampled high level CKE enables internal clock at the next rising edge of CLK. Low level CKE sampled in the period from the simultaneous cycle with a "Read" command till the end of the burst read cycle is distinguished with internal command controller from the low level CKE sampled in Active Standby state, then power is consumed because of data sensing and burst read operation. Low level CKE sampled in Active Standby state cuts power dissipation to be in Power Down state. High level CKE sampled in Power Down state enables internal CKE to be in Active Standby state with preserved row address.

FUNCTION STATE TABLE FOR SYNCHRONOUS READ Current State CKE CS RAS CAS MR Add. Command Action at next clock cycle or cycles State after the completion of the command Note H L L L L Code Mode Register Set Mode Register Set Active Standby H L L H H RA Row Active Row Address Latch Active Standby H L H L H CA Read Column Address Latch Trigger Burst Read Active Standby after Burst Read L H X X X X Power Down Entry Power Down Power Down H L H H L X Burst Stop NOP Active Standby H L L H L X Precharge NOP Active Standby H L L L H X NOP NOP Active Standby H L H L L X NOP NOP Active Standby H L H H H X NOP NOP Active Standby Active Standby H H X X X X NOP NOP Active Standby H L L L L Code Mode Register Set Illegal H L L H H RA Row Active Row Address Latch Active Standby H L H L H CA Read Column Address Latch Trigger Burst Read Active Standby after Burst Read L X X X X X Clock Suspend Clock Suspend Entry Clock Suspend H L H H L X Burst Stop Stop the Burst Read Cycle delayed by CAS Latency Active Standby H L L H L X Precharge Stop the Burst Read Cycle delayed by CAS Latency Active Standby H L L L H X NOP NOP Read H L H L L X NOP NOP Read H L H H H X NOP NOP Read Read H H X X X X NOP NOP Read H X X X X X Exit Power Down Exit Power Down Active Standby Power Down L X X X X X Power Down Power Down Power Down H X X X X X Exit Clock Suspend Exit Clock Suspend Read Clock Suspend L X X X X X Clock Suspend Clock Suspend Clock Suspend ( H = Logical high, L = Logical low, X = Don't Care) Notes: The latched row address is preserved during any state except another “Row Active” command. Low level CKE sampled in Active Standby state disables internal clock and cuts power dissipation to be in Power Down state. High level CKE sampled in Power Down state enables internal clock to be in Active Standby state. To preserve previous “Read” command, the latest “Row Active” command must be implemented at CL- 1 clock cycle or later after the previous “Read” command. 4. To preserve previous “Read” command, the latest “Read” command must be implemented at CL-1 clock cycle or later after the previous “Read” command. 5. Sampled low level CKE in the period of Burst Read disables CLK buffer to suspend internal clock signals at the next rising edge of CLK. Sampled high level CKE in the Clock Suspend enables internal clock at the next rising edge of CLK.

Note: A7 and A8 must be low during Mode Register Set cycle. During power on, mode register is initialized to the default state when VCC reaches a specific voltage (less than 3.0 V). The default state of Mode Register is as shown below. CAS Latency = 5 Burst Type = Sequential Burst Length = 4 BURST SEQUENCE (BURST LENGTH = 4) Initial address Sequential Interleave BURST SEQUENCE (BURST LENGTH = 8) Initial address Sequential Interleave

(1) WORD = “H”: x32 Organization Pin Name A10 A11 A12 Row Address RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 Column Address CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 X X X X X ( X = Don’t Care) (2) WORD = “L”: x16 Organization Pin Name A10 A11 A12 Row Address RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 Column Address CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 X X X X ( X = Don’t Care) (3) Programming Address displayed on programmer: x16 Ad0 Ad1 Ad2 Ad3 Ad4 Ad5 Ad6 Ad7 Ad8 Ad9 Ad10 Ad11 Ad12 Device Address: x16 STO = “H”, AMPX = “L” CAP0 CAP1 CAP2 CAP3 CAP4 CAP5 CAP6 CAP7 CAP8 Address (STO = “L”) WORD = “L”: x16 CA0 Note2 CA1 Note3 CA2 CA3 CA4 CA5 CA6 CA7 CA8 RA0 RA1 RA2 RA3 Address (STO = “L”) WORD = “H”: x32 Note1 CA0 Note4 CA1 Note5 CA2 CA3 CA4 CA5 CA6 CA7 RA0 RA1 RA2 RA3 Address displayed on programmer: x16 Ad13 Ad14 Ad15 Ad16 Ad17 Ad18 Ad19 Ad20 Ad21 Device Address: x16 STO = “H”, AMPX = “L” A10 A11 A12 Address (STO = “L”) WORD = “L”: x16 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 Address (STO = “L”) WORD = “H”: x32 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 Users of MR27V6466F are recommended to study the relationship between "Address displayed on programmer" and "Address (STO = "L")" ignoring "Device Address: x16, STO = "H"". The order of data on Synchronous Read operation (STO="L") is checked on this table. "Device Address : x16, STO = "H"" will be utilized to design socket adapter on programmer or to check boards designed to mount blank OTP and program OTP on board. OKI will supply a socket adapter to program MR27V6466F as conventional x16 standard OTP. The users and the venders of programmer who use the socket adapter can ignore "Device Address: x16, STO = "H"". The persons who use 32Mbit SOTP and 64Mbit SOTP must be careful to distinguish the socket adapters for 64Mbit from one for 32Mbit. The difference is caused from the additional assignment of column address and 1 bit shift of row address on 64Mbit SOTP Note 1. A0 in programmer distinguishes upper word (x16) or lower word (x16) of Double word (x32). On word (x16) organization the address of device corresponds to the address of programmer. On double word (x32) organization the address numeral code of device is half of that in programmer, and output on DQ0 to DQ15 is lower word (A0 = "0") and output on DQ16 to DQ31 is upper word (A0 = "1"). 2. CA1 is MSB of burst read on condition of WORD = "L" and BL = 4. 3. CA2 is MSB of burst read on condition of WORD = "L" and BL = 8. 4. CA1 is MSB of burst read on condition of WORD = "H" and BL = 4. 5. CA2 is MSB of burst read on condition of WORD = "H" and BL = 8.

Clock (CLK) The clock input enables MR27V6466F to sample all the inputs, to control internal circuitry, and to turn on output drivers. All timings are referred to the rising edge of the clock. All inputs with high level CKE and low level CS should be valid at the rising edge of CLK for proper functionality. Clock Enable (CKE) The clock enable (CKE) turns on or switches off the admission of the clock input into the internal clock signal lines. All internal circuits are controlled by the internal clock signal to implement each command. High level CKE sampled at CKEN-1 clock cycle enables the admission of the rising edge of clock input into internal clock line at CKEN cycle. Low level CKE sampled at CKE N-1 cycle suspends the rising edge of CLK at CKEN cycle. The suspension of internal clock signal in all state ignores new input except CKE, and holds internal state and output state. Low level CKE in Active Standby state, defined as Power Down state, cuts power dissipation. In Power Down state, the contents of mode resister and Row Address are preserved. After recovering high level CKE to exit from Power Down state, MR27V6466F is in Active Standby state. Low level CKE just after the sampling of "Read" command till the completion of burst read, defined as Clock Suspend, makes read operation go on with power dissipation. Any command operation does not interrupted by arbitrary low level CKE. Sampling command with low level CKE preceded with high level CKE is illegal. Power On Apply power and start clock considering following issues. During power on, Mode Register is initialized into the default state. (default state: CAS latency = 5, Burst Type = Sequential, Burst length = 4) After power on, MR27V6466F is in Active Standby state and ready for "Mode Register set" command or "Row Active" command. MR27V6466F requires neither command nor waiting time as power on sequence after starting CLK input in order to start "Row Active" command to read data. It is recommended in order to utilize default state of Mode Register that MR and CKE inputs are maintained to be pulled up during power on till the implementation of the first "Row Active" command. After above power on, "Row Active" command and "Read" command can be started immediately on default Mode Register state. It is recommended that DQM input is maintained to be pulled up to prevent unexpected operation of output buffers. Organization Control The organization of data output (DQ0~DQ31) depends on the logical level on WORD at the input timing of each "Read" command. High level sampling of WORD derives double word mode (x32) output and low level sampling of WORD derives word mode (x16) output. Constant WORD level input brings consistent organization. MODE Register Mode register stores the operating mode of MR27V6466F. Operating modes are consisted with CAS latency, Burst Type and Burst Length. Registration of RAS latency is not required, because RAS to CAS delay (tRCD) is requested independently of system clock. When the contents of Mode register are required to be changed for the next operation, "Mode Register Set" command can be sampled at any cycle in Active Standby state. After "Mode Register Set" command is sampled, CS must be fixed to logical high level to prevent sampling of new command input during succeeding three clock cycles. Refer to Mode Resister Field Table for the relation between Operation modes and input pin assignment

After sampling "Read" command, MR27V6466F starts actual data read operation with sense amplifiers, and transmits the data from sense amplifiers to data out buffers to start burst read. This flow of sequential functionality takes time as clock cycles defined as CAS latency (CL). CAS latency can be set in Mode Register between from four cycles to six cycles. In this sequence (from sampling "Read" command to start of driving data bus), sense amplifiers consume maximum current flow. The detailed sequence is as shown below. Fix the column address of memory matrix driver. Row address is already fixed with "Row Active" command. (at 1st cycle) Read the data of selected memory cells with sense amplifiers. Deliver the data detected with sense amplifiers to the register for data output latch. Couple selectively the section of the register storing each (double) word to output buffers. Enable the output buffers to drive data bus (at CL-1 cycle). Data the output on data bus can be sampled at the rising edge of system clock at CL cycle. New "Row Active" command or new "Read" command can be sampled to perform gapless burst read at CL-1 clock cycle of the last "Read" command. New command preceeding CL-1 cycle interrupts sense amplifiers to read the data at the selected memory cells of the last "Read" command. Interrupted "Read" command perishes or outputs invalid data before the starting of the data burst of new "Read" command. Refer to the timing chart of "Burst Read/Interrupt I" and "Burst Read/Interrupt II". Burst Read Data outputs are consecutive during the cycle number defined as Burst Length (BL). The latest burst read is completed unless any interruption such as "Precharge" command stops the sequential data output. Burst Length is set in Mode Register as either four or eight. After sampling of "Read" command, the first output can be read at the cycle delayed by CAS latency. Burst Type is also stored in Mode register as either sequential or interleave. The output buffers go into a high impedance state after burst read sequence is finished, unless a new "Read" command has been sampled to perform gapless read or preemptive read. Burst read can be interrupted by "Burst Stop" command or "Precharge" command at the cycle delayed by CAS latency from the command. On condition that reading data with sense amplifiers of preceding "Read" command is not interrupted by new "Read" command or "Row active" command, burst read of preceding "Read" command is continued regularly until the burst data sequence of the new "Read" command starts. The new (latest) burst data sequence always starts regularly. DQM Input level on DQM is sampled at the rising edge of system clock to mask data at two cycles later. The output of masked data is in a high-Z state.

Precharge* Entry Exit * All operation of “Precharge” command is to stop burst read. Note: : state can be kept for any duration : passing command CKE = L CKE = H Exit Entry

Min. Max. Unit Voltage on VCC Relative to VSS VCC, VCCQ –0.5 V Voltage on Any Pin Relative to VSS VIN, VOUT, DC –0.5 VCC + 0.5 V Voltage on VPP Relative to VSS VPP –0.5 V Operating Temperature TA Storage Temperature TSTG –55 125 Short Circuit Current IOS mA Power Dissipation PD 1.0 W RECOMMENDED OPERATION CONDITION FOR SYNCRONOUS READ Parameter Symbol Min. Typ. Max. Unit Note Power Supply Voltage VCC, VCCQ 3.0 3.3 3.6 V Voltage Level on DC Pin –0.5 VCC + 0.3 V Input High Voltage VIH 2.0 VCC + 0.3 V Input Low Voltage VIL –0.3 0.8 V Operating Temperature TA Power Dissipation1 (Airflow over 1 m/s) PD1 0.6 W Power Dissipation2 (No airflow) PD2 0.4 W Power Dissipation3 (Airflow over 1 m/s) PD3 0.9 W Power Dissipation4 (No airflow) PD4 0.6 W Notes: 1. VIH max can be VCC + 1.5V for the pulse width shorter than 3 ns. Pulse width is measured at 50% of pulse peak level. 2. VIL min can be –1.5 V for the pulse width shorter than 3 ns. Pulse width is measured at 50% of pulse peak level. 3. The clock frequency is under 83MHz. CAPACITANCE Parameter Symbol Min. Max. Unit Input Capacitance CIN pF Output Capacitance COUT pF

DC CHARACTERISTICS FOR SYNCHRONOUS READ Parameter Symbol Min. Max. Unit Test Condition ICCS1 mA CKE = 0.8V Power Down Current ICCS2 150 µA CKE = 0 V tCC = 10 ns Active Standby Current ICC1 120 mA CKE = 2.4V CS = 2.4V tCC = 10 ns Gapless Burst Read Current ICC2 250 mA CKE = 2.4V tCC = 10 ns, DQM = H, CL = 5, BL = 4 Input Leak Current IIL –10 µA 0V > VIN > VCC + 0.3 V Output Leak Current IOL –10 µA 0V > VIN > VCC Input High Voltage VIH 2.0 VCC+0.3V V Note 1 Input Low Voltage VIL –0.3 0.8 V Note 2 Voltage Level on DC Pin –0.5 VCC+0.3V V Output High Voltage Level VOH 2.4 V IOH = –4 mA Output Low Voltage Level VOL 0.4 V IOL = 4 mA ( Voltage levels are referred to VSS ) Notes: 1. VIH max can be VCC + 1.5V for the pulse width shorter than 3 ns. Pulse width is measured at 50% of pulse peak level. 2. VIL min can be –1.5 V for the pulse width shorter than 3 ns. Pulse width is measured at 50% of pulse peak level.

AC CHARACTERISTICS FOR SYNCHRONOUS READ (1/2) Parameter Symbol Min. Max. Unit Notes CLK Cycle Time tCC ns Data to Valid Output Delay tAC ns Data Output Hold Time tOH 2.3 ns CLK High Pulse Width tCH ns CLK Low Pulse Width tCL ns Input Setup Time tSI ns Input Hold Time tHI ns CLK to Output in Low-Z tOLZ ns CLK to Output in High-Z tOHZ ns Input Level Transition Time tT 0.1 ns 1CLK Cycle “Row Active” to “Read” Delay Time tRCD 2CLK Cycle CL = 4 tCRD 3CLK Cycle 1,2 CL = 5 tCRD 4CLK Cycle BL = 4 CL = 6 tCRD 5CLK Cycle CL = 4 tCRD 3CLK Cycle 1,2 CL = 5 tCRD 4CLK Cycle “Read” to “Row Active” Delay ( Words of preceding “Read” command can be read ) < Random Access > BL = 8 CL = 6 tCRD 5CLK Cycle CL = 4 tCCD 3CLK Cycle 1,2 CL = 5 tCCD 4CLK Cycle BL = 4 CL = 6 tCCD 5CLK Cycle CL = 4 tCCD 3CLK Cycle 1,2 CL = 5 tCCD 4CLK Cycle “Read” to “Read” Delay ( Words of preceding “Read” command can be read ) < Sequential Access > BL = 8 CL = 6 tCCD 5CLK Cycle CL = 4 tRC 3CLK + tRCD Cycle 1,2 CL = 5 tRC 4CLK + tRCD Cycle BL = 4 CL = 6 tRC 5CLK + tRCD Cycle CL = 4 tRC 3CLK + tRCD Cycle 1,2 CL = 5 tRC 4CLK + tRCD Cycle “Row Active” Cycle Time ( Words of preceding “Read” command can be read ) < Random Access > BL = 8 CL = 6 tRC 5CLK + tRCD Cycle CL = 4 tCCD 4CLK Cycle 1,2 BL = 4 CL = 5 tCCD 4CLK Cycle CL = 4 tCCD 8CLK Cycle 1,2 CL = 5 tCCD 8CLK Cycle “Read” to “Read” Delay ( Consecutive Column Read ) < Sequential Access > BL = 8 CL = 6 tCCD 8CLK Cycle “Read” to “Burst Stop” Delay 1CLK Cycle “Read” to “Precharge” Delay 1CLK Cycle Power down Exit Setup Time tPDE tSI + 1CLK Cycle Power down Exit to “Read” Delay tPDR tSI + 3CLK Cycle Notes: 1. The shortage of clock cycles interrupts the data sensing of preceding "Read" command. The shortage of cycle time for preceding command is detected by internal command controller to cease the preceding command operation. The latest "Row Active" or "Read" command is completed. When a legal tCCD is shorter than BL, burst read is terminated with another burst read. 2. Up to 50 MHz

AC CHARACTERISTICS FOR SYNCHRONOUS READ (2/2) Parameter Symbol Value Unit Notes Clock Disable Time from CKE tCKE 1CLK Cycle Clock Enable Time from CKE tCKE 1CLK Cycle Output High Impedance from DQM tDQM 2CLK Cycle Recovery from DQM tDQM 2CLK Cycle Output High Impedance from “Burst Stop” tBOH CL Cycle Output High Impedance from “Precharge” tPOH CL Cycle “Row Active” Input from “Mode Register Set” tMRD Cycle AC TEST CONDITIONS Parameter Values Notes Input Signal Levels VIH/VIL = 2.4 V/0.4 V Timing Reference Level of Input/Output Signals 1.4 V Transition Time of Input Signals tr/tf = 1 ns/1 ns Output Load LVTTL Notes: The transition time of input signals is measured between 0.8 V and 2.0 V. If tr or tf is longer than 1ns, the "Timing Reference Level of Input/Output Signals" is changed to VIL or VIH/0.8 V or 2.0 V respectively. Output Load Output 1.4 V 50Ω 50 pF ZO = 50Ω

Read Cycle I: Random Access @ CAS Latency = 5, Burst length = 4 Ra CLK CKE tCC tCL High CS RAS CAS ADDR tSI tHI tRCD DQ MR Don’t Care Row Active Read tRC Row Active Read tOH Ca Rb Cb tCH tAC tOHZ

Read Cycle II: Random Access with Gapless Burst @ CAS Latency = 4, Burst length = 4 CLK CKE tCC High CS RAS CAS ADDR tSI DQ MR tOH Don’t Care Row Active Read tRC Row Active Read Row Active Read Ra Ca Rb Cb Rc Cc tRCD tHI tCL tCH tAC

Read Cycle III: Consecutive Column Read @ CAS Latency = 5, Burst length = 4 CLK CKE tCC High CS RAS CAS ADDR tRCD tCCD DQ MR Don’t Care Row Active Read Read tOH Cb Ca Ra tCH tCL tHI tSI tAC tOHZ

“Burst Stop” command & “Precharge” command @ CAS Latency = 5 CLK CKE tCC tCL High CS RAS CAS ADDR DQ MR Don’t Care Row Active Read Burst Stop Row Active Read Precharge Ra Ca Rb Cb tOH tRCD tPOH tBOH tCH tOHZ tAC tSI tHI

Clock Suspend @ CAS Latency = 5, Burst length = 4 Note At cycle numbers 9, 12 and 13, the rising edge of internal clock is omitted because of low level CKE at cycles 8, 11 and 12. Clock suspend is defined with the low level CKE sampled in the period of read operation. CLK CKE tCC CS RAS CAS ADDR tSI tHI tCCD DQ MR Don’t Care Row Active Read Read Clock Suspend Entry Exit Exit Clock Suspend Entry Read “b” operation ( Note1 ) Cb Ca Ra tCH tCL tCKE tCKE tCKE tCKE tRCD Read “a” operation (Note2)

Power Down @ CAS Latency = 4, Burst length = 4 Note Minimum current consumption is expected in Power Down state. Low level CKE sampled only in Active Standby state is defined as Power Down "Entry" command and it cuts current consumption into a minimum level. After Power Down "Exit" the contents of Mode Register and row address are preserved. During Power Down state no command can be sampled. Cb Row Active CLK CKE tCC CS RAS CAS ADDR DQ MR Read Power Down Entry Power Down Exit Power Down (Note1) Read Operation Ca tCH tCL tSI tPDE Read tPDR

Mode Register Set @ CAS Latency = 4, Burst length = 4 CLK CKE tCC CS RAS CAS ADDR DQ MR Don’t Care Power Down Entry Read Row Active Power Down Exit Mode Register Set Power Down tMRD High - Z Cb Rb key tCH tCL

DQM Operation @ CAS Latency = 4, Burst length = 8 CLK CMD CKE DQM DQ tDQM tDQM Q6 Q7 High - Z RD tCKE tCKE

Burst Read/Interrupt I @ CAS Latency = 4, Burst length = 8 Burst Read/Interrupt II @ CAS Latency = 4, Burst length = 4 CLK CMD ADDR DQ High-Z tCCD RD<a> is interrupted by RD<b> RD<a> command perishes. RD<d> sets up Qc2 as the final Qcn. The output state of interrupted command preceded by data read cycle is invalid. RD<d> is interrupted by RD<e>. Invalid state: “H”, ”L” or High-Z Qe3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Invalid State Qe0 Qe1 Qe2 RD RD RD RD RD a b c d e CLK CMD ADDR DQ High-Z tRCD RD<c> is interrupted by ACT<A> tRC tCRD Invalid State RD c ACT A RD a ACT B RD b Qb3 Qb0 Qb1 Qb2 Qa3 Qa0 Qa1 Qa2

Preemptive Burst Read I @ CAS Latency = 4, Burst length = 8 Preemptive Burst Read II @ CAS Latency = 4, Burst length = 8 CLK CMD ADDR DQ RD a RD b RD c RD d Qd0 Qb3 Qa0 Qa1 Qa2 Qb0 Qb1 Qb2 Qd2 Qc0 Qc1 Qc2 Qc3 Qc4 Qd1 CLK CMD ADDR DQ High-Z Qb7 Qb1 Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb2 Qb3 Qb4 Qb5 Qb6 ACT A RD a ACT A RD b High-Z

RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS FOR PROGRAMMING (STO is High level) Parameter Symbol Min. Typ. Max. Unit Condition Notes VPP1 7.75 8.0 8.25 V Program Mode VPP Supply Voltage VPP2 –0.3 VCC VCC+0.5 V Read Mode VCC1 3.9 4.0 4.1 V Program Mode VCC2 4.5 4.6 4.7 V Read Mode VCC Supply Voltage VCC3 2.75 2.8 2.85 V Read Mode IPP1 mA VPP = 8.25 V, VCC = 4.1 V VPP Current IPP2 100 µA VPP = VCC = 4.7 V ICCP1 150 mA VPP = 8.25 V, VCC = 4.1 V VCC Current ICCP2 200 mA VPP = VCC = 4.6 V Input Leak Current IIL –10 µA Output Leak Current IOL –10 µA Output High Voltage Level VOH 2.4 V IOH =–400 µA Output Low Voltage Level VOL 0.45 V IOL = 2.1 mA Input High Voltage VIH 3.2 VCC+0.7 V VCC = 2.8/4.6 V Input Low Voltage VIL –0.3 0.45 V VCC = 2.8/4.6 V Voltage Level on DC pin –0.3 VCC+0.5 V OE Input Distinctive High Voltage For Contact Check VH 6.6 6.7 6.8 V VCC = 3.0 V Operating Temperature Ta (Voltage levels are referred to VSS) Notes: 1. Program represents the modes below. Program, Program Verify, Program Inhibit 2. Read represents the modes below. Read, Output Disable, Standby

FUNCTION TABLE FOR PROGRAMMING Function VCC VPP CE OE WORD DQ0~ DQ15 CAP0~ CAP8 Add. RAS CAS AMPX STO Notes Program 4.0 V 8.0 V L H L DIN A0 to A8 A9 to A21 X Open H Program Inhibit 4.0 V 8.0 V H H L HZ A0 to A8 A9 to A21 X Open H Program Verify 4.0 V 8.0 V H L L DOUT A0 to A8 A9 to A21 X Open H Read 2.8/ 4.6 V 2.8/ 4.6V L L L DOUT A0 to A8 A9 to A21 X Open H Output Disable 2.8/ 4.6 V 2.8/ 4.6V L H L HZ A0 to A8 A9 to A21 X Open H Standby 2.8/ 4.6 V 2.8/ 4.6V H X L HZ A0 to A8 A9 to A21 X Open H Contact Check 3.0 V 3.0 V L 6.7 V L AAAA 0AA 16AA X Open H Contact Check 3.0 V 3.0 V L 6.7 V L 5555 155 0955 X Open H Full Static Contact Check 3.0 V 3.0 V L 6.7 V L 5555 155 0955 X Open H ADDRESS MULTIPLEX Function VCC VPP CE OE WORD DQ0~ DQ15 CAP0~ CAP8 Add. RAS CAS AMPX STO Notes Program 4.0 V 8.0 V L H L DIN H H H Program Inhibit 4.0 V 8.0 V H H L HZ RA/CA H H Program Verify 4.0 V 8.0 V H L L DOUT H H H Read 2.8/ 4.6V 2.8/ 4.6V L L L DOUT RA/CA H H Output Disable 2.8/ 4.6V 2.8/ 4.6V L H L HZ X X H H Standby 2.8/ 4.6V 2.8/ 4.6V H X L HZ X X H H Contact Check Address multiplex Contact Check ( H = Logical high, L = Logical low, X = Don't Care in the range of logical level) Notes: 1. Dual procedures to check complementary output codes on the indicated complementary address inputs assure every address, DQ, and OE pin connection. When address input code is incorrect, output code is "FFFF".

Synchronous read is far different from anyone of conventional nonvolatile memories. STO input level switches operation mode either synchronous read or conventional EPROM/OTP type programming. The word "Programming" contains actual programming (inject electrons into floating gates of memory cells), program verify (verify data on actual programming bias), and read on programmer. High level STO assures full compatible programming operation with conventional EPROM/OTP. Low level STO assures high speed synchronous read. "Full static programming" is recommended for loose devices. Program MR27V6466F is programmed with 25 microsecond pulse width on 4.0 V VCC and 8.0 V VPP. OKI recommends consecutive programming, because of the similarity of device sorting process. Almost all words can be programmed sufficiently with one pulse. Programmers are recommended to be equipped with large current capacity of VPP and VCC supplying source and responsive capacitance (around 0.1 µF) on each socket to stabilize VPP and VCC voltage level, since switching speed of transistors produced with advanced wafer process technology is very fast and high voltage immunity of those is decreasing. Excessive overshooting of VPP voltage may destroy device permanently. Excessive overshooting of VCC voltage may cause misprogramming or disturbance. Excessive undershooting of VPP or VCC level may cause insufficient electron injection into floating gate. Additional programming increases programming time. Program Inhibit When VPP is 8.0 V, address must be changed only in "Program Inhibit" mode. Program Verify This operation mode is utilized to check that each word is programmed sufficiently. It is recommended to take time more than some seconds between actual programming and "Program Verify" ("Read") for each word, because just after the actual programming (injection of electron into floating gate) of each word, pretended excessive electrons are attached around floating gate to show false sufficiency of programming. Programming flow is selected to separate "Program" and "Program Verify" to take enough time. Contact Check When programmed OTP lot contains failed devices at a rate of more than 0.1%, some of or almost all failed devices are caused by misconnection with the sockets on the programmer. The possibility of misconnection is increased with surface mount devices such as SOP or TSOP. OKI will supply socket adapters exclusively applicable to MR27V6466F, but connections of all pins can not be assured with these socket adapters. Following contact check sequence before actual programming is recommended. Supply VCC with 3.0 V power source. Bias logical low level on CE. Supply 6.7 V on OE to enable contact check mode. Apply two address codes and check each output respectively. If irregular address code is applied, then output is FFFF. <Connection of Address, DOUT, VCC, OE, and STO pins are checked> CE must be checked with a method suitable for the programmer. VPP can be checked with current flow (more than 100 µA) in Program Inhibit mode. AMPX and WORD pins is open in the socket adapter, since these pins are pulled down to VSS when STO is high.

AC CHARACTERISTICS FOR PROGRAMMING (STO is High Level) Parameter Symbol Min. Typ. Max. Unit Condition Notes VPP Setup Time tVS µs VPP = 8.0 V, VCC = 4.0 V Address Setup Time tAS 100 ns VPP = 8.0 V, VCC = 4.0 V Data Setup Time tDS 100 ns VPP = 8.0 V, VCC = 4.0 V Address Hold Time tAH µs VPP = 8.0 V, VCC = 4.0 V Data Hold Time tDH 100 ns VPP = 8.0 V, VCC = 4.0 V Program Pulse Width tPW µs VPP = 8.0 V, VCC = 4.0 V OE Setup Time tOES µs VPP = 8.0 V, VCC = 4.0 V Data Valid from OE tOE 100 ns VPP = 8.0 V, VCC = 4.0 V OE High to Output Float Delay tOHZ 100 ns VPP = 8.0 V, VCC = 4.0 V Address Setup Time(RAS/CAS) tASR tASC ns VPP = 8.0 V, VCC = 4.0 V RAS/CAS Pulse Width tRAS tCAS ns VPP = 8.0 V, VCC = 4.0 V Address Hold Time(RAS/CAS) tAHR tAHC ns VPP = 8.0 V, VCC = 4.0 V RAS Precharge Time tRP µs VPP = 8.0 V, VCC = 4.0 V RAS to CAS Delay tRCD ns VPP = 8.0 V, VCC = 4.0 V Address to CE Delay tACD 100 ns VPP = 8.0 V, VCC = 4.0 V AC CHARACTERISTICS FOR VERIFY AND READ (STO is High Level) Parameter Symbol Min. Typ. Max. Unit Condition Notes Address Access Time tACC 100 ns VPP = VCC = 2.8/4.6 V RAS Access Time tACC 100 ns VPP = VCC = 2.8/4.6 V CAS Access Time tACC 100 ns VPP = VCC = 2.8/4.6 V CE Access Time tCE 100 ns VPP = VCC = 2.8/4.6 V OE Access Time tOE ns VPP = VCC = 2.8/4.6 V CE High to Output Float Delay tCHZ ns VPP = VCC = 2.8/4.6 V OE High to Output Float Delay tOHZ ns VPP = VCC = 2.8/4.6 V Address Hold from OE high tAHO ns VPP = VCC = 2.8/4.6 V Address Setup Time(RAS/CAS) tASR tASC ns VPP = VCC = 2.8/4.6 V RAS/CAS Pulse Width tRAS tCAS ns VPP = VCC = 2.8/4.6 V Address Hold Time(RAS/CAS) tAHR tAHC ns VPP = VCC = 2.8/4.6 V RAS to CAS Delay tRCD ns VPP = VCC = 2.8/4.6 V Address to CE Delay tACD 100 ns VPP = VCC = 2.8/4.6 V

Consecutive Programming Waveforms (VPP = 8.0 V, AMPX = L) Consecutive Program Verify Cycle (VPP = 8.0 V, AMPX = L) Notes: 1. Falling edge of OE must be preceded with data stabilizing time of more than tACC max, because output of invalid state can cause unstable system operation. Output buffer of MR27V6466F is designed to drive 100 pF load in 5ns. CAP0 to CAP8 A0 to A12 CE OE DQ0 to DQ15 VPP tVS tDS tAS tPW tDH tAH DIN DIN High CAP0 to CAP8 A0 to A12 CE OE DQ0 to DQ15 tACC tOHZ tAHO High tOE Note1 DOUT DOUT

Program and Program Verify Cycle Waveforms (AMPX = L) Read Cycle (AMPX = L) CAP0 to CAP8 A0 to A12 CE OE DQ0 to DQ15 VPP 8.0V tOHZ tAS tPW tDH tOES DIN DOUT tDS tOE tOHZ CAP0 to CAP8 A0 to A12 CE OE DQ0 to DQ15 tACC tOE tCE DOUT DOUT tOHZ tCHZ

Consecutive Programming Waveforms (VPP = 8.0 V, AMPX = H, WORD = L) CE OE DQ0 to DQ15 VPP tVS tDS tPW tDH DIN High A0 to A12 RAS CAS tASR tAHR tRAS tASC tAHC tCAS Row address Column address tRCD tACD tRP RA

Consecutive Program Verify Cycle (VPP = 8.0 V, AMPX = H, WORD = L) Notes: 1. Falling edge of OE must be preceded with data stabilizing time of more than tACC max, because output of invalid state can cause unstable system operation. Output buffer of MR27V6466F is designed to drive 100 pF load in 5ns. CE OE DQ0 to DQ15 High A0 to A12 RAS CAS tASR tAHR tRAS tASC tAHC tCAS Row address Column address tRCD DOUT tACC tOE tOHZ Note1

Program and Program Verify Cycle Waveforms (AMPX = H, WORD = L) CE OE DQ0 to DQ15 VPP tDS tPW tDH DIN A0 to A12 RAS CAS tASR tAHR tRAS tASC tAHC tCAS Row address Column address tRCD tACD tOES DOUT tOE tOHZ 8.0V tRP RA

Read Cycle (AMPX = H, WORD = L) CE OE DQ0 to DQ15 A0 to A12 RAS CAS tASR tAHR tRAS tASC tAHC tCAS Row address Column address tRCD DOUT tCE tOE tOHZ CE OE DQ0 to DQ15 A0 to A12 RAS CAS tASR tAHR tRAS tASC tAHC tCAS Row address Column address tRCD DOUT tACC tOHZ tCHZ

VPP = VCC = 3.3 V CONTACT CHECK ADDRESS = FIRST LOCATION VCC = 4.0 V VPP = 8.0 V PROGRAM ONE 25 µs PULSE LAST ADDRESS YES NO INCREMENT ADDRESS X = 0 VERFY ONE WORD PASS NG X = X + 1 LAST ADDRESS YES NO INCREMENT ADDRESS VPP = VCC = 2.8 V X = 2 NO YES READ WORD NG DEVICE PASSED DEVICE FAILED PROGRAM ONE 25 µs PULSE VPP = VCC = 4.6 V READ WORD NG PASS

Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). TSOP(2)86-P-400-0.50-K Mirror finish Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating (≥5µm) Package weight (g) 0.53 TYP. Rev. No./Last Revised 1/Jul. 14, 1998 (Unit: mm)

The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.