MSM9811

MSM9811 OKI | Alldatasheet

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Issue Date: Sep. 1, 2004 MSM9811 4-Channel Mixing OKI ADPCM Type Voice Synthesis LSI GENERAL DESCRIPTION The MSM9811 is a 4-channel mixing voice synthesis LSI, to which up to 128 Mbits of ROM and/or EPROM storing voice data can directly be connected externally. The device is straight 8-bit PCM playback, non-linear 8-bit PCM playback, 4-bit ADPCM playback, and 4-bit ADPCM2 playback selectable and provides 2-channel stereo output and volume control. The MSM9811 contains a 14-bit D/A converter and LPF. The MSM9811 can easily configure a system by connecting voice data storage memory, power amplifier, and CPU externally.

FEATURES

• Non-linear 8-bit PCM/straight 8-bit PCM/4-bit ADPCM/4-bit ADPCM2
• Serial input or parallel input selectable
• Phrase Control Table function
• 4-channel mixing function
• Master clock frequency

4.096 MHz

• Sampling frequency 21.2 kHz, 25.6 kHz, 32.0 kHz
• Maximum number of phrases : 256
• Output channel L/R 2 channels
• Built-in volume control function (for each output channel)
• Built-in 14-bit D/A converter
• Built-in low-pass filter Digital filter
• Package 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (MSM9811GA)

16*9 MPY RD0 RD7 RA0 RA23 ROE RDAO AGND AVDD DGND DVDD RESET LDAO

PIN CONFIGURATION (TOP VIEW) DGND AGND TEST4 LDAO RDAO AVDD DVDD RCS TEST1 TEST2 XT XT TEST3 SERIAL CMD RD DVDD RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 ROE RD0 RD1 RD2 RD3 RD4 RD5 RA23 RA22 RA21 RA20 RA0 RA17 RA16 RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA19 RA18 NC WR NCR/BUSY CS D0/SR0 D1/SR1 D2/SR2 D3/SR3 D4/UD D5/SO D6/SI D7/SD RESET RD7 RD6 DGND NC: No connection 64-pin Plastic QFP

Description

40-47, 49-64 RA23-RA0 O Address pins for external memory. These pins become high impedance when RCS pin is “H“. 30, 31, 33-38 RD7-RD0 I Data pin for external memory. Pull-down resistors are internally connected to these pins. These pull-down resistors become valid when the RCS pin is “H”, and become invalid when the RCS pin is “L”. ROE O Output enable pin for external memory. This pin becomes high impedance when RCS pin is “H”. RCS I When this pin is “L”, RA23 to RA0 and ROE pins output address data and output enable signal. When this pin is “H”, RA23 to RA0 and ROE pins become high impedance. CMD I Select pin for Command data or Subcommand data for CPU interface. When this pin is “H”, subcommand input is selected. When this pin is “L”, command input is selected. A pull-up resistor is internally connected to this pin. RD I Read pin for CPU interface. A pull-up resistor is internally connected to this pin. WR I Write pin for CPU interface. A pull-up resistor is internally connected to this pin. CS I Chip select pin for CPU interface. When CS is “H”, WR signal is not entered in this LSI. A pull-up resistor is internally connected to this pin. SERIAL I CPU input interface select pin. When SERIAL is “H”, serial input interface is selected. When it is “L”, parallel input interface is selected. D7/SD I/O Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status data output pin. When serial input interface is selected, this pin serves as serial data input pin. D6/SI I/O Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, this pin serves as serial clock input pin. D5/SO I/O Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, this pin serves as channel status serial output pin.

Data bus pin for CPU interface when parallel interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, fix this pin at GND level. D3/SR3 D2/SR2 D1/SR1 D0/SR0 I/O Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, this pin serves as channel status output pin. Channels 4 thru 1 are output to SR3 thru SR0, respectively. LDAO O LEFT side D/A output pin. RDAO O RIGHT side D/A output pin. XT I Crystal or ceramic oscillator connection pin. A feedback resistor of about 1MΩ is connected between XT and XT. If necessary, enter external clocks into this pin. XT O Crystal or ceramic oscillator connection pin. When external clocks are used, leave this pin open. RESET I When this pin is “L” level, the LSI is initialized. At that time, oscillation stops and D/A outputs go to GND level. NCR/BUSY I Channel status select pin. When this pin is “H”, NCR signal is output. When it is “L”, BUSY signal is output. TEST1 TEST2 TEST3 TEST4 I Pins for LSI testing. Apply “L” level to these pins. 7, 48 DVDD Digital power supply pin. A bypass capacitor of 0.1 µF or more should be connected between the DGND pin and the DVDD pin. AVDD Analog power supply pin. A bypass capacitor of 0.1 µF or more should be connected between the AGND pin and the AVDD pin. 1, 32 DGND Digital GND pin. AGND Analog GND pin.

(GND = 0 V) Parameter Symbol Condition Rating Unit Power Supply Voltage VDD –0.3 to +7.0 V Input Voltage VIN Ta = 25°C –0.3 to VDD+ 0.3 V Storage Temperature TSTG –55 to +150 RECOMMENDED OPERATING CONDITIONS (GND = 0 V) Parameter Symbol Condition Range Unit Power Supply Voltage VDD 4.5 to 5.5 V Operating Temperature Top –40 to +85 Min. Typ. Max. Master Clock Frequency fOSC 3.5 4.096 4.5 MHz

ELECTRICAL CHARACTERISTICS

(DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit High-level Input Voltage VIH 0.84 × VDD V Low-level Input Voltage VIL 0.16 × VDD V High-level Output Voltage VOH IOH = –1 mA VDD – 0.4 V Low-level Output Voltage VOL IOL = 2 mA 0.4 V High-level Input Current 1 I IH1 VIH = VDD µA High-level Input Current 2 (Note 1) I IH2 Applied to pins with internal pull-down resistor 300 µA Low-level Input Current 1 IIL1 VIL = GND –10 µA Low-level Input Current 2 (Note 2) IIL2 Applied to pins with internal pull-up resistor –300 –30 µA Output Leakage Current ILO 0 ≤ VOUT ≤ VDD –10 +10 µA Operating Current IDD fOSC = 4 MHz, No load mA Ta = –40 to +70°C µA Standby Current IDS Ta = –40 to +85°C µA Notes 1: Applicable to RD7 to RD0 pins (when RCS = “H”). 2: Applicable to CMD, RD, WR, and CS pins.

(DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit LDAO,RDAO Load Resistance (During OP amplifier output) ROUTA kΩ LDAO,RDAO Output Impedance (When OP amplifier is not used) ROUTD kΩ LDAO,RDAO Output Level No load 0.7 to 0.94 VDD V AC Characteristics (VDD = 4.5 to 5.5 V, GND = 0 V, Ta = –40 to +85°C, CL = 5 pF) Parameter Symbol Min. Typ. Max. Unit Master Clock Duty Cycle fduty RESET Input Pulse Width tW(RST) µs RESET Delay Time From Raising of Power Supply tD(RST) µs Set up and Hold Time of CS for RD tCR ns RD Pulse Width tRR 200 ns Output Data Valid Time after Fall of RD tDRE 100 ns Data Float Time after Rise of RD tDRF ns Setup and Hold Time of CMD for WR tDW ns Setup and Hold Time of CS for WR tCW ns WR Pulse Width tWW 200 ns Data Setup Time before Rise of WR tDWS 100 ns Data Hold Time after Rise of WR tDWH ns WR - WR Pulse Interval tWWS 160 ns CS - CS Pulse Interval tCC 100 ns Serial Data Setup Time tSDS ns Serial Data Hold Time tSSD ns Serial Clock Pulse Width tW(SCK) 200 ns Output Data Valid Time after Rise of Serial Clock tSDD 200 ns Setup Time of WR for Serial Data tSWDS 200 ns Setup Time of Serial Clock Fall for WR Rise tSIWS 300 ns Setup Time of RD for Serial Clock Rise tSRIS 300 ns

TIMING DIAGRAMS (PARALLEL INPUT) Data Read Timing RD(I) D7 - D0(O) tRR tDRE tDRF Data out Valid CS(I) tCR tCR VIH VIL VIH VIL VOH VOL Data Write Timing (Sub-command, Command Input) CMD(I) CS(I) tWSS tDWS WR(I) D7 - D0(I) tDWH tWW tCW tDW tDW tCW tDW tDW tCC tDWS tDWH VIH VIL VIH VIL VIH VIL VIH VIL Data Stable Data Stable

TIMING DIAGRAMS (SERIAL INPUT) Data Write Timing (Sub-command, Command Input) CMD(I) CS(I) WR(I) SD(I) SI(I) tCW tDW tCC tDW tCW tDW tDW tWSS tSWDS tSIWS tSIWS WR(I) SD(I) SI(I) tSSD tSDS tW(SCK) tSWDS tW(SCK) tSSD tSDS tW(SCK) tW(SCK) VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

CS(I) RD(I) SO(O) SI(I) tCR tCR RD(I) SO(O) SI(I) tSRIS VIH VIL VIH VIL VOH VOL VIH VIL VIH VIL tSDD tSDD

TIMING DIAGRAM (COMMON TO PARALLEL AND SERIAL I/O) Power-on Timing · Power-down Timing VDD RESET(I) tD(RST) tW(RST) XT XT Reset processing Waiting for command Oscillation stabilization Oscillating 4.5V VIH VIL Standby RESET (I) tW(RST) LDAO (O) RDAO (O) XT XT Standby Waiting for command Waiting for command 1/2VDD GND Oscillating Oscillation stabilization time GND 1/2VDD 1/2VDD 1/2VDD Oscillating

Continuous Playback Timing When Phrase Control Table is not Used LDAO/RDAO Sub-command/ Command NCRn BUSYn FADR1 START FADR2 START FADR1 playback FADR2 playback

Continuous Playback Timing When Phrase Control Table is Used (Note) Do not enter the START command and MUON command during playback (BUSY = “L”) when the phrase control table is used. Otherwise, the LSI may malfunction. Enter the START command and MUON command after BUSY = “H”. LDAO/RDAO Sub-command/ Command NCRn BUSYn Note) FADR1 START FADR2 START FADR2 playback FADR1 playback

LOOP Playback Timing (Phrase Control Table is Used/not Used) LDAO/RDAO Sub-command/ Command NCRn BUSYn FADR1 START LOOP released LOOP set FADR1 playback LOOP valid FADR1 playback LOOP valid FADR1 playback

MUON Command Input Timing When Phrase Control Table is not Used DAOL/ DAOR Sub-command/ Command NCRn BUSYn FADR1 START FADR2 START MUON FADR2 playback FADR1 playback Silence (4 to 1020 ms) MUON command

MUON Command Input Timing When Phrase Control Table is Used DAOL/DAOR Sub-command/ Command NCRn BUSYn FADR1 Note) Note) START FADR2 START MUON FADR2 playback FADR1 playback Silence (4 to 1020 ms) MUON command (Note) Do not enter the START command and MUON command during playback (BUSY = “L”) when the phrase control table is used. Otherwise, the LSI may malfunction. Enter the START command and MUON command after BUSY = “H”.

The microcontroller interface includes two interface circuits, parallel interface and serial interface. The statuses of each pin both in parallel interface mode and in serial interface mode are shown below. SERIAL = “L” SERIAL = “H” Parallel I/O interface Serial I/O interface D7 (I/O) SD (I) Serial data input pin D6 (I/O) SI (I) Serial clock input pin D5 (I/O) SO (O) Serial data output pin D4 (I/O) UD (I) Fix this pin at GND level D3 (I/O) SR3 (O) D2 (I/O) SR2 (O) D1 (I/O) SR1 (O) D0 (I/O) Data I/O pins SR0 (O) Channel status signal output pin

Each command consists of a command and a sub-command. Data is input when the CMD pin is “H”. A command is input when the CMD pin is “L”. D7 to D0 NCRn Comman d name CMD pin H CH4 to CH1 Sets the bit of a voice synthesis start channel to “1”. Valid only at “H” START L X X X Starts playback. H CH4 to CH1 Sets the bit of a voice synthesis end channel to “1”. None STOP L X X X Ends playback. H CH4 to CH1 Sets the bit of a LOOP channel to “1”. None LOOP L X X X Starts LOOP. H O O O O Selects an option. None OPT L X X X H M7 to M0 Selects a silence time at M × 4 ms. (Condition: 1 ≤ M ≤ 255) Valid only at “H” MUON L C1 to C0 Selects a channel that outputs a silence and plays a silence. H FA7 to FA0 Selects a phrase to be played. None FADR L C1 to C0 Selects a channel that sets up a phrase. H SA23 to SA16 H SA15 to SA8 H SA7 to SA0 Selects a ROM address at which voice synthesis starts. H ST23 to ST16 H ST15 to ST8 H ST7 to ST0 Selects a ROM address at which voice synthesis ends. H S3 to S0 P1 to Selects a sampling frequency using S3 to S0. Selects a voice synthesis method using P1 to P0. None DADR L C1 to C0 Sets the condition to a channel selected by C1 to C0. H X X X X V3 to V0 Sets a playback volume between V3 and V0 × –2 dB. None CVOL L C1 to C0 Selects a channel to which a playback volume is set. H L3 to L0 R3 to R0 Selects a left side voice volume using L3 to L0 and selects a right side voice volume using R3 to R0. The volume of output is –2 dB × (L or R). None PAN L C1 to C0 Selects a channel for setting PAN using C1 to C0. X: Don’t Care

4.0 kHz 8.0 kHz 16.0 kHz 32.0 kHz Undefined 6.4 kHz 12.8 kHz 25.6 kHz Undefined 5.3 kHz 10.6 kHz 21.2 kHz Undefined Undefined Undefined Undefined Voice Synthesis Algorithm List P1 to P0 Voice synthesis algorithm OKI 4-bit ADPCM OKI 4-bit ADPCM2 8-bit Straight PCM OKI 8-bit Nonlinear PCM

–16 dB –2 dB –18 dB –4 dB –20 dB –6 dB –22 dB –8 dB –24 dB –10 dB –26 dB –12 dB –28 dB –14 dB –30 dB OPT Command List Default x x x Sets the volumes of all channels to VDD (p-p). x x x Sets the volumes of all channels to 1/2 VDD (p-p). x x x Sets the volumes of all channels to 1/4 VDD (p-p). x x x Sets the volumes of all channels to 1/8 VDD (p-p). x x x Secondary digital filtering is performed. x x x Primary digital filtering is performed. x x x x An on-chip digital filter is not used. x x x x Data is output directly from a D/A converter. (Output Z ≅ 3 kΩ) x x x x Data is output via a voltage follower. (Output Z ≅ 500 Ω) (Note) x indicates that data is independent of a function described.

LPF Frequency Characteristics This LSI contains a LPF in which a digital filter technology is used. The frequency characteristics when a secondary filter is used at fs = 8 kHz is shown below. The cutoff frequency is directly proportional to the sampling frequency fs. LPF Output Frequency Characteristics (fs = 8 kHz) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 100 1000 10000 100000 [Hz] [dB]

To enter the power down mode, set the RESET pin to “L”. When an external clock is supplied to the XT pin, fix the XT pin at “L”. If an external clock is supplied via the XT pin during the power down mode, the IDS specification is not satisfied because current flows between the XT pin and the XT pin. The circuit of XT and XT pins is shown below. Channel Status The channel status includes NCRn and BUSYn. These two channel statuses can be switched by setting the NCR/BUSY pin. Corresponding channel NCR/BUSY = “H” NCR/BUSY = “L” CH1 NCR1 BUSY1 CH2 NCR2 BUSY2 CH3 NCR3 BUSY3 CH4 NCR4 BUSY4 The n-channel NCR signal is NCRn and the n-channel BUSY signal is BUSYn. When NCRn is “H”, the START command and MUON command can be input for the next message of “n” channel to be played. When the phrase control table is used and BUSYn is “L”, do not enter the START command and MUON command even if NCRn is “H”. Otherwise, the LSI may malfunction. When BUSYn is “H”, the “n” channel does not output a voice. When BUSYn is “L”, the “n” channel outputs a voice. Approx. 500 kΩ RESET “L” Internal master clock XT “L” XT Power down mode

Parallel I/O (SERIAL = “L”) The outputs of channel statuses in parallel I/O mode are shown below. Pin name NCR/BUSY = “H” NCR/BUSY = “L” NCR4 BUSY4 NCR3 BUSY3 NCR2 BUSY2 NCR1 BUSY1 Serial I/O (SERIAL = “H”) The outputs when channel statuses are serially read during serial I/O mode are shown below. Signal name NCR/BUSY = “H” NCR/BUSY = “L” SO3 NCR4 BUSY4 SO2 NCR3 BUSY3 SO1 NCR2 BUSY2 SO0 NCR1 BUSY1 The outputs when channel statuses are output via SR3 to SR0 during serial I/O mode are shown below. Pin name NCR/BUSY = “H” NCR/BUSY = “L” SR3 NCR4 BUSY4 SR2 NCR3 BUSY3 SR1 NCR2 BUSY2 SR0 NCR1 BUSY1

Voice Synthesis Algorithms The MSM9811 contains 4-bit ADPCM algorithm, 4-bit ADPCM2 algorithm, 8-bit straight PCM algorithm, and 8-bit non-linear PCM algorithm. One of these algorithms can be selected depending on the kind of voices to be played. The features of these algorithms are described below. Voice synthesis algorithm Applicable waveform Feature Oki 4-bit ADPCM Normal voice waveforms Oki-original 4-bit ADPCM Oki 4-bit ADPCM2 Normal voice waveforms An improved version of Oki-original 4-bit ADPCM. This algorithm has improved its waveform traceability. Oki 8-bit Nonlinear PCM Sound effects including high frequency components This algorithm plays back the center of waveform as a 10-bit sound. 8-bit PCM Sound effects including high frequency components Normal 8-bit PCM algorithm Memory Configuration and Voice Data Creation Method The ROM data consists of a voice management area, a voice data area, and a phrase control table area. The voice management area controls the voice data start address, voice data end address, and use of the phrase control table. 256 phrases of voice management data are stored in this area. The voice data area stores actual waveform data. The phrase control table area stores data for effectively using voice data. See “Phrase Control Table Function” for details. The ROM data is created by using a dedicated tool. Voice management area (16 Kbit fixed) Voice data area Phrase control table area This area is used to create ROM data. 0x000000 0x0007FF 0x000800 max: 0x7ffffff max: 0x7ffffff ROM address

Playback Time and Memory Capacity The playback time is determined by external memory capacity, sampling frequency, and voice synthesis algorithm. The relationship is described below. (The bit length is 4 bits for ADPCM and ADPCM2 and 8 bits for PCM.) When the sampling frequency is 16 kHz and the voice synthesis algorithm is 4-bit ADPCM and an 8-Mbit ROM is used, the playback time is calculated as shown below. In the above equation, the playback time when the phrase control table function is not used is shown. 1.024 × (Memory capacity – 16) (Kbits) Sampling frequency (kHz) × bit length Playback time = (Seconds) 16 (kHz ) × 4 (bit) Playback time = ≅ 131 (Seconds)

It is possible to mix 4 channels at a time. Moreover, the LSI is capable of starting or stopping voices of each channel separately.

• Note on waveform clamping during mixing Increasing the number of channels to be mixed may cause clamping. To prevent clamping, reduce the volumes of all channels using the OPT command. (Note) Mixing using a different sampling frequency cannot be done. Continuous Playback Function The continuous playback function is used to continuously play back the next phrase after playing back a phrase. The next phrase to be played can be previously selected while a phrase is being played back. See “Continuous Playback Flowchart” for details. The continuous playback function is also available in the case of the phase control table. (Note) The following changes of voice synthesis algorithms are not permitted for continuous playback function. These changes may generate noises. ADPCM → ADPCM2 ADPCM2 → ADPCM

Phrase Control Table Function The phrase control table function is used to continuously play back multiple phrases and to set up a volume. It is possible to perform the following functions using the phrase control table function. CVOL setting Continuous playback (The number of continuous playbacks can be specified limitlessly, but depends on memory capacity.) Silence insertion function (4 mSec to 124 mSec) The memory capacity of voice ROM is effectively used by using the phrase control table function. Examples of ROM data when the phrase control table function is used are shown below. Example 1) Phrases when the phrase control table function is used Phrase 1 Phrase 2 Phrase 3 Phrase 4 It fine It is It is It is Phrase 5 rainy tomorrow tomorrow is It Silence is tomorrow It rainy fine today today fine rainy today is Example 2) ROM data when the example 1 is converted into ROM Address management area Phrase control area It fine rainy is today tomorrow (Note) In the phrase control table, each message of the playing phrase is provided with a CVOL value. Note that a CVOL value is overwritten over each message.

A volume can be adjusted at the stages of OPT, CVOL and PAN as shown below. A volume is set to all channels at the stage of OPT. A volume is set to each channel at the stage of CVOL. A volume is set to “L” and “R” of each channel at the stage of PAN. OPT PAN[L] CH1 CVOL CH2 CVOL CH3 CVOL CH4 CVOL PAN[R] PAN[L] PAN[R] PAN[L] PAN[R] PAN[L] PAN[R] Left-side Mixing Block Left-side Output Right- side Mixing Block Right- side Output ADPCM Block The output level attenuations when the CVOL, OPT and PAN commands are executed are shown below. <Left-side output volume calculation> Left-side output volume = (V + L) × –2 + (O4 × 2 + O3) × –6 [dB] Setting a volume (0 to 15) with the CVOL command Setting a left-side volume (0 to 15) with the PAN command O4, O3: Setting a volume (0 or 1) with the OPT command <Right-side output volume calculation> Right-side output volume = (V + L) x –2 + (O4 × 2 + O3) × –6 [dB] Setting a volume (0 to 15) with the CVOL command Setting a right-side volume (0 to 15) with the PAN command O4, O3: Setting a volume (0 or 1) with the OPT command

The OPT command changes the setting inside the LSI according to data stored in the TMP register. Table 4 shows the correspondence between data input (D7 to D0) and options. Table 4 OPT Command List Default x x x Sets the volumes of all channels to VDD (p-p). x x x Sets the volumes of all channels to 1/2 VDD (p-p). x x x Sets the volumes of all channels to 1/4 VDD (p-p). x x x Sets the volumes of all channels to 1/8 VDD (p-p). x x x Secondary digital filtering is performed. x x x Primary digital filtering is performed. x x x x An on-chip digital filter is not used. x x x x Data is output directly from a D/A converter. (Output Z ≅ 3 kΩ) x x x x Data is output via a voltage follower. (Output Z ≅ 500 Ω) (Note) x indicates that data is independent of a function described. When the OPT command is input, the LSI changes the option at the rising edge of the WR pulse. When power is turned on, or when the RESET pulse is input, the registers corresponding to D4-D0 have been set to “L”. If the option is changed when voice synthesis is in execution, voice quality may change. Oki recommends to set the option after power is turned on or after RESET is input. Volume Option Volume can be set by the CVOL command and PAN command, but a waveform may be clamped when channel synthesis is executed. If the CVOL command and PAN command are used to prevent a waveform from being clamped, the number of steps used for actual volume decreases, and effective voice synthesis may not be performed. If it is known that a waveform will be clamped, this option can set the volume of all channels to low, so that the number of steps of the volume can be utilized to the maximum level. Digital Filter Processing This LSI has a built-in oversampling circuit for digital filter processing. This oversampling system evenly generates four times more points of sampling frequencies. When power is turned on or if the RESET pulse is input, those pulses have been set to pass through the oversampling circuit. If digital filter processing is unnecessary, change this setting by the OPT command.

As Figure 7 shows, CS and WR pulses are input 7 times when CMD is in “H” status, to input data to the TMP1 to TMP7 registers. The LSI increments the registers at the rise of the WR pulse when CMD is “H”. CMD must not be “L” while inputting data. When CMD becomes “L” while inputting data, the increment of registers is cleared. Table 5 shows the configuration of data to be input to TMP1 to TMP7 registers. Table 5 TMP Register Data Configuration TMP1 register A23 A22 A21 A20 A19 A18 A17 A16 TMP2 register A15 A14 A13 A12 A11 A10 TMP3 register TMP4 register T23 T22 T21 T20 T19 T18 T17 T16 TMP5 register T15 T14 T13 T12 T11 T10 TMP6 register TMP7 register Input the start address of voice data to TMP1 to TMP3 registers. Input the stop address of voice data to TMP4 to TMP6 registers. Input the playback system and sampling frequency to the TMP7 register. Table 6 shows the input data configuration of the playback system and sampling frequency. Table 6 Data Configuration of Playback System and Sampling Frequency Sampling frequency 4.0 kHz Sampling frequency 8.0 kHz Sampling frequency 16.0 kHz Sampling frequency 32.0 kHz Sampling frequency 6.4 kHz Sampling frequency 12.8 kHz Sampling frequency 25.6 kHz Sampling frequency 5.3 kHz Sampling frequency 10.6 kHz Sampling frequency 21.3 kHz Playback algorithm: 4-bit ADPCM Playback algorithm: 4-bit ADPCM2 Playback algorithm: 8-bit non-linear PCM Playback algorithm: 8-bit straight PCM

The CVOL command adjusts the volume of the specified channel to the volume which corresponds to the size of data stored in the TMP register at the rise of the WR pulse. Volume can be set in 16 steps up to –30 dB in –2dB step units. Set data as shown in Table 7. Table 7 Volume Setting Data Configuration Volume(dB) 0 dB –2 dB –4 dB –6 dB –8 dB –10 dB –12 dB –14 dB –16 dB –18 dB –20 dB –22 dB –24 dB –26 dB –28 dB –30 dB (D7-D4: Don't care) When power is turned on and the RESET pulse is input, all channels are set to 0dB.

The PAN command adjusts the volume of the specified channel for the left and right respectively, to the volume which corresponds to the size of data stored in the TMP register at the rise of the WR pulse. This command enables stereo output. When volume is controlled by the OPT command and CVOL command, volume to be output is the volume stored in ROM multiplied by volume set by the OPT command, CVOL command, and PAN command respectively. This volume is output from LDAO and RDAO. Volume can be set in 16 steps up to –30 dB in –2 dB step units. Set data as shown in Table 8. Table 8 PAN Data Configuration Volume at left side Volume at right side 0 dB –2 dB –4 dB –6 dB –8 dB –10 dB –12 dB –14 dB –16 dB –18 dB –20 dB –22 dB –24 dB –26 dB –28 dB –30 dB

Select a phrase to start voice synthesis. (FADR command) Start monaural playback. Set up PAN for each channel. (PAN command) End playback? Select a channel to end playback. (STOP command) Yes No Select a channel to start playback. (START command) Do mixing with other channels? Set up a volume for each channel. (CVOL command)

Select a phrase of a left side channel. (FADR command) Start stereo playback. Do mixing with other channels? Start playback. (START command) End playback? Select a channel to end playback. (STOP command) No Yes Select a phrase of a right side channel. (FADR command) Set up PAN of a left side channel. (PAN command) Set up PAN of a right side channel. (PAN command)

Select a phrase to start voice synthesis. (FADR command) Start continuous playback. Set up PAN. (PAN command) Select a channel to start playback. (START command) Start voice synthesis of the first phrase. NCR = 1? Select a phrase to be played next. (FADR command) Select a channel to start playback. (START command) Select a phrase to be played next. No Yes Set up CVOL. (CVOL command) Is it possible to select a phrase to be played next?

It is possible to change the volume level of a channel that is being played. If the CVOL command is issued when voices are not being played, the changed volume level will be valid during the next playback. When the phrase control table function is used, the value of CVOL is changed by the phrase control table function because there are volume setting values in the phrase control table. CVOL command Voices are being played (BUSY = 0) Change the volume level of the selected channel? Yes No PAN command Change the volume level of the selected channel. Yes No Change the volume level of the selected channel. Change PAN of the channel?

Application circuit example when four 4 Mbit OTP ROMs are connected (serial input interface) RDAO AMP

(Unit: mm) QFP64-P-1414-0.80-BK Mirror finish Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating ( ≥5µm) Package weight (g) 0.87 TYP. Rev. No./Last Revised 6/Feb. 23, 2001 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

REVISION HISTORY

No. Date Previous Edition Current Edition Jun. 2000 Edition 1 FEDL9811FULL-02 May. 2001 Edition 2 7,20,31,32 7,20,31,32 Corrected the output impedance of analog signals. FEDL9811FULL-03 Jun 20, 2003 Corrected the word ”AOUT” to “LDAO,RDAO” In Analog Characteristics table. FEDL9811FULL-04 Sep. 1, 2004 Edition 4

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