MSM9200-XX OKI | Alldatasheet

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¡ Semiconductor GENERAL DESCRIPTION The MSM9200-xx is a dot matrix vacuum fluorescent display tube controller driver IC which displays characters, numerics and symbols. Dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from a microcontroller. A display system is easily realized by internal ROM and RAM for character display. The MSM9200-xx has low power consumption because it is munufactured in CMOS process technology. -01 and -02 are available as general codes. Custom codes are provided if necessary.

FEATURES

  • Logic power supply (VDD)
  • Fluorescent display tube drive power supply (VDISP)
  • Fluorescent display tube drive power supply (VFL) : –20 to –60 V
  • VFD driver output current (VFD driver output can directly be connected to the fluorescent display tube. No pull-down resistor is required.) - Segment driver (SEG1 to SEG35) : –5 mA (VFL=–60V) - Segment driver (AD1 to AD8) : –10 mA (VFL=–60V) - Grid driver (COM1 to COM16) : –30 mA (VFL=–60V)
  • General output port output current - Output driver (P1-4) : ±1 mA (VDD=3.3V±10%) ±2 mA (VDD=5.0V±10%)
  • Content of display - CGROM 5¥7 dots, 224 types (character data) - CGRAM 5¥7 dots, 32 types (character data) - ADRAM 16 (display digit) ¥8 bits (symbol data) - DCRAM 64 (stored digit) ¥8 bits (register for character data display) - General output port 4 bits (static mode)
  • Display control function - Display digit : 1 to 16 digits - Display duty (contrast adjustment) : 16 stages - Display blink position specification : Blinking time is input externally - Display shift (left and right) : Can be set only for SEG output - All lights ON/OFF
  • 4 interfaces with microcontroller : DA, CS, CP, and BLINK (5 interfaces when RESET is added)
  • 1 byte instruction execution (excluding data write to RAM and display blink position specification)
  • Oscillation circuit included (external C and R)
  • Package: 80-pin plastic QFP (QFP80-P-1414-0.65-K) (Product name: MSM9200-xxGS-K) xx indicated the code number. ¡ Semiconductor MSM9200-xx 5 ¥¥¥¥¥ 7 Dot Character ¥¥¥¥¥ 16-Digit Display Controller/Driver with Character RAM Preliminary E2C0035-27-Y4 This version: Nov. 1997 Previous version: Jul. 1996

¡ Semiconductor BLOCK DIAGRAM VDISP VDD GND VFL BLINK RESET DA CP CS OSC0 OSC1 SEG1 SEG35 AD1 AD8 COM1 COM16 DCRAM 64w¥8b CGROM 224w¥35b CGRAM 32w¥35b ADRAM 16w¥8b 8-bit Shift Register Command Decoder Control Circuit Timing Generator 1 Oscillator Timing Generator 2 Digit Control Duty Control Grid Driver Port Driver AD Driver Segment Driver DCRAM Address Counter Write Address Counter Read Address Counter Address Selector

¡ Semiconductor INPUT AND OUTPUT CONFIGURATION Schematic Diagrams of Logic Portion Input and Output Circuits Input Pin Output Pin Schematic Diagram of Driver Output Circuit GND VDD GND INPUT VDD GND VDD GND OUTPUT VDD VFL VDISP VFL OUTPUT VDISP

¡ Semiconductor PIN CONFIGURATION (TOP VIEW) VFL2 NC VDISP3 NC GND OSC0 OSC1 RESET BLINK DA CP CS VDD VDISP2 NC VFL1 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG35 SEG34 SEG33 SEG32 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 VDISP1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 NC: No connection 80-Pin Plastic QFP

¡ Semiconductor Pin Symbol Type

Description

O Fluorescent tube grid electrode 45 to 60 COM1-16 O Fluorescent tube grid electrode 1 to 8 AD1-8 O Fluorescent tube grid electrode 73 to 76 P1-4 O LED drive control terminals General port output. Output of these pins in static mode, so control for LED driving is performed through these pins. VDD 9, 63, 78 VDISP1-3 GND 61, 80 VFL1-2 Power supply Fluorescent display tube anode electrode drive output. Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH>–5 mA Fluorescent display tube grid electrode drive output. Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH>–30 mA Fluorescent display tube grid electrode drive output. Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH>–10 mA VDD-GND are power supplies for internal logic. VDISP-VFL are power supplies for driving fluorescent tubes. Use the same power supply for VDD and VDISP. Apply VFL after VDD and VDISP are applied. Connects to: DA I Micro- controller Serial data input (positive logic). Input from LSB. CP I Micro- controller Shift clock input. Serial data is shifted on the rising edge of CP. CS I Micro- controller Chip select input. "H" disables serial data transfer. BLINK I Micro- controller Display blink frequency input (square wave). Only the position specified by the display blink position set command is validated. The time of "High" (light ON) and "Low" (light OFF) level of the signal frequency to be input to BLINK is the blink time. Fix BLINK pin to the VDD or GND pin when the display blink control is not used. PIN DESCRIPTION

¡ Semiconductor Pin Symbol Type I C1, R1 OSC1 O External RC pin for RC oscillation. Connect R and C externally. The RC time constant depends on the VDD voltage used. Set the target oscillation frequency to 2 MHz. Connects to: OSC0 OSC1 RESET I Micro- controller Reset input (pull-up resistor included). "Low" initializes all the functions. Initial status is as follows.

  • Address of each RAM
  • Data of each RAM
  • Display digit
  • Contrast adjusment
  • Display blink
  • All lights ON or OFF
  • All outputs address "00"H Content is undefined 16 digits Blinking is disabled for all outputs OFF mode "Low" level RESET (Circuit when R and C are connected externally) See Application Circuit. (RC oscillation circuit) See Application Circuit. or C2, R2

¡ Semiconductor ABSOLUTE MAXIMUM RATINGS *1 Use the same power supply for VDD and VDISP. RECOMMENDED OPERATING CONDITIONS-1 When the power supply voltage is 5V (typ). Parameter Supply Voltage 1 Symbol Condition Rating Unit Supply Voltage 2 Input Voltage Power Dissipation Storage Temperature Output Current VDD VDISP VFL VIN PD TSTG IO3 (*1) Ta£25°C COM1-COM16 AD1-AD8 SEG1-SEG35 –0.3 to 6.5 –80 to VDISP+0.3 –80 to VDD+0.3 565 –55 to 150 –10 to 0.0 V V V mW –40 to 0.0 –20 to 0.0 mA IO1 IO2 (*1) –0.3 to 6.5 V IO4 P1-P4 –4.0 to 4.0 Parameter Supply Voltage 1 Symbol Condition Min. Typ. Max. Unit Supply Voltage 2 High Level Input Voltage Low Level Input Voltage CP Frequency Oscillation Frequency Frame Frequency Operating Temperature VDD VDISP VFL VIH VIL fC TOP All input pins excluding OSC0 pin All input pins excluding OSC0 pin R1=3.3kW, C1=47pF DIGIT=1–16, R1=3.3kW, C1=47pF 4.5 –60 0.7VDD –40 5.0 5.5 –20 0.3VDD 1.0 V V V V MHz 1.5 183 2.0 244 2.5 305 MHz Hz fOSC fFR RESET Input Time R2=1.0kW, C2=0.1PF 200 µs tRSON

¡ Semiconductor RECOMMENDED OPERATING CONDITIONS-2 When the power supply voltage is 3.3V (typ). Parameter Supply Voltage 1 Symbol Condition Min. Typ. Max. Unit Supply Voltage 2 High Level Input Voltage Low Level Input Voltage CP Frequency Oscillation Frequency Frame Frequency Operating Temperature VDD VDISP VFL VIH VIL fC TOP All input pins excluding OSC0 pin All input pins excluding OSC0 pin R1=3.3kW, C1=39pF DIGIT=1–16, R1=3.3kW, C1=39pF 3.0 –60 0.8VDD –40 3.3 3.6 –20 0.2VDD 1.0 V V V V MHz 1.5 183 2.0 244 2.5 305 MHz Hz fOSC fFR RESET Input Time R2=1.0kW, C2=0.1µF 200 µs tRSON

¡ Semiconductor

ELECTRICAL CHARACTERISTICS

Min. Max. Unit High Level Input Voltage VIH CS, CP, BLINK, DA, RESET CS, CP, BLINK, DA, RESET DA, RESET Low Level Input Voltage VIH=VDD VIL=0.0V CS, CP, BLINK, DA, RESET VIL IIH IIL High Level Input Current Low Level Input Current High Level Output Voltage VOH1 VOH2 VOH3 VOH4 COM1-16 AD1-8 SEG1-35 P1-4 IDD1 P1-4 COM1-16 AD1-8 SEG1-35 VDD, VDISP IOH1=–30mA IOH2=–10mA IOH3=–5mA IOH4=–2mA Duty=15/16 Digit=1–16 All output lights ON Low Level Output Voltage Current Consumption 0.7VDD –1.0 –1.0 VDISP–1.5 VDISP–1.5 VDISP–1.5 VDD–1.0 0.3VDD 1.0 1.0 1.0 V V µA µA V V V V V mA mA (VDD=VDISP=5.0V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified) CS, CP, BLINK, VFL+1.0 V IOL1=2mA VOL2 VOL1 IDD2 fOSC= 2MHz no load Duty=8/16 Digit=1–9 All output lights OFF

¡ Semiconductor DC Characteristics-2 Parameter Symbol Applied pin Condition Min. Max. Unit High Level Input Voltage VIH CS, CP, BLINK, DA, RESET CS, CP, BLINK, DA, RESET DA, RESET Low Level Input Voltage VIH=VDD VIL=0.0V CS, CP, BLINK, DA, RESET VIL IIH IIL High Level Input Current Low Level Input Current High Level Output Voltage VOH1 VOH2 VOH3 VOH4 COM1-16 AD1-8 SEG1-35 P1-4 IDD1 P1-4 COM1-16 AD1-8 SEG1-35 VDD, VDISP IOH1=–30mA IOH2=–10mA IOH3=–5mA IOH4=–1mA Duty=15/16 Digit=1–16 All output lights ON Low Level Output Voltage Current Consumption 0.0 0.8VDD –1.0 –1.0 VDISP–1.5 VDISP–1.5 VDISP–1.5 VDD–1.0 0.2VDD 1.0 1.0 1.0 V V µA µA V V V V V mA mA (VDD=VDISP=3.3V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified) CS, CP, BLINK, VFL+1.0 V IOL1=1mA VOL2 VOL1 IDD2 fOSC= 2MHz no load Duty=8/16 Digit=1–9 All output lights OFF

¡ Semiconductor AC Characteristics-1 Parameter Symbol Condition Min. Max. Unit CP Pulse Width DA Setup Time DA Hold Time CS Setup Time CS Hold Time CS Wait Time Data Processing Time RESET Pulse Width Waite DA Time All Output Slow Rate VDD Rise Time tCW tDS tDH tCSS tCSH tCSW tDOFF tRSON tRSOFF tR tPRZ R1=3.3kW, C1=47PF R1=3.3kW, C1=47PF tR=20% to 80% tF=80% to 20% When mounted in the unit 300 300 300 300 300 300 4.0 100 ns ns ns ns ms ns ms ms ms ms CP Frequncy fC 1.0 MHz When RESET signal is input externally 300 ns (VDD, VDISP=5.0V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified) tF Cl=100pF 4.0 ms VDD Off Time tPOF When mounted in the unit, VDD=0.0V 5.0 ms AC Characteristics-2 Parameter Symbol Condition Min. Max. Unit CP Pulse Width DA Setup Time DA Hold Time CS Setup Time CS Hold Time CS Wait Time Data Processing Time RESET Pulse Width DA Wait Time All Output Slew Rate VDD Rise Time tCW tDS tDH tCSS tCSH tCSW tDOFF tWRES tRSOFF tR tPRZ R1=3.3kW, C1=39PF R1=3.3kW, C1=39PF Cl=100pF When mounted in the unit 300 300 300 300 300 300 4.0 100 ns ns ns ns ms ns ms ms ms ms CP Frequncy fC 1.0 MHz When RESET signal is input externally 300 ns (VDD, VDISP=3.3V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified) tF 4.0 ms tR=20% to 80% tF=80% to 20% VDD Off Time tPOF When mounted in the unit, VDD=0.0V 5.0 ms

¡ Semiconductor TIMING DIAGRAM

  • Data Timing CS CP DA tCSS tC tDS tDH tDOFF tCW tCW tCSH tCSW VALID VALID VALID VALID VIH VIH fC VIL VIL VIH VIL
  • Reset Timing VDD RESET DA tPRZ tRSON tRSOFF tRSOFF tOF tWRES When external R and C are connected. When input externally

0.8 VDD

0.0 V VIL VIH VIL

0.5 VDD

  • Output Timing All outputs tF tR

0.8 VDISP

0.2 VFL

VDD=3.3V±10% VDD=5.0V±10% VIH

0.7 VDD

0.2 VDD

0.3 VDD

¡ Semiconductor FUNCTIONAL DESCRIPTION Command List 1st byte 2nd byte LSB MSB LSB MSB Command DCRAM data write 1 A B C D E DCRAM data write 2 DCRAM data write 3 DCRAM data write 4 CGRAM data write 1 CGRAM data write 2 ADRAM data write Display blink position set DCRAM address shift DCRAM address reset General output port set Display duty set Number of digits set All lights ON/OFF Test mode C10 C15 C20 C25 C30 C11 C16 C21 C26 C31 C12 C17 C22 C27 C32 C13 C18 C23 C28 C33 C14 C19 C24 C29 C34 G10 G11 G12 G13 G14 G15 G16 SG AD S L H C10 C15 C20 C25 C30 C11 C16 C21 C26 C31 C12 C17 C22 C27 C32 C13 C18 C23 C28 C33 C14 C19 C24 C29 C34 2nd byte 3rd byte 4th byte 5th byte 6th byte Xn Cn SG AD Gn S Pn Dn Kn H L : Don't care : Address specification for each RAM : Character code specification for each RAM : SEG display area specification : AD display area specification : Display blink position specification : Left and right display shift specification : General output port status specification : Display duty specification : Number of digits specification : All lights ON instruction : All lights OFF instruction When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes. Note: The test mode is used for inspection before shipment. It is not a user function. 2nd byte 3rd byte 4th byte 5th byte 6th byte 2nd byte 3rd byte

¡ Semiconductor Positional Relationship Between SEGn and ADn (one digit) AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 SEG1 SEG6 C10 SEG11 C15 SEG16 C20 SEG21 C25 SEG26 C30 SEG31 SEG2 SEG7 C11 SEG12 C16 SEG17 C21 SEG22 C26 SEG27 C31 SEG32 SEG3 SEG8 C12 SEG13 C17 SEG18 C22 SEG23 C27 SEG28 C32 SEG33 SEG4 SEG9 C13 SEG14 C18 SEG19 C23 SEG24 C28 SEG29 C33 SEG34 SEG5 SEG10 C14 SEG15 C19 SEG20 C24 SEG25 C29 SEG30 C34 SEG35 Area for the ADRAM data to be output CGRAM written data. Corresponds to 2nd byte CGRAM written data. Corresponds to 3rd byte CGRAM written data. Corresponds to 4th byte CGRAM written data. Corresponds to 6th byte CGRAM written data. Corresponds to 5th byte

¡ Semiconductor Data Transfer System and Command Write System Display control command and data are written by an 8-bit serial transfer. Write timing is shown in the figure below. Setting the CS pin to "Low" level enables a data transfer. Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first). As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each register and RAM. Therefore it is not necessary to input load signals from the outside. Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin changes from "High" to "Low" is recognized in 8-bit units. When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes. Reset Function Reset is executed when the RESET pin is set to "L", (when turning power on, for example,) and initializes all functions. Initial status is as follows. Reset again according to "Initial Setting Flowchart" after reset. tDOFF LSB CS CP DA B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 MSB 1st byte LSB MSB 2nd byte When data is written to DCRAM* Command and address data tCSH B0 B1 B2 B3 B4 B5 B6 B7 LSB MSB 2nd byte Character code data of the next address Character code data

¡ Semiconductor Description of Commands and Functions 1. DCRAM data write 1 (Specifies the address (00H to 0FH) of DCRAM and writes the character code of CGROM and CGRAM.) 2. DCRAM data write 2 (Specifies the address (10H to 1FH) of DCRAM and writes the character code of CGROM and CGRAM.) 3. DCRAM data write 3 (Specifies the address (20H to 2FH) of DCRAM and writes the character code of CGROM and CGRAM.) 4. DCRAM data write 4 (Specifies the address (30H to 3FH) of DCRAM and writes the character code of CGROM and CGRAM.) DCRAM (Data Control RAM) has a 6-bit address to store character code of CGROM and CGRAM. (4 bits can be set by the user and the 2 bits on the MSB side are automatically set.) The character code specified by DCRAM is converted to a 5¥7 dot matrix character pattern via CGROM or CGRAM. The capacity is 64¥8 bits, which can store 64 characters. Note: The addresses 00H to 3FH of DCRAM are automatically incremented. [Command format] 1st byte (1st) LSB MSB 2nd byte (2nd) LSB MSB : selects DCRAM data write mode and specifies DCRAM address (Ex: Specifies DCRAM address 00H) : specifies character code of CGROM and CGRAM : written into DCRAM address 00H To specify the character code of CGROM and CGRAM continuously to the next address, specify only character code as follows. The addresses of DCRAM are automatically incremented. Specification of an address is unnecessary.

¡ Semiconductor 2nd byte (3rd) LSB MSB 2nd byte (4th) LSB MSB : specifies character code of CGROM and CGRAM : written into DCRAM address 01H : specifies character code of CGROM and CGRAM : written into DCRAM address 02H 2nd byte (17th) LSB MSB 2nd byte (18th) LSB MSB : specifies character code of CGROM and CGRAM : written into DCRAM address 0FH : specifies character code of CGROM and CGRAM : written into DCRAM address 10H 2nd byte (65th) LSB MSB 2nd byte (66th) LSB MSB : specifies character code of CGROM and CGRAM : written into DCRAM address 3FH : specifies character code of CGROM and CGRAM : DCRAM address 00H is rewritten X0 (LSB) to X3 (MSB): DCRAM addresses (4 bits: 16 characters) Note: A total of 64 characters for the four specifications C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 character) [COM positions and set DCRAM addresses] The states when RESET is input and DCRAM address reset commands are executed Command No. HEX K0 COM position K1 K2 K3 Command No. HEX K0 COM position K1 K2 K3 COM1 COM2 COM15 COM16

¡ Semiconductor 5. CGRAM data write 1 (Specifies the addresses 00H to 0FH of CGRAM and writes character pattern data.) 6. CGRAM data write 2 (Specifies the addresses 10H to 1FH of CGRAM and writes character pattern data.) CGRAM (Character Generator RAM) has a 5-bit address to store 5¥7 dot matrix character patterns. (4 bits can be set by the user and the 1 bit on the MSB is automatically set.) A character pattern stored in CGRAM can be displayed by specifying the character code (address) by DCRAM. The address of CGRAM is assigned to 00H to 1FH. (All the other addresses are the CGROM addresses.) Capacity is (16¥2)¥35¥8 bits, which can store 32 types of character patterns. Note: The addresses 00H to 1FH of CGRAM are automatically incremented. [Command format] C5 C10 C15 C20 C25 C30 * 2nd byte (2nd) LSB MSB : specifies 1st column data : rewritten into CGRAM address 00H C6 C11 C16 C21 C26 C31 * 3rd byte (3rd) LSB MSB : specifies 2nd column data : rewritten into CGRAM address 00H 1st byte (1st) LSB MSB : selects CGRAM data write mode and specifies CGRAM address. (Ex: specifies CGRAM address 00H) C7 C12 C17 C22 C27 C32 * 4th byte (4th) LSB MSB : specifies 3rd column data : rewritten into CGRAM address 00H C8 C13 C18 C23 C28 C33 * 5th byte (5th) LSB MSB : specifies 4th column data : rewritten into CGRAM address 00H C9 C14 C19 C24 C29 C34 * 6th byte (6th) LSB MSB : specifies 5th column data : rewritten into CGRAM address 00H To specify character pattern data continuously to the next address, specify only character pattern data as follows. The addresses of CGRAM are automatically incremented. Specification of an address is therefore unnecessary. The 2nd to 6th byte (character pattern data) are regarded as one data item, so 300 ns is sufficient for tDOFF time between bytes.

¡ Semiconductor C5 C10 C15 C20 C25 C30 * 2nd byte (7th) LSB MSB specifies 1st column data : rewritten into CGRAM address 01H C9 C14 C19 C24 C29 C34 * 6th byte (11th) LSB MSB specifies 5th column data : rewritten into CGRAM address 01H C5 C10 C15 C20 C25 C30 * 2nd byte (12th) LSB MSB specifies 1st column data : rewritten into CGRAM address 02H C9 C14 C19 C24 C29 C34 * 6th byte (16th) LSB MSB specifies 5th column data : rewritten into CGRAM address 02H C5 C10 C15 C20 C25 C30 * 2nd byte (77th) LSB MSB specifies 1st column data : rewritten into CGRAM address 0FH C9 C14 C19 C24 C29 C34 * 6th byte (81th) LSB MSB specifies 5th column data : rewritten into CGRAM address 0FH C5 C10 C15 C20 C25 C30 * 2nd byte (82th) LSB MSB specifies 1st column data : rewritten into CGRAM address 10H C9 C14 C19 C24 C29 C34 * 6th byte (86th) LSB MSB specifies 5th column data : rewritten into CGRAM address 10H C5 C10 C15 C20 C25 C30 * 2nd byte (157th) LSB MSB specifies 1st column data : rewritten into CGRAM address 1FH C9 C14 C19 C24 C29 C34 * 6th byte (161th) LSB MSB specifies 5th column data : rewritten into CGRAM address 1FH C5 C10 C15 C20 C25 C30 * 2nd byte (162th) LSB MSB specifies 1st column data (CGRAM address 00H is rewritten) C9 C14 C19 C24 C29 C34 * 6th byte (167th) LSB MSB specifies 5th column data (CGRAM address 00H is rewritten) X0 (LSB) to X3 (MSB): CGRAM addresses (4 bits: 16 characters) Note: A total of 32 characters for the two specifications. C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per digit)

¡ Semiconductor C10 C15 C20 C25 C30 C11 C16 C21 C26 C31 C12 C17 C22 C27 C32 C13 C18 C23 C28 C33 C14 C19 C24 C29 C34 area that corresponds to 2nd byte (1st column) area that corresponds to 3rd byte (2nd column) area that corresponds to 5th byte (4th column) area that corresponds to 6th byte (5th column) area that corresponds to 4th byte (3rd column) Positional relationship between the output area of CGROM and that of CGRAM Note: CGROM (Character Generator ROM) has an 8-bit address to generate 5¥7 dot matrix character patterns. The capacity is 224¥35¥8 bits, which can store 224 types of character patterns. 2 types of general-purpose code are availble (see ROM CODE list) and custom codes are provided on customer's request. [CGROM addresses and set CGRAM addresses] Refer to ROMCODE table Command No. HEX K0 CGROM address K1 K2 K3 Command No. HEX K0 CGROM address K1 K2 K3 RAM00(00000000B) RAM01(00000001B) RAM10(00010000B) RAM11(00010001B) RAM02(00000010B) RAM03(00000011B) RAM12(00010010B) RAM13(00010011B) RAM04(00000100B) RAM05(00000101B) RAM14(00010100B) RAM15(00010101B) RAM06(00000110B) RAM07(00000111B) RAM16(00010110B) RAM17(00010011B) RAM08(00001000B) RAM09(00001001B) RAM18(00011000B) RAM19(00011001B) RAM0A(00001010B) RAM0B(00001011B) RAM1A(00011010B) RAM1B(00011011B) RAM0C(00001100B) RAM0D(00001101B) RAM1C(00011100B) RAM1D(00011101B) RAM0E(00001110B) RAM0F(00001111B) RAM1E(00011110B) RAM1F(00011111B)

¡ Semiconductor 7. ADRAM data write (specifies address of ADRAM and writes symbol data) ADRAM (Additional Data RAM) has a 4-bit address to store symbol data. Symbol data specified by ADRAM is directly output without CGROM and CGRAM. The capacity is 8¥16 bits, which can store 8 types of symbol patterns for each digit. The terminal to which the contents of ADRAM are output can be used as a cursor. [Command format] 2nd byte (2nd) LSB MSB : sets symbol data (written into ADRAM address 0H) 1st byte (1st) LSB MSB : selects ADRAM data write mode and specifies ADRAM address (Ex: specifies ADRAM address 0H) To specify symbol data continuously to the next address, specify only symbol data as follows. The address of ADRAM is automatically incremented. Specification of addresses is therefore unnecessary. 2nd byte (3rd) LSB MSB : sets symbol data (written into ADRAM address 1H) 2nd byte (4th) LSB MSB : sets symbol data (written into ADRAM address 2H) 2nd byte (17th) LSB MSB : sets symbol data (written into ADRAM address FH) 2nd byte (18th) LSB MSB : sets symbol data (ADRAM address 00H is rewritten.) X0 (LSB) to X3 (MSB): ADRAM addresses (4 bits: 16 characters) C0 (LSB) to C7 (MSB): Symbol data (8-symbol data per digit)

¡ Semiconductor [COM positions and ADRAM addresses] HEX D0 COM position D1 D2 D3 HEX D0 COM position D1 D2 D3 COM1 COM9 COM2 COM10 A COM3 COM11 B COM4 COM12 C COM5 COM13 D COM6 COM14 E COM7 COM15 F COM8 COM16 8. Display blink position set (sets the blink position for the SEG area or AD area in COMn. Display blink position can be set separately for the SEG area and AD area. In this case, select by command in which COMn the SEG area or AD area is made blink. The blink disabled state is entered for this setting when power is turned on or when a RESET signal is input. The display blink cycle is determined by the frequency to be input to the BLINK pin. [Command format] G1 G2 G3 G4 G5 G6 G7 G8 2nd byte (2nd) LSB MSB : specifies blink position to COM1 to COM8 G9 G10 G11 G12 G13 G14 G15 G16 3rd byte (3rd) LSB MSB : specifies blink position to COM9 to COM16 SG AD * 1st byte (1st) LSB MSB : selects either the AD output area or the segment output area and specifies digit The 2nd and 3rd bytes (COM1 to COM16 position specification) are regarded as one data item, so 300 ns is sufficient for tDOFF time between bytes. SG: Specifies SEG area AD: Specifies AD area Gn: Specifies blinks

¡ Semiconductor [SEG and AD display and set data] SG/AD Gn Does not blink (current state) Does not bilnk (current state) Specified positions do not blink Specified positions blink SEG and AD display (The state when power is applied or when RESET is input) Note: If both SG and AD are set to "1" by command, both the SEG area and the AD area are specified. 9. DCRAM address shift (Shifts SEG output left or right.) DCRAM address shift shifts SEG output 1 digit to the left or right using 1 bit data. AD output cannot be shifted. [Command format] SG * 1st byte LSB MSB : selects DCRAM address shift and sets shift value (left, right) S: Specifies the direction of shift [Set data and shift direction of display] S Shift direction of display Shift to left Shift to right

¡ Semiconductor [DCRAM address shift and COM positions] When S=0 (shift to left) is performed from the initial state. Command No. HEX K0 COM position K1 K2 K3 Command No. HEX K0 COM position K1 K2 K3 COM2 COM3 COM16 COM1 When S=1 (shift to right) is performed from the initial state. Command No. HEX K0 COM position K1 K2 K3 Command No. HEX K0 COM position K1 K2 K3 COM1 COM14 COM15 COM16

¡ Semiconductor A. DCRAM address reset (returns display status to initial setting status) The DCRAM address reset returns the status where a DCRAM address shift is executed to initial status. [Command format] 1st byte LSB MSB : selects DCRAM address reset Relation between the DCRAM address shifts and the COM outputs COM output 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DCRAM address (HEX) Initial status or the status where display address reset executed (DCRAM address is 00H) COM output 10 11 12 13 14 15 16 3F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E DCRAM address (HEX) When left shift is executed in the initial status COM output 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 DCRAM address (HEX) When right shift is executed in the initial status B. General output port set (specifies the general output port status) The general output port is an output for 4-bit static operation. It is used to control other I/O devices and turn on LED. When at the "High" level, this output becomes the VDD voltage, and when at the "Low" level, it becomes the ground potential. Therefore, the fluorescent display tube cannot be driven. [Command format] P1-P4: general output port [Set data and set state of general output port] 1st byte LSB MSB : selects a general output port and specifies the output status Pn Display state of general output port Sets to the output to Low Sets to the output to High (The state when power is applied or when RESET is input.)

¡ Semiconductor C. Display duty set (writes display duty value to duty cycle register) Display duty adjusts contrast in 16 stages using 4-bit data. When power is turned on or when the RESET signal is input, the duty cycle register value is "0". Always execute this instruction before turning the display on, then set a desired duty value. [Command format] D0 D1 D2 D3 1st byte LSB MSB : selects display duty set mode and sets duty value D0 (LSB) to D3 (MSB): display duty data (4 bits: 16 stages) [Relation between setup data and controlled COM duty] HEX COM duty HEX COM duty A B C D E F The state when powered on or when RESET signal inputs.

¡ Semiconductor D. Number of digits set (writes the number of display digits to the display digit register) The number of digits set can display a maximum of 16 digits using 4-bit data. When power is turned on or when a RESET signal is input, the number of digit register value is "0". Always execute this instruction to change the number of digits before turning the dispaly on. [Command format] 1st byte LSB MSB : selects the number of digit set mode and specifies the number of digit value K0 (LSB) to K3 (MSB): number of digit data (4 bits: 16 digits) [Relation between setup data and controlled COM] HEX Number of digits of COM COM1-16 COM1-1 COM1-2 COM1-3 COM1-4 COM1-5 COM1-6 COM1-7 HEX Number of digits of COM A B C D E F COM1-8 COM1-9 COM1-10 COM1-11 COM1-12 COM1-13 COM1-14 COM1-15 E. All display lights ON/OFF set (turns all dispaly lights ON or OFF) All display lights ON is used primarily for display testing. All display lights OFF is primarily used to prevent malfunction when power is turned on. [Command format] L H 1st byte LSB MSB : selects all display lights ON or OFF mode and sets all lights ON or OFF value [Set data and display state of SEG and AD] H All outputs maintain current states Sets all outputs to Low Sets all outputs to High Sets all outputs to High Display state of SEG and AD L (The state when power is applied or when RESET is input.) (All lights ON mode has priority.)

¡ Semiconductor Initial Setting Flowchart Apply VFL All display lights OFF Number of digits set Display duty set CGRAM Data write mode (with address set) CGRAM Character code CGRAM Is character code write ended? Another RAM to be set? General output port set Releases all display lights OFF mode ADRAM Data write mode (with address set) ADRAM Character code ADRAM Is character code write ended? DCRAM Data write mode (with address set) DCRAM Character code DCRAM Is character code write ended? Select a RAM to be used Status of all outputs by RESET signal input Display operation mode Address is automatically incremented NO NO NO YES YES YES YES End Address is automatically incremented Address is automatically incremented

¡ Semiconductor APPLICATION CIRCUIT Notes: 1. The VDD value depends on the power supply voltage of the microcontroller used. Adjust the values of the constants R1, R2, R4, C1, and C2 to the power supply voltage used. 2. The VFL value depends on the fluorescent display tube used. Adjust the values of the constants R3 and ZD to the power supply voltage used. MSM9200-xx MCU RESET VDD, VDISP1-3 COM1-16 SEG1-35 AD1-8 BLINK VDD GND GND VFL1-2 OSC0 OSC1 DA CP CS Output port P1-4 VDD VFL ZD 5¥7-dot matrix fluorescent display tube GRID (DIGIT) ANODE (SEGMENT) ANODE (SEGMENT) Heater transformer LED VDD NPN Tr GND

¡ Semiconductor Reference data The figure below shows the relationship between the VFL voltage and the output current of each driver. Take care that the total power consumtion to be used does not exceed the power dissipation. –30 –25 –20 –15 –10 –10 –20 –30 –40 –50 –60 [Output Current] (mA) [VFL Voltage (VDD-n) ] COM1 to COM16 (Condition: VOH=VDISP–1.5 V) AD1 to AD8 (Condition: VOH=VDISP–1.5 V) SEG1 to SEG35 (Condition: VOH=VDISP–1.5 V) (V) (mA) [VFL Voltage-Output Current of Each Driver]

¡ Semiconductor MSM9200-01 ROM Code 00000000B (00H) to 00011111B (1FH) are the CGRAM addresses. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1101 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 RAM00 RAM10 RAM01 RAM11 RAM02 RAM12 RAM03 RAM13 RAM04 RAM14 RAM05 RAM15 RAM06 RAM16 RAM07 RAM17 RAM08 RAM18 RAM09 RAM19 RAM0A RAM1A RAM0B RAM1B RAM0C RAM1C RAM0D RAM1D RAM0E RAM1E RAM0F RAM1F MSB LSB

¡ Semiconductor MSM9200-02 ROM Code 00000000B (00H) to 00011111B (1FH) are the CGRAM addresses. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1101 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 RAM00 RAM10 RAM01 RAM11 RAM02 RAM12 RAM03 RAM13 RAM04 RAM14 RAM05 RAM15 RAM06 RAM16 RAM07 RAM17 RAM08 RAM18 RAM09 RAM19 RAM0A RAM1A RAM0B RAM1B RAM0C RAM1C RAM0D RAM1D RAM0E RAM1E RAM0F RAM1F MSB LSB

¡ Semiconductor Digit Output Timing (for 16-digit display, at a duty of 15/16) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 AD1-8 SEG1-35 VFL t1=1024T t2=60T t3=4T Frame cycle Display timing Blank timing VDISP VFL VDISP T=8/ fOSC (t1=4.096 ms when fosc=2.0 MHz) (t2=240 ms when fosc=2.0 MHz) (t3=16 ms when fosc=2.0 MHz)

¡ Semiconductor (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.85 TYP. QFP80-P-1414-0.65-K Mirror finish