MSM81C55-5RS

MSM81C55-5RS OKI | Alldatasheet

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¡ Semiconductor MSM81C55-5RS/GS/JS GENERAL DESCRIPTION The MSM81C55-5 has a 2k-bit static RAM (256 bytes) with parallel I/O ports and a timer. It uses silicon gate CMOS technology and consumes a standby current of 100 micro ampere, maximum, while the chip is not selected. Featureing a maximum access time of 400 ns, the MSM81C55-5 can be used in an MSM80C85AH system without using wait states. The parallel I/O consists of two 8-bit ports and one 6-bit port (both general purpose). The MSM81C55-5 also contains a 14-bit programmable counter/timer which may be used for sequence-wave generation or terminal count-pulsing.

FEATURES

• High speed and low power achieved with silicon gate CMOS technology
• 256 words x 8bits RAM
• Single power supply, 3 to 6 V
• Completely static operation
• On-chip address latch
• 8-bit programmable I/O ports (port A and B)
• TTL Compatible
• RAM data hold characteristic at 2 V
• 6-bit programmable I/O port (port C)
• 14-bit programmable binary counter/timer
• Multiplexed address/data bus
• Direct interface with MSM80C85AH
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM81C55-5RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM81C55-5JS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM81C55-5GS-2K) FUNCTIONAL BLOCK DIAGRAM ¡ Semiconductor MSM81C55-5RS/GS/JS 2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER IO/M AD0 - 7 CE ALE RD WR RESET TIMER IN TIMER OUT Timer 256 · 8 Static RAM A B C Port A Port B Port C PA0 - 7 PB0 - 7 PC0 - 5 VCC (+5 V) GND (0 V) E2O0014-27-X2 This version: Jan. 1998 Previous version: Aug. 1996

¡ Semiconductor MSM81C55-5RS/GS/JS PIN CONFIGURATION (TOP VIEW) 40 pin Plastic DIP 44 pin Plastic QFP PC TIMER IN RESET TIMER OUT IO/M CE RD WR ALE GND PC PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VCC AD7 AD6 AD5 PC4 PC5 AD4 AD3 AD2 AD1 AD0 PB PB5 PB4 PB3 PB2 NC PB1 TIMER OUT IO/M CE RD WR NC ALE AD NC AD5 AD6 AD7 GND PA0 PC RESET TIMER IN PC PC3 NC PB PA7 PA6 AD0 AD1 AD2 AD3 17 PA VCC PA PA2 PA3 PA4 PC PC1 PC0 PB7 44 pin Plastic QFJ PB PB5 PB4 PB3 PB2 PB1 PB0 TIMEROUT IO/M CE RD WR ALE AD0 AD AD5 AD6 AD7 GND VCC PA0 PC RESET TIMER IN PC PC3 VCC PA PA6 PA5 AD1 AD2 AD3 NC 11 PA NC PA PA2 PA3 NC PC PC1 PC0 PB7

¡ Semiconductor MSM81C55-5RS/GS/JS ABSOLUTE MAXIMUM RATING –55 to +150 MSM81C55-5RS Power Supply Voltage VCC –0.5 to +7 V Input Voltage VIN –0.5 to VCC +0.5 V Output Voltage VOUT –0.5 to VCC +0.5 V Storage Temperature TSTG °C Power Dissipation PD 0.7 W Parameter UnitSymbol Referenced to GND Ta = 25°C Conditions Rating MSM81C55-5GS MSM81C55-5JS 1.01.0 OPERATING CONDITION Range Power Supply Voltage VCC 3 to 6 V Operating Temperature TOP –40 to +85 °C Parameter UnitSymbol RECOMMENDED OPERATING CONDITIONS Typ. Power Supply Voltage (81C55) VCC 5V TOP +25 "L" Level Input V IL — "H" Level Input VIH — Min. 4.5 –40 –0.3 2.2 Max. 5.5 +85 +0.8 VCC +0.3 Parameter UnitSymbol V V Supply Voltage (81C55-5) VCC 54.75 5.25 V Operating Temperature (81C55-5) VOP +25–40 +70 °C Operating Temperature (81C55) DC CHARACTERISTICS Typ. Max. "L" Level Output Voltage VOL — 0.45 V "H" Level Output Voltage VOH —— V —— V Parameter UnitSymbol Min. 2.4 4.2 IOL = 2 mA IOH = –400 mA IOH = –40 mA Condition VCC = 4.5 V to 5.5 V Ta = –40°C to 85°C Input Leak Current ILI —1 0 mA Output Leak Current ILO —1 0 mA –10 –10 0 £ VIN £ VCC 0 £ VOUT £ VCC CE ‡ VCC –0.2 V VIH ‡ VCC –0.2 V VIL £ –0.2 V Standby Current Mean Operating Current ICCS 0.1 100 mA —5 mA —Memory cycle time: 1 msICC

¡ Semiconductor MSM81C55-5RS/GS/JS AC CHARACTERISTICS Parameter Symbol Unit Remarks Max.Min. VCC = 4.75 V to 5.25 V, Ta = –40 to +70°C 80C85AH 5MHz I/F Max.Min. VCC = 4.5 V to 5.5 V, Ta = –40 to +80°C 80C85AH 3MHz I/F Address/latch Setup Time tAL ns Latch/address Holt Time tLA ns 37 — 30 — 50 — 30 — Read/output Delay Time Latch/read (write) Delay Time tLC ns40 —100 — Address/output Delay Time tRD ns— 140— 170 Latch Width tAD ns— 330— 400 Read/data Bus Floating Time tLL tRDF ns70 —100 — Read (write)/latch Delay Time tCL ns08 00 100 Read (write) Width tCC ns20 —20 — Data In/write Setup Time tDW ns200 —250 — Write/data-in Hold Time tWD ns100 —150 — Recovery Time tRV ns25 —0 — Write/port Output Delay Time tWP ns200 —300 — tPR ns— 300— 400 Port Input/read Setup Time Load capaci- tance: 150 pFtRP ns Read/port Input Hold Time tSBF ns 50 — 10 — 70 — 50 — Strobe Width Strobe/buffer Full Delay Time tSS ns— 300— 400 Strobe/buffer Empty Delay Time tRBE ns150 —200 — Strobe/interrupt-on Delay Time tSI ns— 300— 400 tRDI ns— 300— 400 Read/interrupt-off Delay Time Port Input/strobe Setup Time tPSS ns— 300— 400 Strobe/port-input Hold Time tPHS ns20 —50 — Strobe/buffer-empty Delay Time tSBE ns100 —120 — Write/buffer-full Delay Time tWBF ns— 300— 400 tWI ns— 300— 400 Write/interrupt-off Delay Time ns Time Output Delay Time Low tTL ns— 300— 400 Time Output Delay Time High tTH ns— 300— 400 tRDE ns— 300— 400 Read/data Buse Enable Delay Time Timer Cycle Time tCYC ns10 —10 — tr, tf ns320 —320 — Timer Input Rise and Fall Times Timer Input Low Level Time t1 ns—8 0— 80 ns40 —80 — Timer Input High Level Time WRITE to TIMER-IN for writes which start counting tWT ns70 —120 — tTW ns200 —200 — TIMER-IN to WRITE for writes which start counting ns0—0 — Note: Timings are measured wth V L = 0.8 V and VH = 2.2 V for both input and output.

¡ Semiconductor MSM81C55-5RS/GS/JS TIMING DIAGRAM Read Cycle CE tAD Address Data Valid tAL tLA tLL tLC tCC tRV tCL tRDE tRDF tRD IO/M AD0 - 7 ALE RD CE tAL tLA tLL tCC tRV tWD IO/M AD0 - 7 ALE WR tLC tDW tCL Address Data Valid Write Cycle

¡ Semiconductor MSM81C55-5RS/GS/JS Strobe Input Mode BF tSBF STROBE INTR RD Input Data From Port tSS tSI tPSS tPHS tRDI tRBE Strobe Output Mode BF tSBE tWBF tWI tWP tSI STROBE INTR WR Output Data To Port

¡ Semiconductor MSM81C55-5RS/GS/JS Basic Input Mode RD tPR tRP Port Input Data Bus 1234512 5 TIMER IN tr tf t1 tCYC tTL tTH tTL tTH TIMER OUT (Pulse) TIMER OUT (Square Wave) Load Counter From Count Length Register Load Counter From Count Length Register Count Down(5fi 1) (Note) (T.C) (Note) Note: Periodically outut according to the output mode (m1=1) programming contents. Timer Waveforms 1 WR tWP Data Bus Port Output Note: The DATA BUS timing is the same as the read and write cycles. Basic Output Mode

¡ Semiconductor MSM81C55-5RS/GS/JS Timer Waveforms 2 RAM DATA HOLD CHARACTERISTICS AT LOW SUPPLY VOLTAGE WR tTW tWT TIMER IN Timer - Start 5 V tSU tR tLA tAL 4.5 V VCCH ALE 0.8 V 0 V 2.2 V CE VCCH Standby ModeVCC Two ways to place device in standby mode: (1) Method using CE Min. Typ. Data Holding Supply Voltage V CCH 2.0 — V Data Holding Supply Current I CCH VIN = 0 V or VCC, ALE = 0 V VCC = VCCH, ALE = 0 VIN = 0 V or VCC — 0.05 mA SpecificationItem UnitSymbol Condition Setup Time t SU 30 — ns Hold Time t R 20 — Max. —n s

¡ Semiconductor MSM81C55-5RS/GS/JS (2) Method using RESET VCC tSU Standby Mode tR 5 V 4.5 V 2.2 V VCCH GND RESET Note: In this case, the C/S register is reset, the port is set into the input mode, and the timer stops. PIN FUNCTION RESET A high level input to this pin resets the chip, places all three I/O ports in the input mode, resets all output latches and stops timer. Symbol Function AD0 - 7 Three-state, bi-directional address/data bus. Eight-bit address information on this bus is read into the internal address latch at the negative going edge of the ALE. Eight bits of data can be read from or written to the chip using this bus depending on the state of the WRITE or READ input. ALE Negative going edge of the ALE (Address Latch Enable) input latches AD 0 - 7, IO/M, and CE signals into the respective latches. CE When the CE input is high, both read and write operations to the chip are disabled. IO/M A high level input to this pin selects the internal I/O functions, and a low level selects the memory. RD If this pin is low, data from either the memory or ports is read onto the AD0 - 7 lines depending on the state of the IO/M line. TIMER OUT Timer output. When the present count is reached during timer operation, this pin provides a square-wave or pulse output depending on the programmed control status. WR If this pin is low, data on lines AD0 - 7 is written into either the memory or into the selected port depending on the state of the line IO/M line. PA0 - 7 (PB0 - 7) General-purpose I/O pins. Input/output directions can be determined by programming the command/ status (C/S) register. PC0 - 5 Three pins are usable either as general-purpose I/O pins or control pins for the PA and PB ports. When used as control pins, they are assigned to the following functions: PC 0: A INTR (port A interrupt) PC1: A BF (port A full) PC2: A STB (port A strobe) PC3: B INTR (port B interrupt) PC4: B BF (port B buffer full) PC5: B STB (port B strobe) TIMER IN Input to the counter/timer VCC 3–6V power supply GND GND

¡ Semiconductor MSM81C55-5RS/GS/JS OPERATION

Description

The MSM81C55-5 has three functions as described below.

• 2K-bit static RAM (256 words · 8 bits)
• Two 8-bit I/O ports (PA and PB) and a 6-bit I/O port (PC)
• 14-bit timer counter The internal register is shown in the figure below, and the I/O addresses are described in the table below.

8 Bit Internal Data Bus

6 Bit

8 Bit

• /CR I/O Address Selecting Register
• /CR
• /CR
• /CR
• /CR
• /CR Internal command/status register Universal I/O port A (PA) Universal I/O port B (PB) I/O port C (PC) Timer count lower position 8 bits (LSB) Timer count upper position 6 bits and timer mode 2 bits (MSB)
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• /CR
• : Don't care.

¡ Semiconductor MSM81C55-5RS/GS/JS (1) Programming the Command/Status (C/S) Register The contents of the command register can be written during an I/O cycle by addressing it with an I/O address of xxxxx000. Bit assignments for the register are shown below: TM2 TM1 IEB IEA PC2 PC1 PB PA Definition of PA0 - 7 0= Input Definition of PB0 - 7 1= Output Definition of PC0 - 5 00=ALT1 11=ALT2 01=ALT3 10=ALT4 See the port control assignment table. Port A Interrupt Enable 1 = Enabled Port B Interrupt Enable 0 = Disabled Timer Command 00 = NOP : Does not affect counter operations. 01 = STOP : Stops the timer if it is runnning. NOP if the timer is not runnning. 10 = STOP AFTER TC : Stops the timer when it reaches TC. NOP if the timer is not running. 11 = START : If the timer is not running, loads the mode and the count length, and immediately starts timer operation. If the timer is running, loads a new mode and the count length, and starts timer operation immediately after TC is reached. 76543210 Pin PC0 PC1 PC2 PC3 PC4 PC5 ALT1 Input port Input port Input port Input port Input port Input port ALT2 Output port Output port Output port Output port Output port Output port ALT3 A INTR A BF A STB Output port Output port Output port ALT4 A INTR A BF A STB B INTR B BF B STB Port Control Assignment Table

¡ Semiconductor MSM81C55-5RS/GS/JS (2) Reading the C/S Register The I/O and timer status can be accessed by reading the contents of the Status register located at I/O address xxxxx000. The status word format is shown below: (3) PA and PB Registers These registers may be used as either input or output ports depending on the programmed contents of the C/S register. They may also be used either in the basic mode or in the strobe mode. I/O address of the PA register: xxxxx001 I/O address of the PB register: xxxxx010 (4) PC Register The PC register may be used as an input port, output port or control register depending on the programmed contents of the C/S register. The I/O address of the PC register is xxxxx011. (5) Timer The timer is a 14-bit down counter which counts TIMER IN pulses. The low order byte of the timer register has an I/O address of xxxxx100, and the high order byte of the register has an I/O address of xxxxx101. The count length register (CLR) may be preset with two bytes of data. Bits 0 through 13 are assigned to the count length and bits 14 and 15 specify the timer output mode. A read operation of the CLR reads the contents of the counter and the pertinent output mode. The initial value range which can initially be loaded into the counter is 2 through 3FFF hex. Bit assignments to the timer counter and possible output modes are shown in the following. INTR A Port A Interrupt Request AD0 A BF Port A Buffer Full AD1 INTE A AD2 INTR B AD3 B BF AD4 INTE B AD5 TIMER AD6AD7 Port A Interrupt Enable Port B Interrupt Request Port B Buffer Full Port B Interrupt Enable Timer Interrupt. This bit is set high when the timer reaches TC, and is reset when the C/S register is read or a hardware reset occurs. M2 M1 T13 T12 T11 T10 T9 T8 Output Mode High Order 6 Bits of Count Length T7 T6 T5 T4 T3 T2 T1 T0 Low Order Byte of Count Length

¡ Semiconductor MSM81C55-5RS/GS/JS M2 M1 0 0 Outputs a low-level signal in the latter half (Note 1) of a count period. 0 1 Outputs a low-level signal in the latter half of a count period, automatically loads the programmed count length, and restarts counting when the TC value is reached. 1 0 Outputs a pulse when the TC value is reached. 1 1 Outputs a pulse each time the preset TC value is reached, automatically loads the programmed count length, and restarts from the beginning. Notes: 1. When counting an asymmetrical value such as (9), a high level is output during the first period of five,and a low level is output during the second period of four. 2. If an internal counter of the MSM81C55-5 receives a reset signal, count operation stops but the counter is not set to a specific initial value or output mode. When restarting count operation after reset, the START command must be executed again through the C/S register. Note that while the counter is counting, you may load a new count and mode into the CLR. Before the new count and mode will be used by the counter, you must issue a START command to the counter. Please note the timer circuit on the MSM81C55-5 is designed to be a square-wave timer, not a event counter. To achieve this, it counts down by twos twice in completing one cycle. Thus, its registers do not contain values directly representing the number of TIMER IN pulse received. After the timer has started counting down, the values residing in the count registers can be used to calculate the actual number of TIMER IN pulse required to complete the timer cycle if desired. To obtain the remaining count, perform the following operations in order. 1. STOP the counter 2. Read in the 16-bit value from the count registers. 3. Reset the upper two mode bits 4. Reset the carry and rotate right one position all 16 bits through carry 5. If carry is set, add 1/2 of the full original count (1/2 full count-1 if full count is odd). Note: If you started with an odd count and you read the count registers before the third count pulse occurs, you will not be able to recognize whether one or two counts have occurred. Regardless of this, the MSM81C55- 5 always counts out the right number of pulses in generating the TIMER OUT waveforms. 55 34 2 (TC) 53 42 (TC) 534 Start Start n=5 (Square Wave) (Pulse) n=4 (Square Wave) (Pulse) TIMER-IN WR TIMER-OUT TIMER-OUT WR TIMER-OUT TIMER-OUT Note: n is the value set in the CLR. Figures in the diagram refer to counter values

¡ Semiconductor MSM81C55-5RS/GS/JS (6) Standby Mode (see page 7) The MSM81C55-5 is placed in standby mode when the high level at the CE input is latched during the negative going edge of ALE. All input ports and the timer input should be pulled up or down to either V CC or GND potential. When using battery back-up, all ports should be set low or in input port mode. The timer output should be set low. Otherwise, a buffer should be added to the timer output and the battery should be connected to the power supply pins of the buffer. By setting the reset input to a high level, the standby mode can be selected. In this case, the command register is reset, so the ports automatically set to the input mode and the timer stops.

¡ Semiconductor MSM81C55-5RS/GS/JS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Low-speed device (Old) Remarks M80C85AH M80C85A/M80C85A-2 8bit MPU M80C86A-10 M80C86A/M80C86A-2 16bit MPU M80C88A-10 M80C88A/M80C88A-2 8bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M81C55 RAM.I/O, timer M82C37B-5 M82C37A/M82C37A-5 DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C53-5 Timer M82C55A-2 M82C55A-5 PPI

¡ Semiconductor MSM81C55-5RS/GS/JS Differences between MSM81C55-5 and MSM81C55 1) Manufacturing Process These devices use a 3 m Si-CMOS. 2) Design These devices use the same chip. However, different outgoing inspection standards are used for these devices separately. 3) Electrical Characteristics ''Oki's '96 Data Book for MICROCONTROLLER'' describes that the MSM81C55-5 satisfies the electrical characteristics of the MSM81C55. As shown above, the devices can be replaced without any trouble.

¡ Semiconductor MSM81C55-5RS/GS/JS (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.

¡ Semiconductor MSM81C55-5RS/GS/JS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFJ44-P-S650-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Mirror finish

¡ Semiconductor MSM81C55-5RS/GS/JS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. QFP44-P-910-0.80-2K Mirror finish