MSM80C86A-10RS OKI | Alldatasheet

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¡ Semiconductor MSM80C86A-10RS/GS/JS GENERAL DESCRIPTION The MSM80C86A-10 is complete 16-bit CPUs implemented in Silicon Gate CMOS technology. They are designed with same processing speed as the NMOS 8086-1 but have considerably less power consumption. It is directly compatible with MSM80C88A-10 software and MSM80C85AH hardware and peripherals.

FEATURES

  • 1 Mbyte Direct Addressable Memory Space
  • Internal 14-word by 16-bit Register Set
  • 24-Operand Addressing Modes
  • Bit, Byte, Word and String Operations
  • 8 and 16-bit Signed and Unsigned Arithmetic Operation
  • From DC to 10 MHz Clock Rate (Note)
  • Low Power Dissipation 10 mA/MHz
  • Bus Hold Circuitry Eliminated Pull-up Resistors
  • 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM80C86A-10RS)
  • 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM80C86A-10JS)
  • 56-pin Plastic QFP (QFP56-P-1519-1.00-K): (Product name: MSM80C86A-10GS-K) (Note) 10 MHz Spec is not compatible with Intel 8086-1 Spec. ¡ Semiconductor MSM80C86A-10RS/GS/JS 16-Bit CMOS MICROPROCESSOR E2O0010-27-X2 This version: Jan. 1998 Previous version: Aug. 1996

¡ Semiconductor MSM80C86A-10RS/GS/JS CIRCUIT CONFIGURATION BHE/S7 Exeuction Unit Register File Relocation Register File Data Pointer and Index Registers (8 Words) Segment Registers and Instruction Pointer (5 Words) 16-Bit ALU Flags Bus Interface Unit AD15 - AD0 INTA, RD, WR, M/IO DT/R, DEN, ALE 6Byte Instruction Queue LOCK QS0, QS1 S2, S1, S0 GND VCC MN/MXREADYRESETCLK TEST INTR NMI RQ/GT0, 1 HOLD HLDA

2 Control & Timing

¡ Semiconductor MSM80C86A-10RS/GS/JS PIN CONFIGURATION (TOP VIEW) 40 pin Plastic DIP GND GND RESET AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT 0(HOLD) RQ/GT1(HLDA) LOCK(WR) S2(M/IO) S1(DT/R) S0(DEN) QS0(ALE) QS1(INTA) TEST READY V CC NMI INTR CLK AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD14 AD13 AD12 AD11 AD10 NC RQ/GT0(HOLD) NC NC A 19/S6 BHE/S7 MN/MX RD NC RQ/GT1(HLDA) LOCK(WR) S 2(M/IO) S1(DT/R) S0(DEN) NC AD AD9 AD8 AD7 AD6 NC NC AD AD4 AD3 AD2 AD1 AD0 56 pin Plastic QFP NC A 19/S6 BHE/S7 MN/MX RD RQ/GT 0(HOLD) RQ/GT1(HLDA) AD10 AD9 AD8 AD7 AD6 AD5 AD4 NC NM1 INTR CLK GND NC RESET AD AD12 AD13 AD14 GND NC LOCK(WR) S 2(M/IO) S1(DT/R) AD3 AD2 AD1 AD0 17 S 0(DEN) VCC READY TEST INTA(QS ALE(QS0) AD A16/S3 A17/S4 A18/S5 44 pin Plastic QFJ AD11

55 AD12

54 AD13

53 AD14

51 GND

49 VCC

48 VCC

46 AD15

45 A16/S3

44 A17/S4

43 A18/S5

27QS1(INTA) 28QS0(ALE)

¡ Semiconductor MSM80C86A-10RS/GS/JS ABSOLUTE MAXIMUM RATINGS MSM80C86A-10GS –65 to +150 MSM80C86A-10RS Power Supply Voltage VCC –0.5 to + 7 V Input Voltage VIN –0.5 to VCC +0.5 V Output Voltage VOUT –0.5 to VCC +0.5 V Storage Temperature TSTG °C Power Dissipation PD 0.7 W Parameter UnitSymbol With respect to GND Ta = 25°C Conditions Rating MSM80C86A-10JS 1.0 OPERATING RANGE Range Power Supply Voltage VCC 4.75 to 5.25 V Operating Temperature Top 0 to +70 °C Parameter UnitSymbol RECOMMENDED OPERATING CONDITIONS Typ. Power Supply Voltage VCC 5.0 V TOP +25 "L" Input Voltage V IL VIH "H" Input Voltage *1 — Min. 4.75 –0.5 VCC –0.8 Max. 5.25 +70 +0.8 VCC +0.5 Parameter UnitSymbol V V *2 — 2.0 V CC +0.5 V Operating Temperature *1 Only CLK *2 Except CLK

¡ Semiconductor MSM80C86A-10RS/GS/JS DC CHARACTERISTICS Max. "L" Output Voltage V OL 0.4 V "H" Output Voltage V OH ——V Parameter Unit Symbol Min. 3.0 VCC –0.4 IOL = 2.5 mA IOH = –2.5 mA IOH = –100 mA Conditions Input Leak Current I LI +1.0 mA Output Leak Current I LO +10 mA –1.0 –10 0 £ VIN £ VCC VO = VCC or GND Typ. Input Leakage Current (Bus Hold Low) IBHL 400 mA50 VIN = 0.8 V Input Leakage Current (Bus Hold High) IBHH –400 mA–50 VIN = 3.0 V Bus Hold Low Overdrive IBHLO 600 mA— *5 Bus Hold High Overdrive IBHHO –600 mA— *6 Operating Power Supply Current ICC 10 Standby Power Supply Current ICCS 500 VIL = GND VIH = VCC VCC = 5.5 V Outputs Unloaded VIN = VCC or GND mA/MHz mA Input Capacitance C IN 10 pF Output Capacitance C OUT 15 pF I/O Capacitance C I/O 20 pF *7— (VCC = 4.5 to 5.5 V, Ta = –40°C to +85°C) *3 Test condition is to lower V IN to GND and then raise VIN to 0.8 V on pins 2-16, and 35-39. *4 Test condition is to raise V IN to VCC and then lower VIN to 3.0 V on pins 2-16, 26-32, and 34- 39. *5 An external driver must source at least I BHLO to switch this node from LOW to HIGH. *6 An external driver must sink at least I BHHO to switch this node from HIGH to LOW. *7 Test Conditions: a) Freq = 1 MHz. b) Unmeasured Pins at GND. c) V IN at 5.0 V or GND.

¡ Semiconductor MSM80C86A-10RS/GS/JS AC CHARACTERISTICS Minimum Mode System Timing Requirements Parameter Symbol Unit Max.Min. 10 MHz Spec. VCC = 4.75 V to 5.25 V Ta = 0 to +70°C Data in Setup Time tDVCL 20 — ns Data in Hold Time tCLDX 10 — ns Max.Min. 8 MHz Spec. VCC = 4.75 V to 5.25 V Ta = 0 to +70°C 20 — 10 — Max.Min. 5 MHz Spec. VCC = 4.5 V to 5.5 V Ta = –40 to +85°C 30 — 10 — CLK Rise Time (From 1.0 V to 3.5 V) tCH1CH2 —1 0 n s—1 0— 10 CLK Fall Time (From 3.5 V to 1.0 V) tCL2CL1 —1 0 n s—1 0— 10 CLK Cycle Period tCLCL 100 DC ns CLK Low Time tCLCH 46 — ns CLK High Time tCHCL 44 — ns 125 DC 68 — 44 — 200 DC 118 — 69 — READY Setup Time into MSM80C86A-2 t RYHCH 46 — ns READY Hold Time into MSM80C86A-10 tCHRYX 20 — ns 68 — 20 — 118 — 30 — RDY Setup Time into MSM 82C84A-2 (See Notes 1, 2) tR1VCL 35 — ns35 —35 — RDY Hold Time into MSM 82C84A-2 (See Notes 1, 2) tCLR1X 0— n s0—0 — HOLD Setup Time tHVCH 20 — ns20 —35 — READY inactive to CLK (See Note 3) tRYLCL –8 — n s–8 —–8 — tIHIL —1 5 n s—1 5— 15 INTR, NMI, TEST Setup Time (See Note 2) tINVCH 15 — ns15 —30 — Input Rise Time (Except CLK) (From 0.8 V to 2.0 V) tILIH —1 5 n s—1 5— 15 Input Fall Time (Except CLK) (From 2.0 V to 0.8 V)

¡ Semiconductor MSM80C86A-10RS/GS/JS Timing Responses Parameter Symbol Unit Max.Min. 10 MHz Spec. VCC = 4.75 V to 5.25 V Ta = 0 to +70°C Max.Min. 8 MHz Spec. VCC = 4.75 V to 5.25 V Ta = 0 to +70°C Max.Min. 5 MHz Spec. VCC = 4.5 V to 5.5 V Ta = -40 to +85°C Address Valid Delay tCLAV 10 60 ns Address Hold Time tCLAX 10 — ns Address Float Delay tCLAZ tCLAX 50 ns 10 60 10 — tCLAX 50 10 110 10 — tCLAX 80 ALE Width tLHLL tCLCH-10 — nstCLCH-10 —tCLCH-20 — ALE Active Delay tCLLH —4 0 n s—5 0— 80 ALE Inactive Delay tCHLL —4 5 n s—5 5— 85 Address Hold Time to ALE Inactive tLLAX tCLCH-10 —n stCLCH-10 —tCLCH-10 — Data Valid Delay tCLDV 10 60 ns10 6010 110 Data Hold Time tCHDX 10 — ns10 —10 — Data Hold Time after WR tWHDX tCLCH-25 — nstCLCH-30 —tCLCH-30 — Control Active Delay 1 tCVCTV 10 55 ns10 7010 110 Control Active Delay 2 tCHCTV 10 50 ns10 6010 110 Control Inactive Delay tCVCTX 10 55 ns10 7010 110 Address Float to RD Active tAZRL 0— n s0—0 — RD Active Delay tCLRL 10 70 ns10 10010 165 RD Inactive Delay tCLRH 10 60 ns RD Inactive to Next Address Active tRHAV tCLCL-35 — ns HLDA Valid Delay tCLHAV 10 60 ns 10 80 tCLCH-40 — 10 100 10 150 tCLC-45 — 10 160 RD Width tRLRH 2tCLCL-40 — ns2tCLCL-50 —2tCLCL-75 — WR Width tWLWH 2tCLCL-35 — ns2tCLCL-40 —2tCLCL-60 — Address Valid to ALE Low tAVAL tCLCH-35 — nstCLCH-40 —tCLCH-60 — Ouput Rise Time (From 0.8 V to 2.0 V) tOLOH —1 5 n s—1 5— 15 Output Fall Time (From 2.0 V to 0.8 V) tOHOL —1 5 n s—1 5— 15 Notes: 1. Signal at MSM82C84A-2 or MSM82C88-2 are shown for reference only. 2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 3. Applies only to T2 state. (8 ns into T3)

¡ Semiconductor MSM80C86A-10RS/GS/JS Maximum Mode System (Using MSM82C88-2 Bus Controller) Timing Requirements Parameter Symbol Unit Max.Min. 10 MHz Spec. VCC = 4.75 V to 5.25 V Ta = 0 to +70°C Data in Setup Time tDVCL 20 — ns Data in Hold Time tCLDX 10 — ns Max.Min. 8 MHz Spec. VCC = 4.75 V to 5.25 V Ta = 0 to +70°C 20 — 10 — Max.Min. 5 MHz Spec. VCC = 4.5 V to 5.5 V Ta = –40 to +85°C 30 — 10 — CLK Rise Time (From 1.0 V to 3.5 V) tCH1CH2 —1 0 n s—1 0— 10 CLK Fall Time (From 3.5 V to 1.0 V) tCL2CL1 —1 0 n s—1 0— 10 CLK Cycle Period tCLCL 100 DC ns CLK Low Time tCLCH 46 — ns CLK High Time tCHCL 44 — ns 125 DC 68 — 44 — 200 DC 118 — 69 — READY Setup Time into MSM80C86A-10 t RYHCH 46 — ns READY Hold Time into MSM80C86A-10 tCHRYX 20 — ns 68 — 20 — 118 — 30 — RDY Setup Time into MSM 82C84A-2 (See Notes 1, 2) tR1VCL 35 — ns35 —35 — RDY Hold Time into MSM 82C84A-2 (See Notes 1, 2) tCLR1X 0— n s0—0 — READY inactive to CLK (See Note 3) tRYLCL –8 — ns–8 —–8 — tIHIL —1 5 n s—1 5— 15 Input Rise Time (Except CLK) (From 0.8 V to 2.0 V) tILIH —1 5 n s—1 5— 15 Input Fall Time (Except CLK) (From 2.0 V to 0.8 V) RQ/GT Setup Time tGVCH 15 — ns15 —30 — RQ Hold Time into MSM80C86A-10 tCHGX 20 — ns30 —40 — Setup Time for Recognition (NMI, INTR, TEST) (See Note 2) tINVCH 15 — ns15 —30 —

¡ Semiconductor MSM80C86A-10RS/GS/JS Timing Responses tCVNV Timing Response Parameter Symbol Unit Max.Min. 10 MHz Spec. VCC = 4.75 V to 5.25 V Ta = 0 to +70°C Max.Min. 8 MHz Spec. VCC = 4.75 V to 5.25 V Ta = 0 to +70°C Max.Min. 5 MHz Spec. VCC = 4.5 V to 5.5 V Ta = –40 to +85°C Command Active Delay (See Note 1) tCLML 53 5 n s Command Inactive Delay (See Note 1) tCLMH 54 5 n s READY Active to Status Passive (See Note 4) tRYHSH —4 5 n s 53 5 54 5 —6 5 5 45 5 45 — 110 Status Inactive Delay Status Active Delay tCHSV 10 45 ns10 6010 110 Address Valid Delay tCLSH 10 60 ns10 7010 130 Address Hold Time tCLAV 10 60 ns10 6010 110 Address Float Delay tCLAX 10 — ns10 —10 — Status Valid to ALE High (See Note 1) tCLAZ tCLAX 50 nstCLAX 50tCLAX 80 Status Valid to MCE High (See Note 1) tSVLH —2 5 n s—2 5— 35 CLK Low to ALE Valid (See Note 1) tSVMCH —3 0 n s—3 0— 35 CLK Low to MCE High (See Note 1) tCLLH —2 5 n s—2 5— 35 ALE Inactive Delay (See Note 1) tCLMCH —2 5 n s—2 5— 35 Data Valid Delay tCHLL 42 5 n s42 54 35 Data Hold Time tCLDV 10 60 ns10 6010 110 tCHDX 10 — ns10 —10 — Control Active Delay (See Note 1) 5 45 ns Control Inactive Delay (See Note 1) tCVNX 54 5 n s 54 5 54 5 5 45 5 45 RD Active Delay Address Float to RD Active tAZRL 0— n s0—0 — RD Inactive Delay tCLRL 10 70 ns10 10010 165 RD Inactive to Next Address Active tCLRH 10 60 ns10 8010 150 tRHAV tCLCL-35 —n stCLCL-40 —tCLCL-45 — tCHDTL —5 0 n s—5 0— 50 GT Active Delay (See Note 5) GT Inactive Delay tCLGL 04 5 n s05 00 85 RD Width tCLGH 04 5 n s05 00 85 Output Rise Time (From 0.8 V to 2.0 V) tRLRH 2tCLCL-40 —n s2tCLCL-50 —2tCLCL-75 — Output Fall Time (From 2.0 V to 0.8 V) tOLOH —1 5 n s—1 5— 15 tOHOL —1 5 n s—1 5— 15 Direction Control Active Delay (See Note 1) tCHDTH —3 0 n s—3 0— 35Direction Control Inactive Delay (See Note 1) Notes: 1. Signals at MSM82C84A-2 or MSM82C88-2 are shown for reference only. 2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK 3. Applies only to T2 state (8 ns into T3) 4. Applies only to T3 and wait states. 5. C L = 40 pF (RQ/GT0, RQ/GT1)

¡ Semiconductor MSM80C86A-10RS/GS/JS TIMING DIAGRAM Input/Output A.C. Testing Load Circuit Minimum Mode Test Points1.5 0.45 1.5 2.4 AC, Testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are 1.5 V for both a logic "1" and "0". CL = 100 pF CL includes jig capacitance. Device Under Test VIH VIL M/IO CLK (MSM82C84A-2 Output) ALE RDY (MSM82C84A-2 Input) See NOTE 5 READY (MSM80C86A-10 Input) (NOTE 1) (WR, INTA = VOH) AD15 - AD0 RD DT/R DEN tCHCTV tCHCL tCLCL tCH1CH2 tCL2CL1 T1 T2 T3 Tw tCLCH tCHDXtCLDVtCLAXtCLAV tCLLH tLHLL tLLAX tAVAL tCHLL tR1VCL BHE, A19 - A16 S7 - S3 tCLR1X tRYLCL tCHRYX tRYHCH tCLDXtDVCLtCLAZ tCLAX tLLAX tAVAL tCLAV AD15 - AD0 tAZRL tCHCTV tCLRL tCVCTV tCVCTX tRLRH tCHCTV tCLRH tRHAV Data In Float Read Cycle VIH VIL Float BHE/S7, A19/S6 - A16/S3

¡ Semiconductor MSM80C86A-10RS/GS/JS Minimum Mode (continued) VIH VIL M/IO BHE/S7, A19/S6 - A16/S3 ALE AD15 - AD0 DEN WR AD15 - AD0 DT/R INTA DEN (NOTE 1) (RD, INTA DT/R = VOH) (NOTES 1&3) (RD, WR = VOH BHE = VOL) CLK (MSM82C84A-2 Output) tCLCL tCHCTV tCHCL tCH1CH2 tCL2CL1 T1 T2 T3 T4TW tCLCH tCLAV tCLLH tCLAX tCLDV tCHDX BHE, A19 - A16 S7 - S3 tLHLL tLLAX tAVAL tCHLL tCLAV tCVCTV tLLAX tAVAL tCVCTV tWLWH tCLAZ tCHCTV tCVCTV tCVCTV tCVCTX tCLAV tCHCTV tCLDX tCVCTX tDVCL tCVCTX tCHDX tWIDX AD15 - AD0 Data Out FloatPointerFloat Invalid Address Software Halt RD, WR, INTA = VOH DT/R = Indeterminate INTA Cycle Write Cycle Software HaltAD15 - AD0 tCLDV tCLAX

¡ Semiconductor MSM80C86A-10RS/GS/JS Maximum Mode VIH VIL QS0, QS1 BHE/S7, A19/S6 - A16/S3 S2, S1, S0 (Except Halt) ALE (MSM82C88-2 Output) RDY (MSM82C84A-2 Input) See NOTE 5 READY (MSM80C86A-10 Input) Read Cycle AD 15 - AD0 RD MRDC or IORC DEN DT/R MSM82C88-2 Outputs (See NOTES 5, 6) tCLAV tCLCL tCH1CH2 tCL2CL1 Tw T1 T2 T3 T4 tCHCL tCLCH tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tSVLH tCLLH tCHLL tRYLCL tR1VCL tCLR1X tCHRYXtRYHSH tRYHCHtCLAZ tDVCL tRHAV tCHDTH tCLMH tCVNX tRLRH tCVNV tCLML tCLRLtCHDTL tCLAV tCLRH tCLDX tAZRL BHE A19 - A16 (See NOTE 8) Data In FloatAD15 - AD0 S7 - S3 Float VIH VIL tCLAX CLK (MSM82C84A-2 Output)

¡ Semiconductor MSM80C86A-10RS/GS/JS Maximum Mode (continued) /#06/#07 VIH VIL AD15 - AD0 AD15 - AD0 See NOTE 3, 4 CLK (MSM82C84A-2 Output) S2, S1, S0 (Except Halt) MSM82C88-2 Outputs See NOTES 5, 6 MSM82C88-2 Outputs See NOTES 5, 6 INTA Cycle tCHSV DEN AMWC or AIOWC MWTC or IOWC MCE/ PDEN DT/R INTA DEN Write Cycle AD15 - AD0 S2, S1, S0 Software Halt (DEN = VOL; RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA = VOH) tCLAV tCLSH tCLAX tCLDV tCVNX tCLML tCLMH tCLML tCLMH tDVCL tCLDX tCHDTH tCLMH tCVNX tCVNV tCLAV tCLML tCHDTLtCLMCH tSVMCH tCVNX tCLAZ tCVNV Data (See NOTE 8) Pointer Float Float Float T2 T3 Tw Invalid Address tCHDX Float Notes: 1. All signals switch between V OH and VOL unless otherwise specified. 2. RDY is sampled near the end of T2, T3, T W to determine if T W machines states are to be inserted. 3. Cascade address is valid between first and second INTA cycle. 4. Two INTA cycles run back-to-back. The MSM80C86A-10 LOCAL ADDR/ DATA BUS is floating during both INTA cycles. Control for pointer address is shown for second INTA cycle. 5. Signals at MSM82C84A-2 or MSM82C88-2 are shown for reference only. 6. The issuance of the MSM 82C88-2 command and control signals ( MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high MSM82C88-2 CEN. 7. All timing measurements are made at 1.5 V unless otherwise noted. 8. Status inactive in state just prior to T4

¡ Semiconductor MSM80C86A-10RS/GS/JS Asynchronous Signal Recognition CLK Signal NMI INTR TEST tINVCH (See NOTE 1) NOTE: 1 Setup requirements for asynchronous signals only to guarantee recognition at next CLK Hold/Hold Acknowledge Timing (Minimum Mode Only) Request/Grant Sequence Timing (Maximum Mode Only) Bus Lock Signal Timing (Maximum Mode Only) Reset Timing CLK LOCK tCLAV Any CLK Cycle Any CLK Cycle tCLAV CLK HOLD AD15 - AD0, A19/S6 - A16/S3, RD, BHE/S7, M/IO DT/R, WR, DEN HLDA MSM80C86A-10 Coprocessor MSM80C86A-10 ‡ 1 CLK Cycle 1 or 2 Cycles tHVCH tHVCH tCLHAV tCLHAV tCLAZ ‡ 50msec tDVCL CLK tCLDX Reset VCC ‡ 4 CLK Cycles Any CLK Cycle CLK RQ/GT AD15 - AD0 A19/S6 - A16/S3 S2, S1, S0, RD, CLOCK BHE/S7 tCLGH ‡ tCLCL tGVCH tCHGX tCLGL ‡ tCLCL tCLGH tCLAZ Pulse 3 Coprocessor ReleaseMSM80C86A-10 Coprocessor MSM80C86A-10 (See NOTE 1) NOTE: 1 The co processor may not drive the buses outside the region shown without risking contention. Pulse 1 Coprocessor RQ Pulse 2 80C86AGT > 0 CLK Cycle

¡ Semiconductor MSM80C86A-10RS/GS/JS PIN DESCRIPTION AD0 - AD15 ADDRESS DATA BUS: Input/Output These lines are the multiplexed address and data bus. These are the address bus at the T1 cycle and the data bus at the T2, T3, TW and T4 cycles. At the T1 cycle, AD 0 low indicates Data Bus Low (D 0-D7) Enable. These lines are high impedance during interrupt acknowledge and hold acknowledge. A16/S3. A17/S4, A18/S5, A19/S6 ADDRESS/STATUS: Output These are the four most significant addresses, at the T1 cycle. Accessing I/O port address, these are low at T1 cycles. These lines are Status lines at T2, T3, TW and T4 cycles. S 3 and S4 are encoded as shown. These lines are high impedance during hold acknowledge. BHE/S7 BUS HIGH ENABLE/STATUS: Output This line indicates Data Bus High Enable (BHE) at the T1 cycle. This line is status line at T2, T3, TW and T4 cycles. RD READ: Output This line indicates that CPU is in the memory or I/O read cycle. This line is the read strobe signal when CPU read data from memory or I/O device. This line is active low. This line is high impedance during hold acknowledge. READY READY:Input This line indicates to the CPU that the addressed memory or I/O device is ready to read or write. This line is active high. If the setup and hold time is out of specification, illegal operation will occur. INTR INTERRUPT REQUEST: Input This line is the level triggered interrupt request signal which is sampled during the last clock cycle of instruction and string manipulation. It can be internally masked by software. This signal is active high and internally synchronized. Stack

0 Alternate Data

¡ Semiconductor MSM80C86A-10RS/GS/JS INTA INTERRUPT ACKNOWLEDGE: Output This line is a read strobe signal for the interrupt acknowledge cycle. This line is active low. TEST TEST: Input This line is examined by the WAIT instruction. When TEST is high, the CPU enters idle cycle. When TEST is low, the CPU exits the idle cycle. NMI NON MASKABLE INTERRUPT: Input This line causes a type 2 interrupt. NMI is not maskable. This signal is internally synchronized and needs 2-clock cycles of pulse width. RESET RESET:Input This signal causes the CPU to initialize immediately. This signal is active high and must be at least four clock cycles. CLK CLOCK: Input This signal provides the basic timing for the internal circuit. MN/MX MINIMUM/MAXIMUM: Input This signal selects the CPU’s operating mode. When V CC is connected, the CPU operates in Minimum mode. When GND is connected, the CPU operates in Maximum mode. VCC VCC: +5V supplied. GND GROUND The following pin function descriptions are maximum mode only. Other pin functions are already described. SO, S1, S2 STATUS: Output These lines indicate bus status and they are used by the MSM82C88-2 Bus Controller to generate all memory and I/O access control signals. These lines are high impedance during hold acknowledge. These status lines are encoded as shown.

¡ Semiconductor MSM80C86A-10RS/GS/JS RQ/GT0 RQ/GT1 REQUEST/GRANT:Input/Output These lines are used for Bus Request from other devices and Bus GRANT to other devices. These lines are bidirectional and active low. LOCK LOCK:Output This line is active low. When this line is low, other devices cannot gain control of the bus. This line is high impedance during hold acknowledge. QS 0/QS1 QUEUE STATUS: Output These lines are Queue Status, and indicate internal instruction queue status. Read I/O Port 0 (LOW) Interrupt acknowledge S1 Characteristics Write I/O Port Halt Read Memory 1 (HIGH) Code Access Write Memory Passive The following pin function descriptions are minimum mode only. Other pin functions are already described. M/IO STATUS: Output This line selects memory address space or I/O address space. When this line is high, the CPU selects memory address space and when it is low, the CPU selects I/O address space. This line is high impedance during hold acknowledge. WR WRITE: Output This line indicates that the CPU is in the memory or I/O write cycle. This line is a write strobe signal when the CPU writes data to memory of I/O device. This line is active low. This line is high impedance during hold acknowledge. 1 (HIGH) First Byte of Op Code from Queue 0 (LOW) No operation QS1 QS0 Characteristics Empty the Queue Subsequent Byte from Queue

¡ Semiconductor MSM80C86A-10RS/GS/JS INTA INTERRUPT ACKNOWLEDGE: Output This line is a read strobe signal for the interrupt acknowledge cycle. This line is active low. ALE ADDRESS LATCH ENABLE: Output This line is used for latching the address into the MSM82C12 address latch. It is a positive pulse and its trailing edge is used to strobe the address. This line is never floated. DT/R DATA TRANSMIT/RECEIVE: Output This line is used to control the output enable of the bus transceiver. When this line is high, the CPU transmits data, and when it is low. the CPU receives data. This line is high impedance during hold acknowledge. DEN DATA ENABLE: Output This line is used to control the output enable of the bus transceiver. This line is active low. This line is high impedance during hold acknowledge. HOLD HOLD REQUEST: Input This line is used for Bus Request from other devices. This line is active high. HLDA HOLD ACKNOWLEDGE: Output This line is used for Bus Grant other devices. This line is active high.

¡ Semiconductor MSM80C86A-10RS/GS/JS FUNCTIONAL DESCRIPTION STATIC OPERATION The MSM80C86A-10 circuitry is of static design. Internal registers, counters and latches are static and require no refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The MSM80C86A-10 can operate from DC to the appropriate upper frequency limit. The processor clock may be stopped in either state (high/low) and held there indefinitely. This type of operation is especially useful for system debug or power critical applications. The MSM80C86A-10 can be single stepped using only the CPU clock. This state can be maintained as long as is necessary. Single step clock operation allows simple interface circuitry to provide critical information for bringing up your system. Static design also allows very low frequency operation (down to DC). In a power critical situation, this can provide extremely low power operation since MSM80C86A-10 power dissipation is directly related to operating frequency. As the system frequency is reduced, so is the operating power until, ultimately, at a DC input frequency, MSM80C86A-10 power requirement is the standby current (500 mA maximum). General Operation The internal function of the MSM80C86A-10 consists of a Bus Interface Unit (BIU) and an Execution Unit (EU). These units operate mutually but perform as separate processors. BIU performs instruction fetch and queueing, operand fetch, DATA read and write address relocation and basic bus control. Instruction pre-fetch is performed while waiting for decording and execution of instructions. Thus, the CPU’s performance is increased. Up to 6-bytes of instructions stream can be queued. The EU receives pre-fetched instructions from the BIU queue, decodes and executes the instructions, and provides the un-relocated operand address to BIU. Memory Organization The MSM80C86A-10 has a 20-bit address to memory. Each address has an 8-bit data width. Memory is organized 00000H to FFFFFH and is logically divided into four segments: code, data, extra data and stack segment. Each segment contains up to 64 Kbytes and locates on a 16-byte boundary. (Fig. 3a) All memory references are made relative to the segment register which functions in accordance with a select rule. Word operands can be located on even or odd address boundary. The BIU automatically performs the proper number of memory accesses. Memory consists of an even address and an odd address. Byte data of even address is transferred on the AD 0-AD7 and byte data of odd address is transfered on the AD 8-AD15. The CPU provides two enable signals BHE and A0 to access either an odd address, even address or both: Memory location FFFF0H is the start address after reset, and 00000H through 003FFH are reserved as an interrupt pointer, where there are 256 types of interrupt pointers. Each interrupt type has a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset address.

¡ Semiconductor MSM80C86A-10RS/GS/JS Memory Organization Reserved Memory Locations CS SS DS ES Segment Register File XXXXOH Code Segment Stack Segment Data Segment Extra Data Segment FFFFFH OOOOH +Offset 64KB Reset Bootstrap Program Jump FFFFFH FFFFOH 3FFH 3FCH Interrupt Pointer for Type 1 Interrupt Pointer for Type 0 Interrupt Pointer for Type 255 Stack All stack pushes and pops. Memory references relative to BP base register except data references. Data references when relative to stack, destination of string operation, or explicitly overridden.Local Data External (Global Data) Destination of string operations: Explicitly selected using a segment overriden. STACK (CS) Instructions Automatic with all instruction prefetch.CODE (CS) Memory Reference Need Segment Selection RuleSegment Register Used DATA (DS) EXTRA (ES)

¡ Semiconductor MSM80C86A-10RS/GS/JS Minimum and Maximum Modes The MSM80C86A-10 has two system modes: minimum and maximum. When using maximum mode, it is easy to organize a multi-CPU system with a MSM82C88-2 Bus Controller which generates the bus control signal. When using minimum mode, it is easy to organize a simple system by generating bus control signal by itself. MN/MX is the mode select pin. Definition of 24-31 pin changes depend on the MN/ MX pin. Bus Operation The MSM80C86A-10 has a time multiplexed address and data bus. If a non-multiplexed bus is desired for a system, it is only to add the address latch. A CPU bus cycle consists of at least four clock cycles: T1, T2, T3 and T4. (Fig. 4) The address output occurs during T1 and data transfer occurs during T3 and T4. T2 is used for changing the direction of the bus at the read operation. When the device which is accessed by the CPU is not ready for The data transfer and the CPU “NOT READY”, TW cycles are inserted between T3 and T4. When a bus cycle is not needed, T1 cycles are inserted between the bus cycles for internal execution. During the T1 cycle, the ALE signal is output from the CPU or the MSM82C88-2 depending on MN/MX. At the trailing edge of ALE, a valid address may be latched. Status bits S 0, S1 and S2 are used in the maximum mode by the bus controller to recognize the type of bus operation according to the following table. Status bits S3 through S 7 are multiplexed with A 16 - A19, and BHE: therefore, they are valid during T2 through T4. S 3 and S 4 indicate which segment register was selected on the bus cycle, according to the following table. Read I/O 0 (LOW) Interrupt acknowledge S1 Characteristics Write I/O Halt Read Data from Memory 1 (HIGH) Instruciton Fetch Write Data to Memory Passive (no bus cycle) 1 (HIGH) Stack 0 (LOW) Alternate Data (Extra segment) S3 Characteristics Code or None Data I/O Addressing The MSM80C86A-10 has 64 Kbytes of I/O or as 32 Kwords I/O. When the CPU accesses an I/ O device, addresses AD0 - AD15 are in the same format as a memory address, and A16 - A19 are low. The I/O ports addresses are same as memory, so it is necessary to be careful when using 8-bit peripherals. S 5 indicates interrupt enable Flag.

¡ Semiconductor MSM80C86A-10RS/GS/JS Basic System Timing T1 T2 T3 TTWAIT T4T1 T2 T3 TTWAIT T4 (4 + N*WAIT) = TCY(4 + N*WAIT) = TCY GOES INACTIVE IN THE STATE JUST PRIOR TO T4 BHE, A19 - A16 BHE, A19 - A16 S7 - S3 S7 - S3 A15 - A0 D15 - D0BUS RESERVED FOR DATA IN VALID A15 - A0 Data Out (D15 - D0) READYREADY WAITWAIT MEMORY ACCESS TIME CLK ALE S2, S1, S0 ADDR/ STATUS RD, INTA ADDR/DATA READY DT/R DEN WR

¡ Semiconductor MSM80C86A-10RS/GS/JS EXTERNAL INTERFACE Reset CPU Initialization is executed by the RESET pin. The MSM80C86A-10’s RESET High signal is required for greater than 4 clock cycles. The Rising edge of RESET terminates present operation immediately. The Falling edge of RESET triggers an internal reset sequence for approximately 10 clock cycles. After the internal reset sequence is finished normal operation occurs from absolute location FFFF0H. Interrupt Operations Interrupt operation is classified as software or hardware, and hardware interrupt is classified as non-maskable or maskable. An interrupt causes a new program location defined on the interrupt pointer table, according to the interrupt type. Absolute locations 00000H through 003FFH are reserved for the interrupt pointer table. The interrupt pointer table consists of 256-elements. Each element is 4 bytes in size and corresponds to an 8-bit type number which is sent from an interrupt request device during the interrupt acknowledge cycle. Non-maskable Interrupt (NMI) The MSM80C86A-10 has a Non-maskable interrupt (NMI) which is of higher priority than the markable interrupt request (INTR). The NMI request pulse width needs a minimum of 2 clock cycles. The NMI will be serviced at the end of the current instruction or between string manipulations. Maskable Interrupt (INTR) The MSM80C86A-10 provides another interrupt request (INTR) which can be masked by software. INTR is level triggered, so it must be held until the interrupt request is acknowledged. INTR will be serviced at the end of the current instruction or between string manipulations. Interrupt Acknowledge Sequence ALE LOCK INTA AD0 - AD15 T1 T2 T3 T4 TI T1 T2 T3 T4 Type VectorFloat

¡ Semiconductor MSM80C86A-10RS/GS/JS Interrupt Acknowledge During the interrupt acknowledge sequence, further interrupts are disabled. The interrupt enable bit is reset by any interrupt, after which the Flag register is automatically pushed onto the stack. During the acknowledge sequence, the CPU emits the lock signal from T2 of the first bus cycle to T2 of the second bus cycle. At second bus cycles, byte is fetched from the external device as a vector which identified the type of interrupt. This vector is multiplied by four and used as a interrupt pointer address. (INTR only) The interrupt Return (IRET) instruction includes a Flag pop operation which returns the original interrupt enable bit when it restores the Flag. HALT When a Halt instruction is executed, the CPU enters the Halt state. An interrupt request or RESET will force the MSM80C86A-10 out of the Halt state. System Timing – Minimum Mode A bus cycle begins T1 with an ALE signal. The trailing edge of ALE is used to latch the address. From T1 to T4 the M/IO signal indicates a memory or I/O operation. From T2 to T4, the address data bus changes the address but to data bus. The read ( RD), write ( WR) and interrupt acknowledge ( INTA) signals causes the addressed device to enable data bus. These signal becomes active at the beginning of T2 and inactive at the beginning of T4. System Timing – Maximum Mode At maximum mode, the MSM82C88-2 Bus Controller is added to system. The CPU sends status information to the Bus Controller. Bus timing signals are generated by Bus Controller. Bus timing is almost the same as in the minimum mode.

¡ Semiconductor MSM80C86A-10RS/GS/JS MOV = Move: Register/memory to/from register Immediate to register/memory Immediatye to register Memory to accumulator Accumulator to memory Register/memory to segment register Segment register to register/memory w d reg w w w w mod mod mod mod reg data addr-low addr-low reg reg r/m r/m r/m r/m 7654 data data if w = 1 addr-high addr-high 3210 7654 data if w = 1 3210 PUSH = Push: Register/memory Register Segment register reg reg mod 110 r / m POP = Pop: Register/memory Register Segment register reg reg mod 000 r / m XCHG = Exchange: Register/memory with register Register with accumulator reg w mod reg r/m IN = Input from: Fixed port Variable port w w port OUT = Output to: Fixed port Variable port XLAT = Translate byte to AL LEA = Load EA to register LDS = Load pointer to DS LES = Load pointer to ES LAHF = Load AH with flags SAHF = Store AH into flags PUSHF = Push flags POPF = Pop flags w w mod mod mod reg reg reg r/m r/m r/m port DATA TRANSFER

¡ Semiconductor MSM80C86A-10RS/GS/JS ADD = Add: Reg./memory with register to either Immediate to register/memory Immediate to accumulator d s w w w mod mod 0 0 data reg r/m r/m data data if w = 1 data if s:w = 01 ADC = Add with carry: Reg./memory with register to either Immediate to register/memory Immediate to accumulator d s w w w mod mod 0 1 data reg r/m r/m data data if w = 1 data if s:w = 01 INC = Increment: Register/memory Register AAA = ASCII adjust for add DAA = Decimal adjust for add reg w mod 0 0 0 r/m SUB = Subtract: Reg./memory with register to either Immediate from register/memory Immediate from accumulator d s w w w mod mod 1 0 data reg r/m r/m data data if w = 1 data if s:w = 01 SBB = Subtract with borrow: Reg./memory with register to either Immediate from register/memory Immediate from accumulator d s w w w mod mod 0 1 data reg r/m r/m data data if w = 1 data if s:w = 01 DEC = Decrement: Register/memory Register NEG = Change sign reg w w mod mod r/m r/m CMP = Compare: Register/memory and register Immediate with register/memory Immediate with accumulator AAS = ASCII adjust for subtract d s w w w mod mod 1 1 data reg r/m r/m data data if w = 1 data if s:w = 01 ARITHMETIC

¡ Semiconductor MSM80C86A-10RS/GS/JS DAS = Decimal adjust for subtract MUL = Multiply (unsigned) IMUL = Integer multiply (signed) AAM = ASCII adjust for multiply DIV = Divide (unsigned) IDIV = Integer divide (signed) AAD = ASCII adjust for divide CBW = Convert byte to word CWD = Convert word to double word w w w w mod mod mod mod r/m r/m r/m r/m

¡ Semiconductor MSM80C86A-10RS/GS/JS NOT = Invert SHL/SAL = Shift logical/arithmetic left SHR = Shift logical right SAR = Shift arithmetic right ROL = Rotate left ROR = Rotate right RCL = Rotate left through carry RCR = Rotate right through carry v v v v v v v w w w w w w w w mod mod mod mod mod mod mod mod r/m r/m r/m r/m r/m r/m r/m r/m AND = And: Reg./memory and register to either Immediate to register/memory Immediate to accumulator d w w w mod mod 1 0 data reg r/m r/m data data if w = 1 data if w = 1 TEST = And function to flags, no result: Register/memory and register Immediate data and register/memory Immediate data and accumulator w w w mod mod 0 0 data reg r/m r/m data data if w = 1 data if w = 1 OR = Or: Reg./memory and register to either Immediate to register/memory Immediate to accumulator d w w w mod mod 0 0 data reg r/m r/m data data if w = 1 data if w = 1 XOR = Exclusive or: Reg./memory and register to either Immediate to register/memory Immediate to accumulator d w w w mod mod 1 1 data reg r/m r/m data data if w = 1 data if w = 1 LOGIC

¡ Semiconductor MSM80C86A-10RS/GS/JS REP = Repeat MOVS = Move byte/word CMPS = Compare byte/word SCAS = Scan byte/word LODS = Load byte/word to AL/AX STOS = Store byte/word from AL/AX z w w w w w STRING MANIPULATION CJMP = Conditional JMP JE/JZ = Jump on equal/zero JZ/JNGE = Jump on less/not greater or equal JLE/JNG = Jump on less or equal/not greater JB/JNAE = Jump on below/not above or equal JBE/JNA = Jump on below or equal/not above JP/JPE = Jump on parity/parity even JO = Jump on over flow JS = Jump on sign JNE/JNZ = Jump on not equal/not zero JNL/JGE = Jump on not less/greater or equal JNLE/JG = Jump on not less or equal/greater JNB/JAE = Jump on not below/above or equal JNBE/JA = Jump on not below or equal/above JNP/JPO = Jump on not parity/parity odd JNO = Jump on not overflow JNS = Jump on not sign LOOP = Loop CX times LOOPZ/LOOPE = Loop while zero/equal LOOPNZ/LOOPNE = Loop while not zero equal JCXZ = Jump on CX zero disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp INT = Interrupt Type specified Type 3 INTO = Interrupt on overflow IRET = Interrupt return type

¡ Semiconductor MSM80C86A-10RS/GS/JS CLC = Clear carry CMC = Complementary carry STC = Set carry CLD = Clear direction STD = Set direction CLI = Clear interrupt STI = Set interrupt HLT = Halt WAIT = Wait ESC = Escape ( to external device) LOCK = Bus lock prefix x x x mod x x x r/m PROCESSOR CONTROL CALL = Call: Direct within segment Indirect within segment Direct intersegment Indirect intersegment mod mod disp-low offset-low seg-low r/m r/m 7654 disp-high offset-high seg-high 3210 765 4 3210 JMP = Unconditional Jump: Direct within segment Direct within segment-short Indirect within segment Direct intersegment Indirect intersegment mod mod disp-low disp offset-low seg-low r/m r/m disp-high offset-high seg-high RET = Return from CALL: Within segment Within seg. adding immediate to SP Intersegment Intersegment adding immediate to SP data-low data-low data-high dat-high CONTROL TRANSFER

¡ Semiconductor MSM80C86A-10RS/GS/JS Foot Notes: AL = 8-bit accumulator AX = 18-bit accumulator CX = Count register DS = Data segment ES = Extra segment Above/below refers to unsigned value Greater=more positive Less=less positive (more negative) signed value If d=1 then “to” reg: If d=0 then “from” reg. If w=1 then word instruction: If w=0 then byte instruction If mod=11 then r/m is treated as a REG field If mod=00 then DISP=0*, disp-low and disp-high are absent If mod=01 then DISP=disp-low sign-extended to 16 bits, disp-high is absent If mod=10 then DISP=disp-high: disp-low If r/m=000 then EA=(BX)+(SI)+DISP If r/m=001 then EA=(BX)+(DI)+DISP If r/m=010 then EA=(BP)+(SI)+DISP If r/m=011 then EA=(BP)+(DI)+DISP If r/m=100 then EA=(SI)+DISP If r/m=101 then EA=(DI)+DISP If r/m=110 then EA=(BP)+DISP* If r/m=111 then EA=(BX)+DISP DISP follows 2nd byte of instruction (before data if required) * except if mod=00 and r/m=110 then EA-disp-high: disp-low If s:w=01 then 16 bits of immediate data form the operand If s:w=11 then an immediate data byte is sign extended to form the 16-bit operand If v=0 then “count”=1:if v=1 then “count” in (CL) x=don’ t care z is used for string primitives for comparison with ZF FLAG SEGMENT OVERRIDE PREFIX 001 reg 110 REG is assigned according to the following table: 16-Bit (w=1) 8-Bit (w=0) Segment

000 AX 000 AL 00 ES

001 CX 001 CL 01 CS

010 DX 010 DL 10 SS

011 BX 011 BL 11 DS

100 SP 100 AH

101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file: FLAGS=x:x:x:x:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)

¡ Semiconductor MSM80C86A-10RS/GS/JS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Low-speed device (Old) Remarks M80C85AH M80C85A/M80C85A-2 8bit MPU M80C86A-10 M80C86A/M80C86A-2 16bit MPU M80C88A-10 M80C88A/M80C88A-2 8bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M81C55 RAM.I/O, timer M82C37B-5 M82C37A/M82C37A-5 DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C53-5 Timer M82C55A-2 M82C55A-5 PPI

¡ Semiconductor MSM80C86A-10RS/GS/JS Differences between MSM80C86A-10 and MSM80C86A-2, MSM80C86A 1) Manufacturing Process All devices use a 1.5 m Si-CMOS process technology. 2) Design Although circuit timings of these devices are a little different, these devices have the same chip size and logics. 3) Electrical Characteristics Oki's '96 Data Book for MICROCONTROLLER describes that the MSM80C86A-10 satisfies the electrical characteristics of the MSM80C86A-2 and MSM80C86A. 4) Other notices 1) The noise characteristics of the high-speed MSM80C86A-10 (for 10 MHz) are a little different from those of the MSM80C86A-2 and MSM80C86A. Therefore when devices are replaced for upgrading, it is recommended to perform noise evaluation. 2) The characteristics of the MSM80C86A-10 basically satisfy those of the MSM80C86A-2 and MSM80C86A but their timings are a little different. When critical timing is required in designing it is recommended to evaluate operating margins at various temperatures and voltages.

¡ Semiconductor MSM80C86A-10RS/GS/JS (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.

¡ Semiconductor MSM80C86A-10RS/GS/JS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFJ44-P-S650-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Mirror finish

¡ Semiconductor MSM80C86A-10RS/GS/JS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFP56-P-1519-1.00-K Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.46 TYP. Mirror finish