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MSM80C154S

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MSM80C154S/83C154S¡ Semiconductor GENERAL DESCRIPTION The MSM80C154S/MSM83C154S, designed for the high speed version of the existing MSM80C154/MSM83C154, is a higher performance 8-bit microcontroller providing low-power consumption. The MSM80C154S/MSM83C154S covers the functions and operating range of the existing MSM80C154/83C154/80C51F/80C31F. The MSM80C154S is identical to the MSM83C154S except it does not contain the internal program memory (ROM).

FEATURES

Operating range Operating frequency : 0 to 3 MHz (V cc=2.2 to 6.0 V) 0 to 12 MHz (Vcc=3.0 to 6.0 V) 0 to 24 MHz (Vcc=4.5 to 6.0 V) Operating voltage : 2.2 to 6.0 V Operating temperature : –40 to +85 °C (Operation at +125°C conforms to the other specification.)
Fully static circuit
Upward compatible with the MSM80C51F/80C31F
On-chip program memory : 16K words x 8 bits ROM (MSM83C154S only)
On-chip data memory : 256 words x 8 bits RAM
External program memory address space : 64K bytes ROM (Max)
External data memory address space : 64K bytes RAM
I/O ports : 4 ports x 8 bits (Port 1, 2, 3, impedance programmable) : 32
16-bit timer/counters : 3
Multifunctional serial port : I/O Expansion mode : UART mode (featuring error detection)
6-source 2-priority level Interrupt and multi-level Interrupt available by programming IP and IE registers
Memory-mapped special function registers
Bit addressable data memory and SFRs
Minimum instruction cycle : 500 ns @ 24 MHz operation
Standby functions : Power-down mode (oscillator stop) Activated by software or hardware; providing ports with floating or active status The software power-down stet mode is termi- nated by interrupt signal enabling execution from the interrupted address. ¡ Semiconductor MSM80C154S/83C154S CMOS 8-bit Microcontroller E2E1023-27-Y3 This version: Jan. 1998 Previous version: Nov. 1996

MSM80C154S/83C154S¡ Semiconductor

Package options 40-pin plastic DIP (DIP40-P-600-2.54) : (Product name: MSM80C154SRS/ MSM83C154S-xxxRS) 44-pin plastic QFP (QFP44-P-910-0.80-2K) : (Product name: MSM80C154SGS-2K/ MSM83C154S-xxxGS-2K) 44-pin QFJ (QFJ44-P-S650-1.27) : (Product name: MSM80C154SJS/ MSM83C154S-xxxJS) 44-pin TQFP (TQFP44-P-1010-0.80-K) : (Product name: MSM80C154STS-K/ MSM83C154S-xxxTS-K) xxx: indicates the code number

MSM80C154S/83C154S¡ Semiconductor T2CON PCH CONTROL SIGNAL SPECIAL FUNCTION REGISTER ADDRESS DECODER PLA IR AIR C-ROM TR1TR2ACC ALU BRPSW RAMDP R/W AMP RAM

256 WORDS

P2.0 P2.7 P0.0 P0.7 P1.0 P1.7 P3.0 P3.7 XTAL1 XTAL2 ALE RESET PSEN EA TH1 TL1 TH0 TL0 TMOD TCON IE IP SBUF(T) SBUF(R) INTERRUPTTIMER/COUNTER 0 & 1 SERIAL IO SCON SIGNALR/W TIMER/ COUNTER 2 PCHL ADDRESS DECODER TL2 BLOCK DIAGRAM (MSM83C154S)

MSM80C154S/83C154S¡ Semiconductor PIN CONFIGURATION (TOP VIEW) V SS P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/HPDI P3.6/WR P3.7/RD XTAL2 XTAL1 P2.0 V CC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA ALE PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 40-Pin Plastic DIP

MSM80C154S/83C154S¡ Semiconductor P1.5 P1.6 P1.7 RESET P3.0/RXD NC P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/HPDI P0.4 P0.5 P0.6 P0.7 EA NC ALE PSEN P2.7 P2.6 P2.5 /#04 P1.4 P1.3 P1.2 P1.1 P1.0 NC V CC P0.0 P0.1 P0.2 P0.3 P3.6/WR P3.7/RD XTAL2 XTAL1 V SS VSS P2.0 P2.1 P2.2 P2.3 P2.4 NC : No-connection pin 44-Pin Plastic QFP PIN CONFIGURATION (Continued)

MSM80C154S/83C154S¡ Semiconductor PIN CONFIGURATION (Continued) NC : No-connection pin 44-Pin Plastic QFJ P0.3 P0.2 P0.1 P0.0 V CC NC P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P2.3 P2.2 P2.1 P2.0 NC V SS XTAL1 XTAL2 P3.7/RD P3.6/WR P1.5 P1.6 P1.7 RESET P3.0/RXD NC P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P0.5 P0.6 P0.7 EA NC ALE PSEN P2.7 P2.6 P2.5 P0.4 P2.4 P3.5/T1/HPDI /,/#03

MSM80C154S/83C154S¡ Semiconductor P0.0 to P0.7 P1.0 to P1.7 P2.0 to P2.7 P3.0 to P3.7 ALE PSEN EA Symbol Descriptipn Bidirectional I/O ports. They are also the data/address bus (input/output of data and output of lower 8-bit address when external memory is accessed). They are open-drain outputs when used as I/O ports, but 3-state outputs when used as data/address bus. P1.0 to P1.7 are quasi-bidirectional I/O ports. They are pulled up internally when used as input ports. Two of them have the following secondary functions:

P1.0 (T2)
P1.1 (T2EX) : used as external clock input pins for the timer/counter 2. : used as trigger input for the timer/counter 2 to be reloaded or captured; causing the timer/counter 2 interrupt. P2.0 to P2.7 are quasi-bidirectional I/O ports. They also output the higher 8-bit address when an external memory is accessed. They are pulled up internally when used as input ports. P3.0 to P3.7 are quasi-bidirectional I/O ports. They are pulled up internally when used as input ports. They also have the following secondary functions:
P3.0 (RXD) Serial data input/output in the I/O expansion mode and serial data input in the UART mode when the serial port is used.
3.1 (TXD) Synchronous clock output in the I/O expansion mode and serial data output in the UART mode when the serial port is used.
3.2 (INT0) Used as input pin for the external interrupt 0, and as count-up control pin for the timer/counter 0.
3.3 (INT1) Used as input pin for the external interrupt 1, and as count-up control pin for the timer/counter 1.
3.4 (T0) Used as external clock input pin for the timer/counter 0.
3.5 (T1) Used as external clock input pin for the timer/counter 1 and power-down-mode control input pin.
3.6 (WR) Output of the write-strobe signal when data is written into external data memory.
3.7 (RD) Output of the read-strobe signal when data is read from external data memory. Address latch enable output for latching the lower 8-bit address during external memory access. Two ALE pulses are activated per machine cycle except during external data memory access at which time one ALE pulse is skipped. Program store enable output which enables the external memory output to the bus during external program memory access. Two PSEN pulses are activated per machine cycle except during external data memory access at which two PSEN pulses are skipped. When EA is held at "H" level, the MSM 83C154S executes instructions from internal program memory at address 0000H to 3FFFH, and executes instructions from external program memory above address 3FFFH. When EA is held at "L" level, the MSM80C154S/MSM83C154S executes instructions from external program memory for all addresses. PIN DESCRIPTIONS

MSM80C154S/83C154S¡ Semiconductor PIN Descriptions (Continued) RESET Symbol Descriptipn XTAL1 XTAL2 VCC VSS If this pin remains "H" for at least one machine cycle, the MSM80C154S/MSM83C154S is reset. Since this pin is pulled down internally, a power-on reset is achieved by simply connecting a capacitor between V CC and this pin. Oscillator inverter input pin. External clock is input through XTAL1 pin. Oscillator inverter output pin. Power supply pin during both normal operation and standby operations. GND pin.

MSM80C154S/83C154S¡ Semiconductor REGISTERS Diagram of Special Function Registers REGISTER NAME BIT ADDRESS DIRECT ADDRESSb7 b5 b4 b3 b2 b1 b0b6 IOCON B ACC PSW TH2 TL2 RCAP2H RCAP2L T2CON IP IE SBUF SCON TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP FF CF BF AF FE CE BE AE FD CD BD AD FC CC BC AC FB CB BB AB FA CA BA AA 0F8H (248) 0F0H (240) 0E0H (224) 0D0H (208) 0CDH (205) 0CCH (204) 0CBH (203) 0CAH (202) 0C8H (200) 0B8H (184) 0B0H (176) 0A8H (168) 0A0H (160) 99H (153) 98H (152) 90H (144) 8DH (141) 8CH (140) 8BH (139) 8AH (138) 89H (137) 88H (136) 87H (135) 83H (131) 82H (130) 81H (129) 80H (128)

MSM80C154S/83C154S¡ Semiconductor Timer/counter 0 mode setting NAME ADDRESS MSB LSB 76543210 BIT LOCATION FLAG FUNCTION TMOD 89H GATE C/ T M1 M0 GATE C/ T M1 M0 TMOD.0 M0 M1 M0 8-bit timer/counter with 5-bit prescalar.00 16-bit timer/counter. 01 8-bit timer/counter with 8-bit auto reloading.10 Timer/counter 0 separated into TLO (8-bit) timer/counter and TH0 (8-bit) timer/counter. TF0 is set by TL0 carry, and TF1 is set by TH0 carry. 11TMOD.1 M1 Timer/counter 0 count clock designation control bit. XTAL1•2 divided by 12 clocks is the input applied to timer/counter 0 when C/T = "0". The external clock applied to the T0 pin is the input applied to timer/counter 0 when C/T = "1". TMOD.2 C/ T When this bit is "0", the TR0 bit of TCON (timer control register) is used to control the start and stop of timer/counter 0 counting. If this bit is "1", timer/counter 0 starts counting when both the TR0 bit of TCON and INT0 pin input signal are "1", and stops counting when either is changed to "0". TMOD.3 GATE Timer/counter 1 mode settingTMOD.4 M0 M1 M0 8-bit timer/counter with 5-bit prescalar.00 16-bit timer/counter01 8-bit timer/counter with 8-bit auto reloading.10 Timer/counter 1 operation stopped.11TMOD.5 M1 Timer/counter 1 count clock designation control bit. XTAL1•2 divided by 12 clocks is the input applied to timer/counter 1 when C/T = "0". The external clock applied to the T1 pin is the input applied to timer/counter 1 when C/T = "1". TMOD.6 C/ T When this bit is "0", the TR1 bit of TCON is used to control the start and stop of timer/counter 1 counting. If this bit is "1", timer/counter 1 starts counting when both the TR1 bit of TCON and INT1 pin input signal are "1", and stops counting when either is changed to "0". TMOD.7 GATE Special Function Registers Timer mode register (TMOD)

MSM80C154S/83C154S¡ Semiconductor Power control register (PCON) IDLE mode is set when this bit is set to "1". CPU operations are stopped when IDLE mode is set, but XTAL1•2, timer/counters 0, 1 and 2, the interrupt circuits, and the serial port remain active. IDLE mode is cancelled when the CPU is reset or when an interrupt is generated. NAME ADDRESS MSB LSB 76543210 BIT LOCATION FLAG FUNCTION PCON 87H SMOD HPD RPD — GF1 GF0 PD IDL PCON.0 IDL PD mode is set when this bit is set to "1". CPU operations and XTAL1•2 are stopped when PD mode is set. PD mode is cancelled when the CPU is reset or when an interrupt is generated. PCON.1 PD General purpose bit.PCON.2 GF0 General purpose bit.PCON.3 GF1 Reserved bit. The output data is "1", if the bit is read.PCON.4 — This bit is used to specify cancellation of CPU power down mode (IDLE or PD) by an interrupt signal. Power-down mode cannot be cancelled by an interrupt signal if the interrupt is not enabled by IE (interrupt enable register) when this bit is "0". If the interrupt flag is set to "1" by an interrupt request signal when this bit is "1" (even if interrupt is disabled), the program is executed from the next address of the power-down-mode setting instruction. The flag is reset to "0" by software. PCON.5 RPD The hard power-down setting mode in enabled when this bit is set to "1". If the level of the power failure detect signal applied to the HPDI pin (pin 3.5) is changed from "1" to "0" when this bit is "1", XTAL1•2 oscillation is stopped and the system is put into hard power down mode. HPD mode is cancelled when the CPU is reset. PCON.6 HPD When the timer/counter 1 carry signal is used as a clock in mode 1, 2 or 3 of the serial port, this bit has the following functions. The serial port operation clock is reduced by 1/2 when the bit is "0" for delayed processing. When the bit is "1", the serial port operation clock is normal for faster processing. PCON.7 SMOD

MSM80C154S/83C154S¡ Semiconductor External interrupt 0 signal is used in level-detect mode when this bit is "0" and in trigger detect mode when "1". NAME ADDRESS MSB LSB 76543210 BIT LOCATION FLAG FUNCTION TCON 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON.0 IT0 Interrupt request flag for external interrupt 0. The bit is reset automatically when an interrupt is serviced. The bit can be set and reset by software when IT0 = "1". TCON.1 IE0 External interrupt 1 signal is used in level detect mode when this bit is "0", and in trigger detect mode when "1". TCON.2 IT1 Interrupt request flag for external interrupt 1. The bit is reset automatically when an interrupt is serviced. The bit can be set and reset by software when IT1 = "1". TCON.3 IE1 Counting start and stop control bit for timer/counter 0. Timer/counter 0 starts counting when this bit is "1", and stops counitng when "0". TCON.4 TR0 Interrupt request flag for timer interrupt 0. The bit is reset automatically when an interrupt is serviced. The bit is set to "1" when a carry signal is generated from timer/counter 0. TCON.5 TF0 Counting start and stop control bit for timer/counter 1. The timer/counter 1 starts counting when this bit is "1", and stops counting when "0". TCON.6 TR1 Interrupt request flag for timer interrupt 1. The bit is reset automatically when interrupt is serviced. The bit is set to "1" when carry signal is generated from timer/counter 1. TCON.7 TF1 Timer control register (TCON)

MSM80C154S/83C154S¡ Semiconductor "End of serial port reception" interrupt request flag. This flag must be reset by software during interrupt service routine. This flag is set after the eighth bit of data has been received when in mode 0, or by the STOP bit when in any other mode. In mode 2 or 3, however, RI is not set if the RB8 data is "0" with SM2 = "1". RI is set in mode 1 if STOP bit is received when SM2 = "1". NAME ADDRESS MSB LSB 76543210 BIT LOCATION FLAG FUNCTION SCON 98H SM0 SM1 SM2 REN TB8 RB8 TI RI SCON.0 RI "End of serial port tramsmission" interrupt request flag. This flag must be reset by software during interrupt service routine. This flag is set after the eighth bit of data has been sent when in mode 0, or after the last bit of data has been sent when in any other mode. SCON.1 TI The TB8 data is sent as the ninth data bit when in mode 2 or 3. Any desired data can be set in TB8 by software. SCON.3 TB8 SCON.6 SM1 SM0 SM1 8-bit shift register I/O00 8-bit UART variable baud rate01 9-bit UART 1/32 XTAL1, 1/64 XTAL1 baud rate10 9-bit UART variable baud rate11 SCON.7 SM0 The ninth bit of data received in mode 2 or 3 is passed to RB8. The STOP bit is applied to RB8 if SM2 = "0" when in mode 1. RB8 can not be used in mode 0. SCON.2 RB8 Reception enable control bit. No reception when REN = "0". Reception enabled when REN = "1". SCON.4 REN If the ninth bit of received data is "0" with SM2 = "1" in mode 2 or 3, the "end of reception" signal is not set in the RI flag. The "end of reception" signal set in the RI flag if the STOP bit is not "1" when SM2 = "1" in mode 1. SCON.5 SM2 MODE Serial port control register (SCON)

MSM80C154S/83C154S¡ Semiconductor Interrupt control bit for external interrupt 0. Interrupt disabled when bit is "0". Interrupt enabled when bit is "1". NAME ADDRESS MSB LSB 76543210 BIT LOCATION FLAG FUNCTION IE 0A8H EA — ET2 ES ET1 EX1 ET0 EX0 IE.0 EX0 Interrupt control bit for timer interrupt 0. Interrupt disabled when bit is "0". Interrupt enabled when bit is "1". IE.1 ET0 Interrupt control bit for external interrupt 1. Interrupt disabled when bit is "0". Interrupt enabled when bit is "1". IE.2 EX1 Interrupt control bit for timer interrupt 1. Interrupt disabled when bit is "0". Interrupt enabled when bit is "1". IE.3 ET1 Interrupt control bit for serial port. Interrupt disabled when bit is "0". Interrupt enabled when bit is "1". IE.4 ES Interrupt control bit for timer interrupt 2. Interrupt disabled when bit is "0". Interrupt enabled when bit is "1". IE.5 ET2 Reserved bit. The output data is "1" if the bit is read.IE.6 — Overall interrupt control bit. All interrupts are disabled when bit is "0". All interrupts are controlled by IE.0 thru IE.5 when bit is "1". IE.7 EA Interrupt enable register (IE)

MSM80C154S/83C154S¡ Semiconductor Interrupt priority bit for external interrupt 0. Priority is assigned when bit is "1". NAME ADDRESS MSB LSB 76543210 BIT LOCATION FLAG FUNCTION IP 0B8H PCT — PT2 PS PT1 PX1 PT0 PX0 IP.0 PX0 IP.1 PT0 IP.2 PX1 IP.3 PT1 IP.4 PS IP.5 PT2 Reserved bit. The output data is "1" if the bit is read.IP.6 — Priority interrupt circuit control bit. The priority register contents are valid and priority assigned interrupts can be processed when this bit is "0". When the bit is "1", the priority interrupt circuit is stopped, and interrupts can only be controlled by the interrupt enable register (IE). IP.7 PCT Interrupt priority bit for timer interrupt 0. Priority is assigned when bit is "1". Interrupt priority bit for external interrupt 1. Priority is assigned when bit is "1". Interrupt priority bit for timer interrupt 1. Priority is assigned when bit is "1". Interrupt priority bit for serial port. Priority is assigned when bit is "1". Interrupt priority bit for timer interrupt 2. Priority is assigned when bit is "1". Interrupt priority register (IP)

MSM80C154S/83C154S¡ Semiconductor Program status word register (PSW) Accumulator (ACC) parity indicator. This bit is "1" when the "1" bit number in the accumulator is an odd number, and "0" when an even number. NAME ADDRESS MSB LSB 76543210 BIT LOCATION FLAG FUNCTION PSW 0D0H CY AC F0 RS1 RS0 OV F1 P PSW.0 P User flag which may be set to "0" or "1" as desired by the user.PSW.1 F1 RAM register bank switchPSW.3 RS0 RS1 RS0 00H - 07H00 08H - 0FH01 10H - 17H10 18H - 1FH11 PSW.4 RS1 Overflow flag which is set if the carry C6 from bit 6 of the ALU or CY is "1" as a result of an arithmetic operation. The flag is also set to "1" if the resultant product of executing multiplication instruction (MUL AB) is greater than 0FFH, but is reset to "0" if the product is less than or equal to 0FFH. PSW.2 OV BANK User flag which may be set to "0" or "1" as desired by the user.PSW.5 F0 Auxiliary carry flag. This flag is set to "1" if a carry C3 is generated from bit 3 of the ALU as a result of executing an arithmetic operation instruction. In all other cases, the flag is reset to "0". PSW.6 AC Main carry flag. This flag is set to "1" if a carry C7 is generated from bit 7 of the ALU as result of executing an arithmetic operation instruction. If a carry C 7 is not generated, the flag is reset to "0". PSW.7 CY RAM ADDRESS

MSM80C154S/83C154S¡ Semiconductor If CPU power down mode (PD, HPD) is activated with this bit set to "1", the outputs from ports 0, 1, 2, and 3 are switched to floating status. When this bit is "0", ports 0, 1, 2, and 3 are in output mode. NAME ADDRESS MSB LSB 76543210 BIT LOCATION FLAG FUNCTION IOCON 0F8H — T32 SERR IZC P3HZ P2HZ P1HZ ALF IOCON.0 ALF IOCON.1 P1HZ IOCON.2 P2HZ IOCON.3 P3HZ IOCON.4 IZC IOCON.5 SERR Timer/counters 0 and 1 are connected serially to from a 32-bit timer/counter when this bit is set to "1". TF1 of TCON is set if a carry is generated in the 32-bit timer/counter. IOCON.6 T32 Leave this bit at "0".IOCON.7 — Port 1 becomes a high impedance input port when this bit is "1". Port 2 becomes a high impedance input port when this bit is "1". Port 3 becomes a high impedance input port when this bit is "1". The 10 kW pull-up resistor for ports 1, 2, and 3 is switched off when this bit is "1", leaving only the 100 kW pull-up resistor. Serial port reception error flag. This flag is set to "1" if an overrun or framing error is generated when data is received at a serial port. The flag is reset by software. I/O control register (IOCON)

MSM80C154S/83C154S¡ Semiconductor Capture mode is set when TCLK + RCLK = "0" and CP/RL2 = "1". 16-bit auto reload mode is set when TCLK + RCLK = "0" and CP/RL2 = "0". CP/RL2 is ignored when TCLK + RCLK = "1". NAME ADDRESS MSB LSB 76543210 BIT LOCATION FLAG FUNCTION T2CON 0C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/ T2 CP/RL2 T2CON.0 CP/ RL2 T2CON.1 C/ T2 T2CON.2 TR2 T2CON.3 EXEN2 T2CON.4 TCLK T2CON.5 RCLK Timer/counter 2 external flag. This bit is set to "1" when the T2EX timer/counter 2 external control signal level is changed from "1" to "0" while EXEN2 = "1". This flag serves as the timer interrupt 2 request signal. If an interrupt is generated, EXF2 must be reset to "0" by software. T2CON.6 EXF2 Timer/counter 2 carry flag. This bit is set to "1" by a carry signal when timer/counter 2 is in 16-bit auto reload mode or in capture mode. This flag serves as the timer interrupt 2 request signal. If an interrupt is generated, TF2 must be reset to "0" by software. T2CON.7 TF2 Timer/counter 2 count clock designation control bit. The internal clocks (XTAL1•2 ÷ 12, XTAL1•2 ÷ 2) are used when this bit is "0", and the external clock applied to the T2 pin is passed to timer/counter 2 when the bit is "1". Timer/counter 2 counting start and stop control bit. Timer/counter 2 commences counting when this bit is "1" and stops counting when "0". T2EX timer/counter 2 external control signal control bit. Input of the T2EX signal is disabled when this bit is "0", and enabled when "1". Serial port transmit circuit drive clock control bit. Timer/counter 2 is switched to baud rate generator mode when this bit is "1", and the timer/counter 2 carry signal becomes the serial port transmit clock. Note, however, that the serial ports can only use the timer/counter 2 carry signal in serial port modes 1 and 3. Serial port receive circuit drive clock control bit. Timer/counter 2 is switched to baud rate generator mode when this bit is "1", and the timer/counter 2 carry signal becomes the serial port transmit clock. Note, however, that the serial ports can only use the timer/counter 2 carry signal in serial port modes 1 and 3. Timer 2 control register (T2CON)

MSM80C154S/83C154S¡ Semiconductor MEMORY MAPS Program Area 002BH43Timer interrupt 2 start 0023H35S I/O interrupt start 001BH27Timer interrupt 1 start 0013H19External interrupt 1 start 0001H1 0000H0CPU reset start 0003H3External interrupt 0 start 0002H2 000BH11Timer interrupt 0 start 16384 65535 4000H 0FFFFH MSM83C154S EXTERNAL ROM AREA 16383 002BH 3FFFH MSM83C154S INTERNAL ROM AREA 44 002CH 7 6 5 4 3 2 1 00 MSM80C154S EXTERNAL ROM AREA

MSM80C154S/83C154S¡ Semiconductor Internal Data Memory and Special Function Register Layout Diagram 248(0F8H) 240(0F0H) 224(0E0H) 208(0D0H) 205(0CDH) 204(0CCH) 203(OCBH) 202(0CAH) 200(0C8H) 184(0B8H) 176(0B0H) 168(0A8H) 160(0A0H) 153( 99H) 152( 98H) 144( 90H) 141( 8DH) 140( 8CH) 139( 8BH) 138( 8AH) 137( 89H) 136( 88H) 135( 87H) 131( 83H) 130( 82H) 129( 81H) 128( 80H) FFH~F8H F7H~F0H E7H~E0H D7H~D0H CFH~C8H BFH~B8H B7H~B0H AFH~A8H A7H~A0H 9FH~98H 97H~90H 8FH~88H 87H~80H IOCON B ACC PSW TH2 TL2 RCAP2H RCAP2L T2CON IP IE SBUF SCON TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP USER DATA RAM BIT RAM BANK3 BANK2 BANK1 BANK0 HEX 0FFREGISTER INDIRECT ADDRESSING SPECIAL FUNCTION REGISTERS USER DATA RAM BIT ADDRESSING DATA ADDRESSING

MSM80C154S/83C154S¡ Semiconductor Bank 2 Bank 1 Bank 0 Bank 3 127 255 08H 2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 7FH 0FFH 1FH 18H 17H 10H 0FH 07H 00H REGISTER 0, 1, INDIRECT ADDRESSING BIT ADDRESSING DATA ADDRESSING REGISTERS 0-7 DIRIECT ADDRESSING USER DATA RAM USER DATA RAM 128 30H 80H Diagram of Internal Data Memory (RAM)

MSM80C154S/83C154S¡ Semiconductor ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Supply voltage Input voltage Storage temperature V CC Ta=25°C –0.5 to 7 V VI Ta=25°C –0.5 to V CC+0.5 V TSTG — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit Power supply voltage Memory retension voltage Oxcillation frequency V CC See below. 2.0 to 6.0 V VCC fOSC=0 Hz (Oscillation stop) 2.0 to 6.0 V fOSC See below. 1 to 24 MHz External clock operating frequency Ambient temperature fEXTCLK See below. 0 to 24 MHz Ta — –40 to +85 °C *1 Depends on the specifications for the oscillator or ceramic resonater. 0.5 23456 Power Supply Voltage (VCC) 2.2 0.6 tCY (ms) fOSC fEXTCLK (MHz)

MSM80C154S/83C154S¡ Semiconductor

ELECTRICAL CHARACTERISTICS

0.2 VCC–0.1 Parameter Symbol Condition Min. Typ. Max. Unit Input Low Voltage V IL — –0.5 — V VCC+0.5Input High Voltage V IH Except XTAL1, EA, 0.2 VCC+0.9 — Vand RESET VCC+0.5Input High Voltage V IH1 XTAL1, RESET and EA 0.7 VCC —V 0.45 Output Low Voltage VOL IOL=1.6 mA — — V(PORT 1, 2, 3) 0.45 Output Low Voltage VOL1 IOL=3.2 mA — — V(PORT 0, ALE, PSEN) —Output High Voltage VOH IOH=–60 mA 2.4 — V (PORT 1, 2, 3) VCC=5 V±10% —IOH=–30 mA 0.75 V CC —V —IOH=–10 mA 0.9 V CC —V —Output High Voltage VOH1 IOH=–400 mA 2.4 — V (PORT 0, ALE, PSEN) VCC=5 V±10% —IOH=–150 mA 0.75 V CC —V —IOH=–40 mA 0.9 V CC —V –80 Logical 0 Input Current/ Logical 1 Output Current/ (PORT 1, 2, 3) I IL / IOH VI=0.45 V –5 –20 mAVO=0.45 V –500 Logical 1 to 0 Transition ITL VI=2.0 V — –190 mAOutput Current (PORT 1, 2, 3) 125RESET Pull-down Resistance R RST —2 0 4 0 k W/CR 10Pin Capacitance C IO Ta=25°C, f=1 MHz —— p F (except XTAL1) 50Power Down Current I PD —1 mA 3±10 Input Leakage Current ILI VSS < VI < VCC —— mA(PORT 0 floating, EA) (VCC=4.0 to 6.0 V, VSS=0 V, Ta=-40 to +85°C)

MSM80C154S/83C154S¡ Semiconductor Maximum power supply current normal operation I CC (mA) VCC 4 V 5 V 6 V Freq 2.2 3.1 4.11 MHz 3.9 5.2 7.03 MHz 12.0 16.0 20.012 MHz 16.0 20.0 25.016 MHz 19.0 25.0 30.020 MHz VCC 4.5 V 5 V 6 V Freq 25.0 29.0 35.024 MHz Maximum power supply current idle mode I CC (mA) VCC 4 V 5 V 6 V Freq 0.8 1.2 1.61 MHz 1.2 1.7 2.33 MHz 3.1 4.4 5.912 MHz 3.8 5.5 7.316 MHz 4.5 6.4 8.620 MHz VCC 4.5 V 5 V 6 V Freq 6.4 7.4 9.824 MHz

MSM80C154S/83C154S¡ Semiconductor DC Characteristics 2 Output High Voltage VOH1 IOH=–20 mA 0.75 VCC —V(PORT 0, ALE, PSEN) –40 Logical 0 Input Current/ Logical 1 Output Current/ (PORT 1, 2, 3) I IL / IOH VI=0.1 V –5 –10 mAVO=0.1 V –300 Logical 1 to 0 Transition ITL VI=1.9 V — –80 mAOutput Current (PORT 1, 2, 3) 125RESET Pull-down Resistance R RST —2 0 4 0 k W/CR 10Pin Capacitance C IO Ta=25°C, f=1 MHz —— p F(except XTAL1) 10Power Down Current I PD —— 1 mA 3±10 Input Leakage Current ILI VSS < VI < VCC —— mA(PORT 0 floating, EA) Meas- uring circuit 0.25 VCC–0.1 Parameter Symbol Condition Min. Typ. Max. Unit Input Low Voltage V IL — –0.5 — V VCC+0.5Input High Voltage V IH Except XTAL1, EA, 0.25 VCC+0.9 — Vand RESET VCC+0.5Input High Voltage V IH1 XTAL1, RESET, and EA 0.6 VCC+0.6 — V 0.1 Output Low Voltage VOL IOL=10 mA— — V(PORT 1, 2, 3) 0.1 Output Low Voltage VOL1 IOL=20 mA— — V(PORT 0, ALE, PSEN) —Output High Voltage VOH IOH=–5 mA 0.75 VCC —V (PORT 1, 2, 3) (VCC=2.2 to 4.0 V, VSS=0 V, Ta=-40 to +85°C)

MSM80C154S/83C154S¡ Semiconductor Maximum power supply current normal operation I CC (mA) VCC 2.2 V 3.0 V 4.0 V Freq 0.9 1.4 2.21 MHz 1.8 2.4 4.33 MHz — 8.0 12.012 MHz — — 16.016 MHz Maximum power supply current idle mode I CC (mA) VCC 2.2 V 3.0 V 4.0 V Freq 0.3 0.5 0.81 MHz 0.5 0.8 1.23 MHz — 2.0 3.112 MHz — — 3.816 MHz

MSM80C154S/83C154S¡ Semiconductor VCC VSS INPUT OUTPUT VIH VIL (*2) V A IO VCC VSS INPUT OUTPUT (*1) V VCC VSS INPUT OUTPUT VIH VIL (*2) V A (*3) VCC VSS INPUT OUTPUT VIH VIL A A (*3) (*3) Measuring circuits *1: Repeated for specified input pins. *2: Repeated for specified output pins. *3: Input logic for specified status.

MSM80C154S/83C154S¡ Semiconductor AC Characteristics (1) External program memory access AC characteristics Parameter Symble Unit Min. Max. 1 to 24 MHz Variable clock from 41.7 1000 nstCLCLXTAL1, XTAL 2 Oscillation Cycle 2tCLCL-40 — nstLHLLALE Signal Width 1tCLCL-15 — nstAVLL Address Setup Time (to ALE Falling Edge) 1tCLCL-35 — nstLLAX Address Hold Time (from ALE Falling Edge) —4 t CLCL-100 nstLLPL Instruction Data Read Time (from ALE Falling Edge) 1tCLCL-30 — nstLLPL From ALE Falling Edge to PSEN Falling Edge 3tCLCL-35 — nstPLPHPSEN Signal Width —3 t CLCL-45 nstPLIV Instruction Data Read Time (from PSEN Falling Edge) 0— n stPXIX Instruction Data Hold Time (from PSEN Rising Edge) —1 t CLCL-20 nstPXIZ Bus Floating Time after Instruction Data Read (from PSEN Rising Edge) —5 t CLCL-105 nstAVIV Instruction Data Read Time (from Address Output) 0— n stAZPL Bus Floating Time(PSEN Rising Edge from Address float) 1tCLCL-20 — nstPXAV Address Output Time from PSEN Rising Edge VCC=2.2 to 6.0V, VSS=0V, Ta=–40°C to +85°C PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load *1 The variable check is from 0 to 24 MHz when the external check is used.

MSM80C154S/83C154S¡ Semiconductor tLHLL tAVLL tLLPL tPLPH tLLIV tPLIV tPXAV tPXIZ tLLAX tAZPL tAVIV tPXIX A0 to A7 INSTR IN A0 to A7PORT0 PORT2 A8 to A15 A8 to A15 A8 to A15 PSEN ALE (2) External program memory read cycle

MSM80C154S/83C154S¡ Semiconductor (3) External data memory access AC characteristics *1 The variable check is from 0 to 24 MHz when the external check is used. *2 For 2.2 £VCC<4 V Parameter Symbol Unit Min. Max. 1 to 24 MHz Variable clock from 41.7 1000 nstCLCLXTAL1, XTAL2 Oscillator Cycle 2tCLCL-40 — nstLHLLALE Signal Width 1tCLCL-15 — nstAVLL Address Setup Time (to ALE Falling Edge) 1tCLCL-35 — nstLLAX Address Hold Time (from ALE Falling Edge) 6tCLCL-100 — nstRLRLRD Signal Width 6tCLCL-100 — nstWLWHWR Signal Width —5 t CLCL-105 nstRLDV RAM Data Read Time (from RD Signal Falling Edge) 0— n stRHDX RAM Data Read Hold Time (from RD Signal Rising Edge) —2 t CLCL-70 nstRHDZ Data Bus Floating Time (from RD Signal Rising Edge) —8 t CLCL-100 nstLLDV RAM Data Read Time (from ALE Signal Falling Edge) —9 t CLCL-105 nstAVDV RAM Data Read Time (from Address Output) 3tCLCL-40 3tCLCL+40 nstLLWL RD/WR Output Time from ALE Falling Edge 4tCLCL-70 — nstAVWL RD/WR Output Time from Address Output 1tCLCL-40 — nstQVWXWR Output Time from Data Output 7tCLCL-105 — nstQVWHTime from Data to WR Rising Edge 2tCLCL-50 — nstWHQX Data Hold Time (from WR Rising Edge) 0— n stRLAZ Time from to Address Float RD Output 1tCLCL-30 1tCLCL+40 nstWHLH Time from RD/WR Rising Edge to ALE Rising Edge 3tCLCL-100*2 *2 1tCLCL+100 VCC=2.2 to 6.0V, VSS=0V, Ta=–40°C to +85°C PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load

MSM80C154S/83C154S¡ Semiconductor tLHLL tWHLH tLLDV tLLWL tRLRH tAVLL tLLAX tRLDV tRHDX tRHDZ tAVWL tAVDV PCH A8 to A15 PCH P2.0 to P2.7 DATA A8 to A15 DPH or A8 to A15 PCH A0 to A7 PCL A0 to A7 Rr or DPL A0 to A7 PCL INSTR IN ALE PSEN RD PORT 0 PORT 2 DATA IN tAZRL tLHLL tWHLH tLLWL tWLWH tAVLL tLLAX tQVWH tWHQX tAVWL A8 to A15 PCH P2.0 to P2.7 DATA A8 to A15 DPHor A8 to A15 PCH A0 to A7 PCL A0 to A7 Rr or DPLA0 to A7 PCL INSTR IN ALE PSEN WR PORT 0 PORT 2 DATA (ACC) A8 to A15 PCH tQVWX (4) External data memory read cycle (5) External data memory write cycle

MSM80C154S/83C154S¡ Semiconductor (6) Serial port (I/O Extension Mode) AC characteristics Parameter Symbol Min. Max. Unit Serial Port Clock Cycle Time t XLXL 12tCLCL —n s Output Data Setup to Clock Rising Edge t QVXH 10tCLCL-133 — Output Data Hold After Clock Rising Edge t XHQX 2tCLCL-75 — Input Data Hold After Clock Rising Edge t XHDX 0— Clock Rising Edge to Input Data Valid t XHDV — 10t CLCL-133 ns ns ns ns CC=2.2 to 6.0V, VSS=0V, Ta=–40°C to +85°C)

MSM80C154S/83C154S¡ Semiconductor tXLXL tQVXH tXHQX tXHDV tXHDX VALID VALID VALID VALID VALID VALID VALID VALID MACHINE CYCLE ALE SHIFT CLOCK OUTPUT DATA INPUT DATA

MSM80C154S/83C154S¡ Semiconductor (7) AC Characteristics Measuring Conditions 1.Input/output signal VOH VOL VOH VOL VIH VIL VIH VIL TEST POINT * The input signals in AC test mode are either V OH (logic "1") or VOL (logic "0") input signals where logic "1" corresponds to a CPU output signal waveform measuring point in excess of V IH, and logic "0" to a point below VIL. 2.Floating VOH VOL VOH VOL VIH VIL VIH VIL Floating * The port 0 floating interval is measured from the time the port 0 pin voltage drops below VIH after sinking to GND at 2.4 mA when switching to floating status from a "1" output, and from the time the port 0 pin voltage exceeds VIL after connecting to a 400 mA source when switching to floating status from a "0" output. (8) XTAL1 external clock input waveform conditions Parameter Symbol Min. Max. Unit External Clock Freq. 1/t CLCL 0 24 MHz Clock Pulse width 1 t CHCx 15 — Clock Pulse width 2 t CLCX 15 — Rise Time t CLCH —5 Fall Time t CHCL —5 ns ns ns ns External Clock Drive Waveform

0.7 VCC

0.2 VCC - 0.1 tCHCL tCLCH tCLCX tCLCL tCHCX EXTERNAL OSCILLATOR SIGNAL

MSM80C154S/83C154S¡ Semiconductor Timing Diagram Basic timing ACC & RAM S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 PCL PCL PCL PCL PCH PCH PCH PCHPCHDPH & PORT DATAPCH /,/,/,/,/,/, PC+1 TM+1 PC+1 TM+1TM+1TM+1 PC+1PC+1PC+1 CYCLE STEP XTAL 1 ALE RD/WR PORT-0 PORT-2 CPU‹ PORT PORT‹ CPU PCH PCL DPL&Rr DATA STABLE PORT OLD DATA DATA STABLE PSEN PCL PORT NEW DATA Port output/input instruction execution Instruction execution External data memory instruction execution Instruction execution Port output/input instruction execution Instruction execution Instruction decoding Instruction decodingInstruction decoding

MSM80C154S/83C154S¡ Semiconductor (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.

MSM80C154S/83C154S¡ Semiconductor (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. QFP44-P-910-0.80-2K Mirror finish

MSM80C154S/83C154S¡ Semiconductor (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFJ44-P-S650-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Mirror finish

MSM80C154S/83C154S¡ Semiconductor (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). TQFP44-P-1010-0.80-K Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.28 TYP. Mirror finish

Product Information

MSM80C154S specifications and overview.

Summary

CMOS 8-bit Microcontroller

Description

CMOS 8-bit Microcontroller

Source title MSM80C154S Datasheet(PDF) - OKI electronic componets

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