MSM7717-02

MSM7717-01 OKI | Alldatasheet

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¡ Semiconductor MSM7717-01/02/03 ¡ Semiconductor MSM7717-01/02/03 Single Rail CODEC GENERAL DESCRIPTION The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400 Hz with filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the device is optimized for ISDN terminals and telephone terminals in digital wireless systems. The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B. The analog output, which can drive a 1.2 k W load, can directly drive a handset receiver differentially.

FEATURES

• Single power supply: 2.7 V to 3.8 V
• Low power consumption Operating mode: 20 mW Typ. V DD = 3 V Power-down mode: 0.03 mW Typ. V DD = 3 V
• Conforms to ITU-T Companding law MSM7717-01: m/A-law pin selectable MSM7717-02: m-law MSM7717-03: A-law
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024 kHz 96/192/384/768/1536/1544/2048/200 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Package options: 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM7717-01GS-K) (Product name: MSM7717-02GS-K) (Product name: MSM7717-03GS-K) 20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K) (Product name: MSM7717-02MS-K) (Product name: MSM7717-03MS-K) E2U0041-28-81 This version: Aug. 1998 Previous version: Nov. 1996

¡ Semiconductor MSM7717-01/02/03 BLOCK DIAGRAM RC LPF 8th BPF AD CONV. TCONT AUTO ZERO 5th LPF DA CONV. PWD Logic PLL RTIM RCONT PCMOUT PCMIN PDN VDD AG DG SG GEN SGC SG PWD AIN– AIN+ GSX VFRO SG RSYNC BCLK XSYNC (ALAW) VR GEN +AOUT– SG PWI +AOUT+ SG

¡ Semiconductor MSM7717-01/02/03 PIN CONFIGURATION (TOP VIEW) 10 11 20SG AOUT+ AOUT– PWI VFRO V DD DG PDN SGC AIN+ AIN– GSX AG BCLK NC : No connect pin /#06/#08/#06/#07 RSYNC PCMIN XSYNC PCMOUT 12 13 24SG AOUT+ AOUT– PWI VFRO DG PDN SGC AIN+ AIN– GSX AG NC : No connect pin RSYNC PCMIN XSYNC PCMOUT VDD BCLK (ALAW)* NC NC NC (ALAW)* NC NC NC 20-Pin Plastic SSOP 24-Pin Plastic SOP * The ALAW pin is only supported by the MSM7717-01GS-K/MSM7717-01MS-K.

¡ Semiconductor MSM7717-01/02/03 PIN AND FUNCTIONAL DESCRIPTIONS AIN+, AIN–, GSX Transmit analog input and transmit level adjustment. AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is connected to the output of the op-amp. The level adjustment should be performed in any method shown below. When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power-saving and power-down modes, the GSX output is at AG voltage. AG Analog signal ground. VFRO Receive filter output. The output signal has an amplitude of 2.0 V PP above and below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMIN and can drive a load of 20 kW or more. For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO and PWI. During power-saving mode this output is in a high impedance state, and during power-down mode, the VFRO output is at an SG level. When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency Characteristics Adjustment Circuit. AIN– AIN+ Analog input 1) Inverting input type R1 : variable R2 > 20 kW Gain = R2/R1 < 10 GSX SG AIN+ AIN– 2) Noninverting input type R3 > 20 kW R4 > 20 kW R5 > 50 kW Gain = 1 + R4 / R3 £ 10 GSX SG Analog input

¡ Semiconductor MSM7717-01/02/03 PWI, AOUT+, AOUT– PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted with respect to the output of AOUT–. Since these outputs provide differential drive of an impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being activated during the power-saving mode, the amplifiers can output other external signals from AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during the power-down mode. VDD Power supply for 2.7 V to 3.8 V. (Typically 3.0 V) PCMIN PCM data input. A serial PCM data input to this pin is converted to an analog signal in synchronization with the RSYNC signal and BCLK signal. The data rate of PCM is equal to the frequency of the BCLK signal. PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. BCLK Shift clock signal input for the PCMIN and PCMOUT signal. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive driver amplifiers are in the operating mode and the other circuits are in the non-operating mode. R6 > 20 kW Gain = VO/VI = R7/R6 £ 1 +SG SG VFRO PWI AOUT– AOUT+ ZL Analog output Analog inverted output ZL > 1.2 kW External Signal Input Receive filter VI VO

¡ Semiconductor MSM7717-01/02/03 RSYNC Receive synchronizing signal input. Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. The frequency should be 8 kHz –50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 kHz –2 kHz, but the electrical characteristics in this specification are not guaranteed. XSYNC Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz –50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, if the frequency characteristic of an applied system is not specified exactly, this device operates in the range of 8 kHz –2 kHz, but the electrical characteristics in this specification are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state.

¡ Semiconductor MSM7717-01/02/03 DG Ground for the digital signal circuits. This ground is separate from the analog signal ground AG. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground AG. PDN Power down control signal. A logic "0" level drives both transmit and receive circuits to a power down state. PCMOUT PCM signal output. Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from MSD in a sequential order. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power saving or power down mode. A pull-up resistor must be connected to this pin because its output is configured as an open drain. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7717-03 (A-law) outputs the character signal, inverting the even bits. Input/Output Level +Full scale –Full scale PCMIN/PCMOUT MSM7717-02 (m-law) MSD 1000 0000 1111 1111 0111 1111 0000 0000 MSM7717-03 (A-law) MSD 1010 1010 1101 0101 0101 0101 0010 1010

¡ Semiconductor MSM7717-01/02/03 SG Signal ground voltage output. The output voltage is 1/2 of the power supply voltage. The output drive current capability is –200 mA. This pin provides the SG level for CODEC peripherals. This output voltage level is undefined during power-saving or power-down mode. SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Only the MSM7717-01GS-K/7717-01MS-K has this pin. The CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will has this pin operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since the pin is internally pulled down.

¡ Semiconductor MSM7717-01/02/03 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS UnitMax.Typ.Min.ConditionSymbolParameter V3.83.02.7Voltage must be fixedVDDPower Supply Voltage °C+85+25–30—TaOperating Temperature VPP1.4——Connect AIN– and GSXVAINAnalog Input Voltage VVDD—0.45´VDDXSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW VIHHigh Level Input Voltage V0.16´VDD—0VILLow Level Input Voltage 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 BCLKF CClock Frequency kHz kHz108.06.0XSYNC, RSYNCFSSync Pulse Frequency %605040BCLKDCClock Duty Ratio ns50——XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW tlrDigital Input Rise Time ns50——tlfDigital Input Fall Time Transmit Sync Pulse Setting Time ns——100BCLK®XSYNC, See Fig. 1tXS ns——100XSYNC®BCLK, See Fig. 1tSX Receive Sync Pulse Setting Time ns——100BCLK®RSYNC, See Fig. 1tRS ns——100RSYNC®BCLK, See Fig. 1tSR ms——1 BCLKXSYNC, RSYNC, See Fig. 1tWSHHigh Level Sync Pulse Width ms——1 BCLKXSYNC, RSYNC, See Fig. 1tWSLLow Level Sync Pulse Width ns——100See Timing DiagramtDSPCMIN Setup Time ns——100See Timing DiagramtDHPCMIN Hold Time kW——0.5Pull-up resistorRDL pF100———CDL Digital Output Load mV+100—–100Transmit gain stage, Gain = 1Voff mV+10—–10Transmit gain stage, Gain = 10Analog Input Allowable DC Offset ns1000——XSYNC, RSYNC, BCLK—Allowable Jitter Width Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition Rating –0.3 to +7 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –55 to +150 Unit V V V

¡ Semiconductor MSM7717-01/02/03

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics Parameter Power Supply Current High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance Symbol IDD1 IDD3 IDD2 VIH VIL IIH IIL VOL IO Condition Operating mode Power-saving mode, PDN = 1, BCLK or XSYNC ® OFF Power-down mode, PDN = 0, BCLK OFF Pull-up resistor > 500 W Min. 0.45´V DD 0.0 0.0 Typ. 2.0 0.005 0.2 Max. 8.0 0.05 V DD 0.16´VDD 2.0 0.5 0.4 Unit mA mA mA V V mA mA V mA CIN — —5— p F (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) No signal — 6.5 10.0 VDD = 3.8 V VDD = 3.0 V XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW XSYNC, RSYNC, BCLK, PCMIN, PDN, ALAW

¡ Semiconductor MSM7717-01/02/03 Transmit Analog Interface Characteristics Receive Analog Interface Characteristics Input Resistance Output Load Resistance Output Load Capacitance RINPW RLVF RLAO CLVF CLAO PWI 10 0.6 MW kW kW pF pF VFRO with respect to SG Output Amplitude Offset Voltage VOVF VOAO VOSVF VOSAO –1.0 –1.0 –100 –100 +1.0 +1.0 +100 +100 V V mV mV VFRO, R L = 20 kW with respect to SG AOUT+, AOUT– (each) with respect to SG VFRO AOUT+, AOUT– AOUT+, AOUT–, RL = 0.6 kW with respect to SG VFRO with respect to SG AOUT+, AOUT–, Gain = 1 with respect to SG Parameter Symbol Condition Min. Typ. Max. Unit (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage R INX RLGX CLGX VOGX VOSGX AIN+, AIN– Gain = 1 –0.7 –20 +0.7 +20 MW kW pF V mV GSX with respect to SG Parameter Symbol Condition Min. Typ. Max. Unit (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C)

¡ Semiconductor MSM7717-01/02/03 AC Characteristics Condition (FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Symbol Min. Typ. Max. Unit Transmit Frequency Response Loss T1 Level (dBm0) 60 20 26 — Freq. (Hz) Loss T2 300 –0.15 +0.07 +0.2 Loss T3 1020 Reference dB0Loss T4 2020 –0.15 –0.01 +0.2 Loss T5 3000 –0.15 +0.15 +0.2 Loss T6 3400 0 0.4 0.8 Receive Frequency Response Loss R1 300 –0.15 –0.03 +0.2 Loss R2 1020 Reference Loss R3 2020 –0.15 –0.02 +0.2 dB0 Loss R4 3000 –0.15 +0.15 +0.25 Loss R5 3400 0 0.56 0.8 SD T1 35 43 — 3 SD T2 35 41 — 0 SD T3 35 38 — –30 Transmit Signal to Distortion Ratio 1020 dBSD T4 28 30 — –40 SD T5 23 25 — –45 SD R1 36 43 — 3 SD R2 36 41 — 0 SD R3 36 40 — –30 Receive Signal to Distortion Ratio 1020 dB SD R4 33.5 —–40 SD R5 30 —–45 Transmit Gain Tracking GT T2 Reference GT T3 1020 –0.3 0 +0.3 dB–40 –10 –50 –55 Receive Gain Tracking GT R2 Reference GT R3 1020 –0.3 –0.02 +0.3 dB –40 –10 –50 –55 *1 Psophometric filter is used. *2 Upper columns are specified for the m-law, lower for the A-law.

¡ Semiconductor MSM7717-01/02/03 AC Characteristics (Continued) Absolute Level (Initial Difference) Nidle T —— –72.5 –70.5 –68 dBm0p Nidle R — –76.5 AV T 0.338 0.35 0.362 AV R 0.483 0.5 0.518 Vrms 1020 Absolute Delay AV Rt –0.2 — +0.2 Td 1020 — — 0.6 ms 0 A to A BCLK = 64 kHz Transmit Group Delay tGD T1 — 0.19 0.75 tGD T2 — 0.11 0.35 tGD T3 — 0.02 0.1250 tGD T4 — 0.05 0.125 ms*5 0.07tGD T5 — 0.75 Receive Group Delay — 0.00 0.75 0.00 — 0.00 0.125 ms0 — 0.09 0.125 — 0.12 0.75 — –74 Idle Channel Noise — AIN = SG *1 *3 dB dB VDD = 3.0 V Ta = 25°C VDD = 2.7 V to 3.8 V Ta = –30 to 85°C Absolute Level (Deviation of Temperature and Power) 500 600 1000 2600 2800 Crosstalk Attenuation C R T 7 58 0— CR R 76 1020 dB 0 TRANS ® RECV RECV ® TRANS tGD R1 tGD R2 tGD R3 tGD R4 tGD R5 500 600 1000 2600 2800 70 — — 0.35 Condition (FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Symbol Min. Typ. Max. UnitLevel (dBm0) Freq. (Hz) *1 Psophometric filter is used. *2 Upper column is specified for the m-law, lower for the A-law. *3 Input "0" code to PCMIN. *4 AVR is defined at VFRO output. *5 With respect to minimum value of the group delay distortion

¡ Semiconductor MSM7717-01/02/03 AC Characteristics (Continued) *6 Measured under idle channel noise. DIS 4.6 kHz to 30 32 — dB Digital Output Delay Time tSD 20 — 200 tXD1 20 — 200 tXD2 20 — 200 tXD3 20 — 200 ns Discrimination 0 0 to 4000 Hz CL = 100 pF + 1 LSTTL S 300 to — –37.5 –35 dBm0Out-of-band Spurious 0 4.6 kHz to IMD fa = 470 — –52 –35 dBm0Intermodulation Distortion –4 2fa – fd PSR T 0 to —3 0— d BPower Supply Noise Rejection Ratio 50 mV PP PSR R 72 kHz 3400 fd = 320 50 kHz 100 kHz Condition (FS = 8 kHz, VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Symbol Min. Typ. Max. UnitLevel (dBm0) Freq. (Hz)

¡ Semiconductor MSM7717-01/02/03 TIMING DIAGRAM PCM Data Input/Output Timing BCLK 123456789 1 0 XSYNC PCMOUT D2 D3 D4 D5 D6 D7 D8MSD tXS tSX tWSL tWSH tSDtXD1 tXD2 tXD3 BCLK RSYNC PCMIN MSD tRS tSR tDS tDH Transmit Timing Receive Timing /,/#01 When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1. When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD. /,/#01 D2 D3 D4 D5 D6 D7 D8 tWSL 123456789 1 0 tWSH Figure 1 Basic Timing

¡ Semiconductor MSM7717-01/02/03 APPLICATION CIRCUIT * These output signals have amplitudes above and below the offset level of V DD/2. FREQUENCY CHARACTERISTICS ADJUSTMENT CIRCUIT AIN– Transmit frequency characteristic Adjustment determined by C1, C2, R1 and R2 Receive frequency characteristic Adjustment determined by C3, C4, R3 and R4 GSX AIN+ SG AOUT+ AOUT– PWI VFRO R4C4 C1M R3 C3 Microphone amp MSM7717-XX PCMOUT XSYNC AIN– GSX AIN+ 1 mF 0.1 mF PCM signal output 8 kHz SYNC signal input PCM shift clock input PCM data Control of companding law 1: A-law 0: m-law 0.1 mF 51 kW Analog input AOUT+ SG RSYNC BCLK PCMIN ALAW DG AOUT– PWI VFRO SGC AG V DD 0 V +3 V Analog inverted output* 51 kW 10 mF MSM7717-01 PDN 0 to 10 W Analog output* +3 V Power down control input 1: Normal operation 0: Power down

¡ Semiconductor MSM7717-01/02/03 NOTES ON USE

• To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device.
• Keep the voltage on the V DD pin not lower than –0.3 V even instantaneously to avoid latch- up that may otherwise occur when power is turned on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.

¡ Semiconductor MSM7717-01/02/03 (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). SOP24-P-430-1.27-K Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Mirror finish

¡ Semiconductor MSM7717-01/02/03 (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). SSOP20-P-250-0.95-K Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.18 TYP. Mirror finish