MSM7704-01 OKI | Alldatasheet

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¡ Semiconductor MSM7704-01/02/03 ¡ Semiconductor MSM7704-01/02/03 2ch Single Rail CODEC GENERAL DESCRIPTION The MSM7704-01/7704-02/7704-03 are two-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices contain two-channel AD/DA converters in a single chip and achieve a reduced footprint and a reduced number of external components. The MSM7704-01/7704-02/7704-03 are best suited for an analog interface to an echo canceller DSP used in digital telephone terminals, digital PABXs, and hands free terminals.

FEATURES

  • Single power supply: +2.7 V to +3.8 V
  • Power consumption Operating mode: 30 mW Typ. 50 mW Max. Power-saving mode: 3 mW Typ. 6 mW Max. Power-down mode: 0.03 mW Typ. 0.3 mW Max.
  • ITU-T Companding law MSM7704-01: m/A-law pin-selectable MSM7704-02: m-law MSM7704-03: A-law
  • Built-in PLL eliminates a master clock
  • The PCM interface can be switched between 2 channel serial/parallel
  • Transmission clock: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544/200 kHz (During 2 channel serial mode, the 64 and 96 kHz clocks are disabled)
  • Adjustable transmit gain
  • Built-in reference voltage supply
  • Analog output can directly drive a 1.2 kW load
  • Package: 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7704-01GS-K) (Product name : MSM7704-02GS-K) (Product name : MSM7704-03GS-K) E2U0021-28-81 This version: Aug. 1998 Previous version: Nov. 1996

¡ Semiconductor MSM7704-01/02/03 BLOCK DIAGRAM AIN1 GSX1 AIN2 GSX2 AOUT1 AOUT2 SGC XSYNC DOUT1 DOUT2 BCLK RSYNC (ALAW) CHPS DIN1 DIN2 PDN V DD AG DG – RC LPF 8th BPF RC LPF 8th BPF 5th LPF S&H 5th LPF S&H SG GEN VR GEN AD CONV. TCONT AUTO ZERO DA CONV. PLL RTIM RCONT PWD Logic

¡ Semiconductor MSM7704-01/02/03 PIN CONFIGURATION (TOP VIEW) 12 13 24SGC AOUT2 NC PDN CHPS VDD DG RSYNC AIN2 GSX2 GSX1 AIN1 BCLK XSYNC NC : No connect pin DIN2 DIN1 DOUT2 DOUT1 AOUT1 NC AG NC NC (ALAW)* 24-Pin Plastic SOP * The ALAW pin is only applied to the MSM7704-01GS-K.

¡ Semiconductor MSM7704-01/02/03 PIN AND FUNCTIONAL DESCRIPTIONS AIN1, AIN2, GSX1, GSX2 AIN1 and AIN2 are the transmit analog inputs for channels 1 and 2. GSX1 and GSX2 are the transmit level adjustments for channels 1 and 2. AIN1 and AIN2 are inverting inputs for the op-amps. GSX1 and GSX2 are connected to the outputs of the op-amps and are used to adjust the level, as shown below. When AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving mode and power down mode, the GSX1 and GSX2 outputs are in high impedance state. AOUT1, AOUT2 AOUT1 is the receive analog output for channel 1 and AOUT2 is used for channel 2. The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage (SG : 1/2 VDD). When the digital signal of +3 dBmO is input to DIN1 and DIN2, it can drive a load of 1.2 kW or more. During power saving mode, or power down mode, these outputs are at the voltage level of SG with a high impedance. VDD Power supply for +3 V. A power supply for an analog circuit in the system to which the device is applied should be used. A bypass capacitor of 0.1 mF to 1 mF with excellent high-frequency characteristics and a capacitor of 10 mF to 20 mF should be connected between this pin and the AG pin if needed. CH1 Analog Input + CH2 Analog Input AIN1C1 R1 R2 GSX1 AIN2C2 R3 R4 GSX2 CH1 Gain Gain = R2/R1 £ 10 R1: Variable R2 > 20 kW CH2 Gain Gain = R4/R3 £ 10 R3: Variable R4 > 20 kW

¡ Semiconductor MSM7704-01/02/03 DIN1 PCM signal input for channel 1 when the parallel mode is selected. D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is output from AOUT1 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is not used and should be connected to GND (0 V). DIN2 PCM signal input for channel 2 when the parallel mode is selected. D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is output from AOUT2 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is used for the 2ch multiplexed PCM signal input. BCLK Shift clock signal input for the DIN1, DIN2, DOUT1, and DOUT2 signals. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048, or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. RSYNC Receive synchronizing signal input. Eight bits PCM data required are selected from a series of PCM signal to the DIN1 and DIN2 pins by the receive synchronizing signal. All timing signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK (generated from the same clock source as BCLK). The frequency should be 8 kHz –50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, unless the frequency characteristics of the system used are strictly specified, this device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in the data sheet are not guaranteed.

¡ Semiconductor MSM7704-01/02/03 XSYNC Transmit synchronizing signal input. PCM output signal from the DOUT1 and DOUT2 pins is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz –50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, unless the frequency characteristics of the system used are strictly specified, this device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving state. DOUT1 PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is configured to be the output of serial multiplexed 2ch PCM signal. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7704-03 (A-law) outputs the character signal, inverting the even bits. Input/Output Level +Full scale –Full scale PCMIN/PCMOUT MSM7704-02 (m-law) MSD 1000 0000 1111 1111 0111 1111 0000 0000 MSM7704-03 (A-law) MSD 1010 1010 1101 0101 0101 0101 0010 1010

¡ Semiconductor MSM7704-01/02/03 DOUT2 PCM signal output for channel 2 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, at the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is left open. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7704-03 (A-law) outputs the character signal inverting the even bits. CHPS Control signal input for the mode selection of PCM input and output. When this signal is at a logic "1" level, the PCM input and output are in the parallel mode. The PCM data of CH1 and CH2 is input to DIN1 and DIN2 and output from DOUT1 and DOUT2 with the same timing. When this signal is at a logic "0" level, the PCM input and output are in the serial mode. The PCM data of CH1 and CH2 is input to DIN2 and output from DOUT1 as time division multiplexed data. The parallel mode is conveniently applied to the digital interface to the echo canceller device, and the serial mode is applied to the digital interface to PCM multiplexer's for PABXs. PDN Power down control signal. When PDN is at a logic "0" level, both transmit and receive circuits are in power down state. AG Analog signal ground. DG Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground.

¡ Semiconductor MSM7704-01/02/03 SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Provides only for the MSM7704-01GS-K. The CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since this pin is internally pulled down.

¡ Semiconductor MSM7704-01/02/03 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition Rating 0 to 7 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –55 to +150 Unit V V V RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supply Voltage Analog Input Voltage Digital Input High Voltage Digital Input Low Voltage Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Sync Pulse Width DIN Set-up Time DIN Hold Time Digital Output Load Analog Input Allowable DC Offset Allowable Jitter Width V DD VAIN VIH VIL FC FS DC tIr tIf tXS tWS tDS tDH RDL Voff tSX tRS tSR Condition Gain = 1 XSYNC, RSYNC, BCLK, DIN1, DIN2, PDN, CHPS BCLK = (eliminates 64, 96 kHz, when 2ch serial mode) XSYNC, RSYNC BCLK XSYNC, RSYNC, BCLK, DIN1, DIN2, PDN, CHPS BCLK®XSYNC, See Timing Diagram XSYNC, RSYNC DIN1, DIN2 DIN1, DIN2 Pull-up resistor, DOUT1, DOUT2 Transmit gain stage, Gain = 10 XSYNC®BCLK, See Timing Diagram BCLK®RSYNC, See Timing Diagram RSYNC®BCLK, See Timing Diagram Transmit gain stage, Gain = 1 XSYNC, RSYNC DOUT1, DOUT2 Min. Typ. Max. Unit 2.7 0.45 ´ VDD 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 100

1 BCLK

0.5 VDD/2 –10 100 100 100 VDD/2 –100 3.0 8.0 3.8 1.4 V DD 0.16 ´ VDD 100 VDD/2 +10 VDD/2 +100 500 100 V VPP V V kHz ns ns ns ms ns ns kW mV ns ns ns mV ns pF kHz C DL Voltage must be fixed Operating Temperature Ta — +25 °C–30 +85

¡ Semiconductor MSM7704-01/02/03

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics Parameter Power Supply Current Input High Voltage Input Low Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance Symbol IDD1 IDD2 IDD3 VIH VIL IIH IIL VOL IO Condition Operating mode, No signal Power-save mode, PDN = 1, XSYNC or BCLK OFF Power-down mode, PDN = 0 Digital input is at 0 V Pull-up resistance > 500 W Min. 0.0 0.0 Typ. 10.0 1.0 0.01 0.2 Max. 14.0 4.0 0.05 V DD 2.0 0.5 0.4 Unit mA mA mA V V mA mA V mA CIN — —5— p F (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) 0.45 ´ VDD 0.16 ´ VDD Transmit Analog Interface Characteristics Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage R INX RLGX CLGX VOGX VOSGX AIN1, AIN2 Gain = 1 –0.7 –20 +0.7 +20 MW kW pF V mV GSX1, GSX2 with respect to SG Parameter Symbol Condition Min. Typ. Max. Unit (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Receive Analog Interface Characteristics Output Load Resistance Output Load Capacitance RLAO CLAO 1.2 kW pF Output Amplitude Offset Voltage VOAO VOSAO –100 +100 V mV AOUT1, AOUT2 (each) with AOUT1, AOUT2 AOUT1, AOUT2, RL = 1.2 kW AOUT1, AOUT2 with respect Parameter Symbol Condition Min. Typ. Max. Unit (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) respect to SG with respect to SG to SG

¡ Semiconductor MSM7704-01/02/03 AC Characteristics Condition (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Symbol Min. Typ. Max. Unit Transmit Frequency Response Loss T1 Level (dBm0) 60 20 26 — dB Freq. (Hz) Loss T2 300 –0.15 +0.07 +0.20 dB Loss T3 1020 Reference dB0Loss T4 2020 –0.15 –0.04 +0.20 dB Loss T5 3000 –0.15 +0.06 +0.20 dB Loss T6 3400 0 0.4 0.80 dB Receive Frequency Response Loss R1 300 –0.15 –0.03 +0.20 dB Loss R2 1020 Reference dB Loss R3 2020 –0.15 +0.02 +0.20 dB0 Loss R4 3000 –0.15 +0.12 +0.20 dB Loss R5 3400 0.0 0.46 0.80 dB SD T1 35 43 — 3 SD T2 35 41 — 0 SD T3 35 38 — –30Transmit Signal to Distortion Ratio 1020 dB SD T4 28 31.5 — –40 *1 SD T5 23 27 — –45 SD R1 36 43 — 3 SD R2 36 41 — 0 SD R3 36 40 — –30Receive Signal to Distortion Ratio 1020 dB SD R4 30 33.5 — –40 *1 SD R5 25 30 — –45 Transmit Gain Tracking GT T2 Reference GT T3 1020 –0.3 0 +0.3 dB–40 –10 –50 –55 Receive Gain Tracking GT R2 Reference GT R3 1020 –0.4 +0.2 +0.4 –40 –10 –50 –55 +0.20 +0.3 *1 Psophometric filter is used *2 Upper is specified for the m-law, lower for the A-law

¡ Semiconductor MSM7704-01/02/03 AC Characteristics (Continued) Absolute Level (Initial Difference) Nidle T —— –73.5 –71.5 –69 –68 dBmOp Nidle R — –76 AV T 0.338 0.350 0.362 AV R 0.483 0.500 0.518 Vrms 1020 Absolute Delay AV Rt –0.2 — +0.2 Td 1020 — — 0.60 ms0 A to A BCLK = 64 kHz Transmit Group Delay tgd T1 — 0.19 0.75 tgd T2 — 0.11 0.35 tgd T3 — 0.02 0.125 0 tgd T4 — 0.05 0.125 ms 0.07tgd T5 — 0.75 Receive Group Delay — 0.00 0.75 0.00 — 0.00 0.125 ms0 — 0.09 0.125 — 0.12 0.75 — –74 Idle Channel Noise — AIN = SG *1 *3 *1 *2 dB dB VDD = 3.0 V Ta = 25°C VDD = 2.7 V to 3.8 V Ta = –30 to +85°C *4 Absolute Level (Deviation of Temperature and Power) 500 600 1000 2600 2800 Crosstalk Attenuation C R T 7 58 0— CR R 76 1020 dB 0 TRANS ® RECV RECV ® TRANS tgd R1 tgd R2 tgd R3 tgd R4 tgd R5 500 600 1000 2600 2800 70 — — 0.35 Condition (VDD =2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Symbol Min. Typ. Max. UnitLevel (dBm0) Freq. (Hz) CR CH 80 CH to CH 75 — *1 Psophometric filter is used *2 Upper is specified for the m-law, lower for the A-law *3 Input "0" code to PCMIN *4 AVT is defined between GSX and DOUT and AVR between DIN and AOUT *5 Minimum value of the group delay distortion

¡ Semiconductor MSM7704-01/02/03 AC Characteristics (Continued) DIS 4.6 kHz to 30 32 — dB Digital Output Delay Time tSD 20 — 200 tXD1 20 — 200 tXD2 20 — 200 tXD3 20 — 200 ns Discrimination 0 0 to 4000 Hz CL = 100 pF + 1 LSTTL S 300 to — –37.5 –35 dBmOOut-of-band Spurious 0 4.6 kHz to IMD fa = 470 — –52 –35 dBmOIntermodulation Distortion –4 2fa – fb PSR T 0 to —3 0— d BPower Supply Noise Rejection Ratio 50 mV PP PSR R 72 kHz 3400 fb = 320 50 kHz 100 kHz Condition (VDD = 2.7 V to 3.8 V, Ta = –30°C to +85°C) Parameter Symbol Min. Typ. Max. UnitLevel (dBm0) Freq. (Hz) *6 The measurement under idle channel noise

¡ Semiconductor MSM7704-01/02/03 APPLICATION CIRCUIT Example of Basic Connection (PCM Serial Mode Operation) PCM Parallel Mode CH1 Analog Input CH1 Analog Output CH2 Analog Input CH2 Analog Output 0 V +3 V 0.1 mF 10 mF1 mF+ AIN1 CH1 PCM Signal Output GSX1 AOUT1 AIN2 GSX2 AOUT2 SGC AG DG DOUT1 DOUT2 DIN2 BCLK XSYNC PDN DIN1 RSYNC CHPS V DD +3 V CH2 PCM Signal Input Bit Clock Input Sync Pulse Input Power Down Control Input 1 : Operation 0 : Power Down +3 V MSM7704 CH2 PCM Signal Output CH1 PCM Signal Input 0 to 10W 0 V +3 V 0.1 mF 10 mF1 mF AIN1 GSX1 AOUT1 AIN2 GSX2 AOUT2 SGC AG DG DOUT1 DOUT2 DIN2 BCLK XSYNC PDN DIN1 RSYNC CHPS VDD +3 V 1 kW 0 V 0 V MSM7704 0 to 10 W CH1 Analog Input CH1 Analog Output CH2 Analog Input CH2 Analog Output 2ch Multiplex PCM Signal Output(Open) 2ch Multiplex PCM Signal Intput Bit Clock Input Sync Pulse Input Power Down Control Input 1: Operation 0: Power Down The AOUT1 and AOUT2 output signals swing –1.0 V above and below the offset level of VDD/

¡ Semiconductor MSM7704-01/02/03 RECOMMENDATIONS FOR ACTUAL DESIGN

  • To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins.
  • Connect the AG pin and the DG pin each other as close as possible. Connect to the system ground with low impedance.
  • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, use the short lead type socket.
  • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device.
  • Keep the voltage on the V DD pin not lower than –0.3 V even instantaneously to avoid latch- up phenomenon when turning the power on.
  • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.

¡ Semiconductor MSM7704-01/02/03 (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). SOP24-P-430-1.27-K Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Mirror finish