MSM7583

MSM7583 OKI | Alldatasheet

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Technical content

MSM7583¡ Semiconductor GENERAL DESCRIPTION The MSM7583 is a CMOS IC for the p/4 shift QPSK modem developed for the digital cordless telephone systems. The device, which contains one system of modulator and two systems of demodulater, is optimized for applications for cell stations in a cordless telephone system.

FEATURES

• Single +5 V Power Supply: 4.5 V to 5.5 V (Modulator Block)
• Built in Root Nyquist Filter for Baseband Limitting (50% Roll-off)
• Ramp Bit for Burst Signal Rise-up (Fall-down) : 2 Symbols
• Built-in D/A converters for Analog Outputs of Quadrature Signal I/Q Components and I + Q 22 (Analog) Power Envelope Output.
• Differential I/Q Analog Output Type
• I/Q Output, DC Offset/Amplitude Adjustable (Demodulator Block)
• Built-in Diversity-corresponding Demodulation Circuit: 2 Systems
• Full Digital p/4 Shift QPSK Demodulation System
• Input IF Signal Frequency Selectable: 1.2/10.7/10.75/10.8 MHz
• Built-in Clock Recovery: 4 Circuits
• Transmit/Receive Independent Power-down Control capability
• Built-in Precise Analog Voltage Reference
• MCU Serial Interface for Mode Setting and Built-in Test Circuit
• Test Modes: Eye Pattern/AFC Compensating Signal/Phase Detection Signal Monitoring Capability
• Transmission Speed: 384 kbps
• Low Power Consumption Operating Mode: 16 mA Typ./Modulator (V DD = 5.0 V) 28 mA Typ./Demodulator (VDD = 5.0 V) Whole Power-down Mode: 0.03 mA Typ. (VDD = 5.0 V)
• Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK)(Product name : MSM7583GS-BK) ¡ Semiconductor MSM7583 p/4 Shift QPSK MODEM E2U0036-28-81 This version: Aug. 1998 Previous version: Nov. 1996

MSM7583¡ Semiconductor BLOCK DIAGRAM SL11 SL21 SL31 SL41 SL11 SL21 SL31 SL41 D E C D E C S E L DPLL S E L DPLL S E L SL41 SL41 SL41 SL41 SL42 SL32 SL22 SL12 S E L DEN EXCK DIN DOUT VDD DGND AGND IFIN1 MCK IFCK PDN0 PDN1 PDN2 RESET IFN2 BST0 ENV SG IFSEL0 (From CR) IFSEL1 (From CR) To each block To each block AFC DecisionPhase Detector Delay Detector Control Register DC Offset Adjust DC Offset Adjust VREF LPF LPF LPF D/A D/A D/A I output gain adjust Q output gain adjust To internal SG To monitor output of each block TEST1, TEST0 (From CR) PLL AFC S/P MAPPING TXCO TXCI TXW TXD TXCEL (From CR) 384 kHZ SLS11 SLS21 AFC1 RXD1 RXSC1 RXC1 RCW1 RPR1 RXD0 RXC0 RXSC0 RXSEL RPR2 RCW2 RXCS2 RXC2 RXD2 AFC2 SLS21 SLS22 Root Nyquist LPF S E L

3.84 MHz

DecisionPhase Detector Delay Detector

MSM7583¡ Semiconductor PIN CONFIGURATION (TOP VIEW) 16 33 64-Pin Plastic QFP NC RPR2 AFC2 RCW2 RPR1 AFC1 RCW1 RXSC0 RXC0 RXD0 RXSEL RXSC2 RXC2 RXD2 NC PDN2 BSTO TXW TXD TXCO TXCI NC NC NC NC NC NC NC NC NC NC IFCK MCK DGND IFIN2 DGND IFIN1 DGND VDD DOUT DIN EXCK DEN RESET PDN0 PDN1 NC SLS22 SLS12 RXSC1 RXC1 RXD1 SLS21 SLS11 VDD ENV SG AGND NC : No connect pin

MSM7583¡ Semiconductor PIN AND FUNCTIONAL DESCRIPTIONS TXD Transmit data input for 384 kbps. TXCI Transmit clock input. When the control register CR0 - B6 is “0”, a 384 kHz clock pulse synchronous with TXD should be input to this pin. This clock pulse should be continuous because this device uses APLL to generate internal clock pulses. When CR0 - B6 is “1”, a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz clock pulse is applied to TXCI, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the TXCI input by 10. The transmit data, synchronous 384 kHz clock pulse, should be input to the TXD. In this case the device does not use APLL, and the 3.84 MHz clock pulse need not be continuous. (Refer to Fig. 1.) TXCO Transmit clock output. When CR0 - B6 is “0”, TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring purposes. When CR0 - B6 is “1”, this pin outputs a 384 kHz clock pulse generated by dividing the TXCI input by 10. (Refer to Fig. 1.) TXW Transmit data window signal input. The transmit timing signal for the burst data is input to the device through this pin. If TXW pin is “1”, modulation data is output. (Refer to Fig. 1.) I+, I– Quadrature modulation signal I component differential analog outputs. The level of the outputs is 500 mVpp with 1.6 Vdc as center value. The output pin load conditions are: R ‡ 10 kW, C £ 20 pF. The gain of these pins can be adjusted using the control registers CR1 - B7 to B4, and the offset voltage at the I– pin can be adjusted using CR3 - B7 to B3. Q+, Q– Quadrature modulation signal Q component differential analog outputs. The level of the outputs is 500 mVpp with 1.6 Vdc as center value. The output pin load conditions are: R ‡ 10 kW , C £ 20 pF. The gain of these pins can be adjusted using the control registers CR1 - B3 to B0, and the offset voltage at the Q– pin can be adjusted using CR4 - B7 to B3.

MSM7583¡ Semiconductor ENV Quadrature modulation signal envelope ( I + Q 22 ) output. Its output level is 500 mVpp with 1.6 Vdc as a center value. The output pin load conditions are: R ‡ 10 kW , C £ 20 pF. The gain of this output can be adjusted using the control registers CR2 - B7 to B4. This pin is also used to monitor eye pattern, AFC compensating signal, and phase detection of the demodulator block during the test mode. Refer to the description of the control register for details. BSTO Modulation burst window signal output. The burst position for the I/Q baseband modulation output is output. (Refer to Fig. 1.) Figure 1 Transmitter Timing Diagram D0 D1 D13D12D11D10 D2 D3 D4 D5 D6 D7 D8 D9 Dn-1 DnTXD TXCI (384 kHz) TXW TXCO (384 kHz) I, Q 2 symbols (1) CR0 - B6 ="0". D0 D1 D13D12D11D10 D2 D3 D4 D5 D6 D7 D8 D9 Dn-1 DnTXD TXCI (3.84 MHz) TXW TXCO (384 kHz) I, Q Delay of 6.25 symbols 2 symbols 2 symbols Delay of 6.25 symbols Ramp fall-down Delay of 6.25 symbols Delay of 6.25 symbols 12 89 1 0 N N+1 N+2 N+16 N+17 N+18 N+19TXCI (384 kHz) TXW BSTO Ramp rise-up Ramp rise-up (2) CR0 - B6 ="1". 2 symbols Ramp fall-down

MSM7583¡ Semiconductor SG Internal reference voltage output. The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and the AGND pin. The external SG voltage, if necessary should be used via buffer. RESET Control register reset. When this pin is set to "0", the register is reset to the initial value. The reset signal input width is 200 ns or more. PDN0, PDN1, PDN2 Inputs for power-down control. PDN0 controls the standby/communication modes, PDN1 controls the modulator, and PDN2 controls the demodulator. Refer to Table 1 for details. Table 1 Power Down Control V DD +5 V power supply voltage. AGND Analog signal ground. DGND Digital signal ground. AGND and DGND are not connected in the device. This pin should be tied to the AGND pin on the PCB as close as possible from the device. AGND and DGND should be connected as close as prossible on the PC board. PDN2 All power-down. Standby Mode PDN1 Modulator power is off (VREF and PLL power is also off). Demodulator power is on. Modulator power is off (VREF and PLL power is on). I and Q outputs are in a high-impedance state. Only demodulator clock recovery block power is on. Modulator power is on. Only demodulator clock recovery block power is on. Modulator power is off (VREF and PLL power is on). I and Q outputs are in a high-impedance state. Demodulator power is on. Modulator power is on. Demodulator power is on. Mode A Mode PDN0 Function Communication Mode Mode B0—1 Mode C100 Mode D110 Mode E101 Mode F111

MSM7583¡ Semiconductor MCK Master clock input. The clock frequency is 19.2 MHz. IFIN1, IFIN2 Modulated signal inputs for the demodulator block. Select the IF frequency from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz based on CR0 - B4 and B3. IFIN1 is for Channel 1, and IFIN2 for Channel 2. IFCK Clock signal input for demodulator block IF frequency (10.7 MHz or 10.75 MHz). MHz should be supplied. When the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to “0” or “1”. (Refer to Fig. 2.) X1, X2 Crystal oscillator connection pins. When IFIN = 10.7 MHz or 10.75 MHz IFCKX2X1 MSM7583 When IFIN = 1.2 MHz or 10.8 MHz IFCKX2X1 MSM7583 19.0222 MHz or 19.1111 MHz Figure 2 How to Use IFCK, X1, and X2

MSM7583¡ Semiconductor RXD1, RXC1, RXSC1 Channel 1 receive data, receive clock, and receive symbol clock output pins. During power-on, these output pins are at the output level of the clock recovery circuit selected by a combination of SLS11 and SLS21 (described later). (Refer to Fig. 3.) RXD2, RXC2, RXSC2 Channel 2 receive data, receive clock, and receive symbol clock output pins. During power-on, these output pins are at the output level of the clock recovery circuit selected by a combination of SLS12 and SLS22 (described later). (Refer to Fig. 3.) SLS11, SLS21, SLS12, SLS22 Receiver slot select signal pins of Channel 1 (SLS11, SLS21) and Channel 2 (SLS12, SLS22). The MSM7583 has four sets of clock recovery circuits and four AFC information storage registers. One of the sets is selected according to a combination of the signals at these pins. (Refer to Fig. 3.) Channel 1 (SLS21, SLS11) = (0, 0): Slot 1, (0, 1): Slot 2 (1, 0): Slot 3, (1, 1): Slot 4 Channel 2 (SLS22, SLS12) = (0, 0): Slot 1, (0, 1): Slot 2 (1, 0): Slot 3, (1, 1): Slot 4 RXD1 (RXD2) RXC1 (RXC2) SLS21 (SLS22) The recovery data and clock pulse are selected asynchronously by the SLS signals. RXSC1 (RXSC2) SLS11 (SLS12) Figure 3 RXD, RXC, and RXSC Timing Diagram RXD0, RXC0, RXSC0 Receive data, receive clock, and receive symbol clock outputs. These pins are at the output level selected by RXSEL (described below).

MSM7583¡ Semiconductor RXSEL Receive data, receive clock, and receive symbol clock select signal. If this pin is set to "0", the output levels of Channel 1 RXD1, RXC1, and RXSC1 are selected to be output to RXD0, RXC0, and RXSC0. If this pin is set to "1", the output levels of Channel 2 RXD2, RXC2, and RXSC2 are selected to be output to RXD0, RXC0, and RXSC0. Note that a hazard may sometime occur in RXDO, RXCO, and RXSCO because RXSEL selects asynchronously. RPR1, RPR2 High-speed phase clock control signal input pin for the clock recovery circuit. When each of the pins is “1”, the clock recovery circuit starts in the high-speed phase clock mode. When the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically. When each of the pins is “0”, the circuit is always in the low- speed phase clock mode. RPR1 is for Channel 1, and RPR2 for Channel 2. AFC1, AFC2 AFC operation range specification signal inputs. As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to “1”. AFC operation starts at a certain period after the AFC information is reset. When RPR is set to “1”, an average number of times that AFC sets to on is low. When RPR is “0”, it is high. When AFC is “0”, frequency error is not calculated, but the frequency is corrected using an error that is held. AFC1 is for Channel 1, and AFC2 for Channel 2. RCW1, RCW2 Clock recovery circuit operation ON/OFF control signal inputs. When this pin is “0”, DPLL does not make any phase corrections. RCW1 is for Channel 1, and RCW2 for Channel 2. Figure 4 AFC Control Timing Diagram AFC RPR (CASE1) AFC information is maintained. AFC information is reset. Average number of times AFC is low. Average number of times AFC is high. AFC RPR (CASE2) AFC information is maintained. “0” The clock recovery circuit starts with the previous AFC information. Average number of times AFC is high.

MSM7583¡ Semiconductor DEN, EXCK, DIN, DOUT Serial control ports for the microprocessor interface. The MSM7583 contains a 6-byte control register. An external CPU uses these pins to read data from and write data to the control register. DEN is the "Enable" signal input pin. EXCK is a data shift clock pulse input pin. DIN is an address and data input pin. DOUT is a data output pin. Figure 5 shows an input/output timing diagram. /#03/#04 High Impedance High Impedance (a) Data Write Timing Diagram (b) Data Read Timing Diagram DEN W EXCK DIN A2 DOUT A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 R A 2A 1A 0 B7 B6 B5 B4 B3 B2 B1 B0 DEN EXCK DIN DOUT /#06/#07/#06/#07 /,/#01/#02 Figure 5 MCU Interface Input/Output Timing Diagram

MSM7583¡ Semiconductor The register map is shown below Table 2 Control Register Map Register A2 A1 A0 Address Data B7 B6 B5 B4 B3 B2 B1 B0 R/W R/WCR0 0 0 0 R/WCR1 0 0 1 R/WCR2 0 1 0 R/WCR3 0 1 1 ENVPD Ich GAIN3 ENV GAIN3 Ich Offset4 Qch Offset4 TXCSEL Ich GAIN2 ENV GAIN2 Ich Offset3 Qch Offset3 MODOFF Ich GAIN1 ENV GAIN1 Ich Offset2 Qch Offset2 IFSEL1 Ich GAIN0 ENV GAIN0 Ich Offset1 Qch Offset1 IFSEL0 Qch GAIN3 Ich Offset0 Qch Offset0 LOCAL INV1 ENVSEL Qch GAIN2 LOCAL INV0 TEST1 Qch GAIN1 TEST0 Qch GAIN0 R/WCR4 1 0 0 R/WCR5 1 0 1 ICT7 ICT6 ICT5 ICT4 ICT1 ICT0 R/W : Read/Write enable

MSM7583¡ Semiconductor ABSOLUTE MAXIMUM RATINGS Power Supply Voltage Digital Input Voltage Storage Temperature Parameter Symbol VDD VDIN TSTG Unit V V –0.3 to V DD + 0.3 –55 to +150 0 to 7 RatingCondition RECOMMENDED OPERATING CONDITIONS Parameter Symbol VDD Ta VIH VIL Unit V V V Condition Voltage must be fixed — °C MHz MHz MHz kHz MHz Max. TXCI (when CR0 - B6 = "0") Min. Typ. Power Supply Voltage Operating Temperature Input High Voltage Input Low Voltage Master Clock Frequency Modulator Input Frequency Demodulator Input Frequency Clock Duty Cycle IF Input Duty Cycle f MCK fTXC1 fTXC2 fIFCK1 fIFCK2 DCCK DCIF MCK TXCI (when CR0 - B6 = "1") IFCK (when IFIN = 10.7 MHz) IFCK (when IFIN = 10.75 MHz) MCK, IFCK, TXCI IFCK All digital input pins All digital input pins 2.2 4.5 –25 –50 ppm –50 ppm 5.5 +70 0.6 VDD +50 ppm +50 ppm +25 19.2 384 3.84 19.0222 19.1111 (VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C)

ELECTRICAL CHARACTERISTICS

V V mA mA mA Max. 2.8 Min. Typ. IDD5 IDD6 VOH VOL IIH IIL VDD 0.03 25.0 8.5 0.0 (VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) 16.0 28.0 35.0 0.06 50.0 17.0 32.0 56.0 70.0 0.4 Power Supply Current Mode A (when VDD = 5.0 V) Mode B (when VDD = 5.0 V) Mode C (when VDD = 5.0 V) Mode D (when VDD = 5.0 V) Mode E (when VDD = 5.0 V) Mode F (when VDD = 5.0 V) Output High Voltage Output Low Voltage Input Leakage Current IOH = 0.4 mA IOL = –1.6 mA

MSM7583¡ Semiconductor Analog Interface Characteristics Parameter Output Resistance Load Output Capacitance Load Output DC Voltage Level Output AC Voltage Level Symbol RLIQ CLIQ VDC1 VAC Condtion Min. 1.55 340 Typ. 1.6 360 Max. 380 Unit kW pF V mV PP I+, I–, Q+, Q–, ENV I+, I–, Q+, Q–, ENV I+, I–, Q+, Q– (TXW = 0) I+, I–, Q+, Q– (TXW = 0 continuous input) DD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) VDC2 — 1.77 VI+ (CR0 – B5 = 1) when not modulated VDC3 — 1.67 VQ+ (CR0 – B5 = 1) when not modulated VDC4 — 1.35 VENV (TXW = 0) VDC5 — 1.72 VENV (TXW = 1, CR0 – B2 = 0, TXD = 0) VDC6 — 1.63 VENV (TXW = 1, CR0 – B2 = 1, TXD = 0) Output DC Voltage Adjustment Level Range DCVL — ±45 — mV — Output AC Voltage Adjustment Level Range ACVL — ±4 — % — Out-of-band Spectrum P600 60 — — dB600 kHz detuning (*) P900 65 — — dB900 kHz detuning (*) Modulation Accuracy EVM — 1.0 3.0 % rms — Demodulator IF Input Level IFV 0.5 — V DD VPPIFIN input level IFIN Input Impedance RIF — 20 — k W— CIF — 5 — pF — SG Output Voltage VSG — 2.0 — V — SG Output Impedance RSG — 2 — k W— 1.65 Offset Voltage Difference V OFF –20 — +20 mVDifference among I+, I–, Q+, and Q– SG warm-up Time T SG — 400 — ms Modulator D/A Conversion Sampling Frequency FSDA — 1.92 — MHz— SG«AGND 0.1 mF (Rise Time to 90% of max. level.) Modulator D/A Conversion Offset Frequency F CDA — 380 — kHz— * Power attenuation at 600 kHz or 900 kHz –96 kHz as referred to two times of the power in frequency band of 0 to 96 kHz

MSM7583¡ Semiconductor Digital Interface Characteristics Transmitter Digital Input/Output Setting Time 200 — — tDS 200 — — tXD1 0 — 200 ns tXD3 0 — 200 Parameter Symbol Min. Typ. Max. Unit (VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) Other Condtion C load = 50 pF Fig. 6 ns ns ns t DH tXD2 tXD4 tM1 50 — — ns tM2 50 — — ns tM3 50 — — ns tM4 50 — — ns tM5 100 — — ns tM6 50 — — ns tM7 50 — — ns tM8 0 — 100 ns tM9 50 — — ns tM10 50 — — ns tM11 0 — 50 ns Serial Port Digital Input/Output Setting Time C load = 50 pF Fig. 8 fEXCK ——1 0 M H z— EXCKEXCK Clock Frequency tRD1 tRD2 tRS1 to tRW tRS4 Receiver Digital Input/Output Setting Time C load = 50 pF Fig. 7 0 — 200 ns 0 — 200 ns 10 — — ms 10 — — ms tSX tXS

MSM7583¡ Semiconductor TIMING DIAGRAM 1 2 3 N-2 N-1 N N+1 tDS tSX TXCI [TXCO*] (384 kHz) TXW TXD tXS tDH /,/, /,/,/,/,/,/,

123 N-2 N-1 N

(3.84 MHz) 1 23456789 1 0 tXD1 tXD2 tXD1 TXCO (384 kHz) Transmit Data Input Timing Transmit Clock (TXCO) Output Timing (when CR0 - B6 = 1) TXCI (384 kHz) 1 2 9 10 N N+1 N+16 tXD3 BSTO Transmit Burst Position Output (BSTO) Timing TXW N+17 N+18 tXD4 *[ ]: When CR0 - B6 = "1", TXCO is indicated. Figure 6 Transmit (Modulator) Digital Input/Output Timing RXC AFC RXD tRD1 tRS4tRS3 tRD2 RPR tRW RCW tRS2tRS1 SLS1 SLS2 Figure 7 Receiver (Demodulator) Digital Input/Output Timing

MSM7583¡ Semiconductor tM1 tM3 tM4 tM2 123 456 tM6 tM7 tM5 11 12 tM10 tM11 W/R A2 A1 A0 B7 tM8 B1 B0 B1 B0 tM9 DEN EXCK DIN DOUT Figure 8 Serial Control Port Interface

MSM7583¡ Semiconductor FUNCTIONAL DESCRIPTION Control Registers (1) CR0 (basic operation mode setting) CR0 ENVPD TXCSEL MODOFF IFSEL1 IFSEL2 ENVSEL TEST1 TEST0 B6 B5 B4 B3 B2 B1 B0 0000000Initial value (*) * The initial value is set when a reset signal is supplied at RESET. B7: Transmit envelope output power down control 0/Envelope output ON 1/Envelope output OFF B6: Transmit timing clock selection 0/TXCI input: 384 kHz. TXCO output: 384 kHz output from APLL Transmit data TXD is input in synchronization with the rising edge of TXCI (APLL is on.) 1/TXCI input: 3.84 MHz. TXCO output: 384 kHz (one-tenth of the TXCI frequency) Transmit data TXD is input in synchronization with the rising edge of TXCO (APLL is off.) B5: Modulation on/off control 1/modulation OFF (with phase fixed) 0/modulation ON. B4, B3: Receiver input IF frequency selection (1, 0) : 10.8 MHz B2: Transmit envelope (I 2 + Q2 or I + Q 22 ) output selection When B1, B0 is (0, 0) : 0/ I + Q 22 output 1/I2 + Q2 output When B1, B0 is other than (0, 0) : 0/Channel 1 receive monitor output 1/Channel 2 receive monitor output B1, B0: Test mode selection bits. Each monitor output is output to the transmit ENV pin. (0, 0): transmit envelope (I2 + Q2 or I + Q 22 ) output (0, 1): receiver phase detection signal output (1, 0): receiver delay detection signal output (1, 1): receiver internal AFC information output

MSM7583¡ Semiconductor (2) CR1 (I, Q gain adjustment) CR1 Ich GAIN3 Ich GAIN2 Ich GAIN1 Ich GAIN0 B6 B5 B4 B3 B2 B1 B0 0000000Initial value Qch GAIN3 Qch GAIN2 Qch GAIN1 Qch GAIN0 B7 to B4: I+/I- output gain setting, in 3 mV steps (Refer to Table 3.) B3 to B0: Q+/Q- output gain setting, in 3 mV steps (Refer to Table 3.) (3) CR2 (ENV gain adjustment) CR2 ENV GAIN3 ENV GAIN2 ENV GAIN1 ENV GAIN0 B6 B5 B4 B3 B2 B1 B0 0000000Initial value ———— B7 to B4: ENV output gain setting, in 9 mV steps (Refer to Table 3.) B3 to B0: Not used Table 3 I, Q, and ENV Output Gain Values 1.042 1.036 1.030 1.024 1.018 1.012 1.006 1.000 0.994 0.988 0.982 0.976 0.970 0.964 0.958 0.952 I and Q Amplitude (value relative to the reference B7 B6 B5 B4 CR1 CR2 ENV Amplitude (value relative to the reference 1.126 1.108 1.090 1.072 1.054 1.036 1.018 1.000 0.982 0.964 0.946 0.928 0.910 0.892 0.874 0.856

MSM7583¡ Semiconductor (4) CR3 (I– output offset voltage adjustment) CR3 Ich Offset4 Ich Offset3 Ich Offset2 Ich Offset1 B6 B5 B4 B3 B2 B1 B0 0000000Initial value Ich Offset0 ——— B7 to B3: I– output pin offset voltage adjustment (Refer to Table 4.) B2 to B0: Not used (5) CR4 (Q– output offset voltage adjustment) CR4 Qch Offset4 Qch Offset3 Qch Offset2 Qch Offset1 B6 B5 B4 B3 B2 B1 B0 0000000Initial value Qch Offset0 ——— B7 to B3: Q– output pin offset voltage adjustment (Refer to Table 4.) B2 to B0: Not used Table 4 I and Q Channel Offset Adjustment Values I and Q offset (mV) B7 B6 B5 B4 B3 +45 +42 +39 +36 +33 +30 +27 +24 +21 +18 +15 +12 CR3, CR4 I and Q offset (mV) B7 B6 B5 B4 B3 –12 –15 –18 –21 –24 –27 –30 –33 –36 –39 –42 –45 –48 CR3, CR4

MSM7583¡ Semiconductor (6) CR5 (IC test) CR5 ICT7 ICT6 ICT5 ICT4 B6 B5 B4 B3 B2 B1 B0 0000000Initial value LOCAL INV1 LOCAL INV0 ICT1 ICT0 B7 to B4: ICT7 to ICT4. Device test control bits. B3, B2 : Local inverting mode setting bits. (Used when the phase of the demodulator IF input to this device is inverted.) (1, 1) = local inverting mode (0, 0) = normal mode B1, B0 : ICT1, ICT0. Device test control bits. Note: CR5 - B7 to B4, B1, and B0 are used to test the device. They should be set to “0” during normal operation. State Transition Time Mode A Mode B Mode C Mode EMode D Mode F 1 ms PDN1 = 0 PDN2 = 1 PDN1 = 0 PDN2 = 0 5 ms 5 ms40 ms PDN1 = 0 PDN2 = 1 PDN1 = 1 PDN2 = 0 5 ms 40 ms PDN1 = 0 PDN2 = 0 PDN1 = 1 PDN2 = 1 Standby mode (PDN0 = 0) Communication mode (PDN0 = 1) Note: The transition time is 1 ms or less unless otherwise stated Figure 9 Power-Down State Transition Time

MSM7583¡ Semiconductor APPLICATION CIRCUIT Figure 10 Example of Circuit Configuration 16 33 48NC IFCK MCK DGND IFIN2 DGND IFIN1 DGND V DD DOUT DIN EXCK DEN RESET PDN0 PDN1 AGND SG ENV V DD SLS11 SLS21 RXD1 RXC1 RXSC1 SLS12 SLS22 NC MSM7583GS-BK

19.2 MHz input

Receive symbol clock 2 output Receive channel select signal Receive data output Receive clock output Receive symbol clock output Demodulator 1 control signal Demodulator 2 control signal VDD C3 C2 C1 C1 = 10 mF C2 = C3 = 0.1 mF C4 = C5 = 1000 pF To orthogonal modulator NC RPR2 AFC2 RCW2 RPR1 AFC1 RCW1 RXSC0 RXC0 RXD0 RXSEL RXSC2 RXC2 RXD2 NC PDN2 BSTO TXW TXD TXCO TXCI NC NC NC NC NC NC NC NC NC

MSM7583¡ Semiconductor Demodulator Control Timing Diagram (Example) Demodulator unit Modulator input data PDN2 SLS2 240 bits 625 ms R1G Slot 1 R2G Slot 2 R3G Slot 3 R4G Slot 4 G SLS1 "0" "0" "0" "1" "1" "0" "1" "1" AFC /,/#01/#02 /,/#01/#02 R2RXD /,/#01/#02 /,/#01 /#02 RXC Timing for CS AFC RPR RCW 56 bits 64 bits 8 bits RPR RCW "0" Loss than 30 bits AFC G: Guard bit R: Ramp bit SS: Start symbol bit PR: Preamble bit UW: Unique word bit CR: CRC bit (1) Control channel/synchronous burst (SS + PR = 64 bits) (2) Communication channel (SS + PR = 8 bits) * AFC and RCW may be controlled at the same timing.

MSM7583¡ Semiconductor (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFP64-P-1414-0.80-BK Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Mirror finish