MSM7540 OKI | Alldatasheet

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MSM7540/7560¡ Semiconductor FEDL7540-03 ¡ Semiconductor MSM7540/7560 Single Rail ADPCM CODEC GENERAL DESCRIPTION The MSM7540/7560 are single channel ADPCM CODEC ICs which perform mutual transcoding between an analog voice band signal 300 to 3400 Hz and 32 kbps ADPCM serial data. Using advanced circuit technology, these devices operate using a single 5 V power supply and have low power consumption. The MSM7540/7560 are optimized for advanced digital cordless telephone system applications.

FEATURES

  • •••• Single 5 V Power Supply Operation
  • •••• ADPCM Algorithm : Complies completely with 1988's version ITU-T G.721 (32 kbps)
  • •••• Transmit/Receive Full-Duplex Operation
  • •••• Transmit/Receive Synchronous Mode Only
  • •••• Serial ADPCM Transmission Data Rate : 32 kbps to 2048 kbps
  • •••• Serial PCM Transmission Data Rate : 64 kbps to 2048 kbps
  • •••• PCM Interface Coding Format MSM7540 : A-law or Linear (14-bit, 2's compliment) Selectable MSM7560 : m-law or Linear (14-bit, 2's compliment) Selectable
  • •••• Low Power Consumption Operating Mode : 60 mW Typ. Power-Down Mode : 1.0 mW Typ.
  • •••• Two Analog Input Amplifier Stages : Externally Adjustable Gain
  • •••• Analog Output Stage : Push-pull Drive (direct drive of 350 W␣ + 120 nF)
  • •••• Built-in Crystal Oscillator (10.368 MHz)
  • •••• Built-in Reference Voltage Supply
  • •••• Option Reset Specified by ITU-T G. 721/ADPCM 28-pin plastic SOP (SOP28-P-430-1.27-K) (Product name: MSM7540GS-K) (Product name: MSM7560GS-K) FEDL7540-03 This version: Nov. 1999 Previous version: Aug. 1998

MSM7540/7560¡ Semiconductor FEDL7540-03 BLOCK DIAGRAM AIN2 GSX2 XSYNC IS AIN1 GSX1 AOUT– ADPCM CODER VDD BCLKA PCMSO PCMSI PCMRI PCMRO IR RSYNC ADPCM DECODER BCLKB AG DG X1 X2 PWI VREFSG CLOCK/ TIMINGMCK LPS RES PDN AOUT+ VFRO P S P S S P S P P S S P RC- LPF A/D Conv. BPF EX- PANDER RC- LPF D/A Conv. LPF COM- PANDER

MSM7540/7560¡ Semiconductor FEDL7540-03 PIN CONFIGURATION (TOP VIEW) 14 15 28RES PCMRI PCMRO IR IS PCMSI PCMSO LPS DG AG SG AIN1 GSX1 AIN2 GSX2 VFRO PWI AOUT– AOUT+ V DD PDN MCK RSYNC XSYNC BCLKA BCLKB 28-Pin Plastic SOP

MSM7540/7560¡ Semiconductor FEDL7540-03 Figure 1 Analog Input/Output Interface PIN AND FUNCTIONAL DESCRIPTIONS AIN1, AIN2, GSX1, GSX2 Transmit analog inputs and the output for transmit gain adjustment. AIN1 (AIN2) connects to the inverting input of the internal transmit amplifier. GSX1 (GSX2) connects to the internal transmit amplifier output. Refer to Fig. 1 for gain adjustment. VFRO, AOUT+, AOUT–, PWI Receive analog output and the output for receive gain adjustment. VFRO is the receive filter output. AOUT+ and AOUT– are differential analog signal outputs which can directly drive Z L = 350 W + 120 nF. Refer to Fig. 1 for gain adjustment. AIN1 GSX1 Analog Input to ENCODER from DECODER Analog OutputZL=120 nF + 350 W/CR * : Side Tone Pass (Gain = R6/RS ) AIN2 GSX2 C2 R3 AOUT– PWI RS* VFRO AOUT+ Transmit Gain: Receive Gain: = (R6/R5)

MSM7540/7560¡ Semiconductor FEDL7540-03 SG Analog signal ground voltage output. The output voltage of this pin is approximately 2.4 V. Put bypass capacitors between this pin and the AG pin. During power-down this output voltage is 0 V. The external SG voltage, if necessary, should be used via a buffer. AG Analog ground. DG Digital ground. This ground is separated internally from the analog signal ground pin (AG). The DG pin must be kept as close as possible to AG on the PCB. V DD +5 V power supply. LPS PCM coding law selection. MSM7540 only ; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the A-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value character signal (2's complement). MSM7560 only ; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the m-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value character signal (2's complement). PDN Power down control input. If this pin is "0", this device is in the power-down state. Normally, this pin is set to "1". RES Optional reset input specified by ITU-T Recommendation G. 721. If this pin is "0", the device is in the reset state. The reset width (during "L") should be 125ms or more. MCK Master clock input. The frequency must be 10.368 MHz. The master clock signal may be asynchronous to BCLKA, BCLKB, XSYNC, and RSYNC. PCMSO Transmit PCM data output. PCM is output from MSB in synchronization with the rising edge of BCLKB and XSYNC.

MSM7540/7560¡ Semiconductor FEDL7540-03 PCMSI Transmit PCM data input. This signal is converted to the transmit ADPCM data. PCM is shifted in synchronization with the falling edge of BCLKB. Normally, this pin is connected to PCMSO. PCMRO Receive PCM data output. PCM is the output signal after ADPCM decoder processing. This signal is output serially from MSB in synchronization with the rising edge of BCLKB and RSYNC. PCMRI Receive PCM data input. PCM is shifted on the falling edge of the BCLKB and input from MSB. Normally, this pin is connected to PCMRO. IS Transmit ADPCM signal output. After having encoded PCM with ADPCM, this signal is output from MSB in synchronization with the rising edge of BCLKA and XSYNC . This pin is an open drain output and remains in a high impedance state during power-down. IS requires a pull-up resistor. IR Receive ADPCM signal input. The ADPCM signal is shifted in series and synchronization with the falling edge of BCLKA and RSYNC, starting with MSB. BCLKB Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI). The frequency is set in the 64 kHz to 2048 kHz range. XSYNC 8 kHz synchronous signal input for transmit PCM and ADPCM data. Synchronize this signal with BCLKA and BCLKB signal. XSYNC is used to indicate the MSB of the serial PCM and ADPCM data stream. Be sure to input the XSYNC signal because it is also used as the input of the timing generator. RSYNC 8 kHz synchronous signal input for receive PCM and ADPCM data. Synchronize this signal with BCLKA and BCLKB signal. RSYNC is used to indicate the MSB of the serial PCM and ADPCM data stream. BCLKA Shift clock input for the ADPCM data (IS, IR). The frequency is set in the range of 32 kHz to 2048 kHz.

MSM7540/7560¡ Semiconductor FEDL7540-03 X1, X2 Crystal oscillator (10.368 MHz) connection. Connect X2, the clock output pin, directly to the MCK pin. When using a conventional external clock of 10.368 MHz, X1 should be connected to the ground, leave X2 open, and provide the external clock through the MCK pin. X1 MCK

10.368 MHz

<Using a self-oscilation circuit> MSM7540/60 X1 MCK <Using an external clock> MSM7540/60

MSM7540/7560¡ Semiconductor FEDL7540-03 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition Rating –0.3 to +7 –0.3 to V DD + 0.3 –0.3 to VDD + 0.3 –55 to +150 Unit V V V RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD Voltage must be fixed 4.5 — 5.5 V MCK, XSYNC, RSYNC, PCMRI, PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES Input High Voltage V IH 2.2 — V DD V MCK, XSYNC, RSYNC, PCMRI, PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES Input Low Voltage V IL 0 — 0.6 V Master Clock Frequency fMCK MCK – 0.01% 10.368 + 0.01% MHz Bit Clock Freqency fBCKA BCLKA 32 — 2048 kHz fBCKB BCLKB 64 — 2048 kHz Synchronous Signal Frequency fSYMC XSYNC, RSYNC — 8.0 — kHz Clock Duty Ratio DC MCK, BCLKA, BCLKB 30 50 70 % MCK, XSYNC, RSYNC, PCMRI, PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES Digital Input Rise Time t Ir ——5 0 n s MCK, XSYNC, RSYNC, PCMRI, PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES Digital Input Fall Time t If ——5 0 n s Transmit Sync Signal Setting Time tXS BCLKA, BCLKB to XSYNC 100 — — ns tXS XSYNC to BCLKA, BCLKB 100 — — ns Receive Sync Signal Setting Time tRS BCLKA, BCLKB to RSYNC 100 — — ns tSR RSYNC to BCLKA, BCLKB 100 — — ns Synchronous Signal Width tWS XSYNC, RSYNC 1 BCLK — 100 ms PCM, ADPCM Set-up Time tDS — 100 — — ns PCM, ADPCM Hold Time tDH — 100 — — ns Digital Output Load RDL IS (Pull-up Resistor) 500 — — W CDL — — 100 pFIS, PCMSO, PCMRO Operating Temperature Ta — –25 +25 +70 °C Bypass Capacitor for SG CSG — 10 + 0.1 — mFSG«GND

MSM7540/7560¡ Semiconductor FEDL7540-03

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics Parameter Power Supply Current Input High Voltage Input Low Voltage Output Low Voltage Output Leakage Current Input Capacitance Symbol IDD1 IDD2 VIH VIL VOL IO Condition Operating Mode, (When no signal, and VDD = 5.0 V) Power Down Mode (When VDD = 5.0 V)

1 LSTTL, Pull-up: 500 W

Min. 2.2 0.0 0.0 Typ. 0.2 0.2 Max. 0.5 VDD 0.6 0.4 Unit mA mA V V V mA CIN — —5— p F (VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) Input Leakage Current IIH IIL VI = VDD VI = 0 V 2.0 0.5 mA mA Transmit Analog Interface Characteristics Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Input Offset Voltage Symbol RINX RLGX CLGX VOGX VOFGX Condition AIN1, AIN2 Min. –20 Typ. Max. 100 *2.226 +20 Unit MW kW pF V PP mV GSX1, GSX2 GSX1, GSX2 GSX1, GSX2, R L = 50 kW Pre–OPAMPs SG Output Voltage SG Output Impedance V SG RSG 2.4 V kW SG Rise Time T SG — 700 — msSG«GND 10 mF + 0.1 mF (Rise time to 90% of max. level) * –3 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 2.226 VPP (MSM7540) –3 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 2.226 VPP (MSM7560)

MSM7540/7560¡ Semiconductor FEDL7540-03 Receive Analog Interface Characteristics * –3 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 2.226 VPP (MSM7540) –3 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 2.226 VPP (MSM7560) Parameter Input Resistance Output Load Resistance Output Capacitance Symbol RINPW RLVF RLAO CLVF CLAO Condition PWI Min. 1.2 Typ. Max. 100 100 Unit MW kW kW pF pF VFRO Output Voltage Level Offset Voltage VOVF VOAO VOFVF VOFAO –100 –20 *2.226 +100 +20 VPP VPP mV mV VFRO AOUT+, AOUT– VFRO AOUT+, AOUT– AOUT+, AOUT– VFRO AOUT+, AOUT– (GAIN = 0 dB), Power amp only GDB 4 0—— d BPower amp (0.3 to 3.4 kHz, ZL = 350 W + 120 nF)(See Fig.1) RL = 50 kW ZL = 350 W + 120 nF(See Fig.1) RL = 1.2 kW —— V PP *2.226 *2.226 Open Loop Gain

MSM7540/7560¡ Semiconductor FEDL7540-03 AC Chracteristics Parameter Transmit Frequency Response Symbol LOSS T1 Level 0 to 60 Min. Typ. Max. Unit dB Freq. Others LOSS T2 300 to 3000 –0.15 — +0.20 dB LOSS T3 1020 Reference dB0LOSS T4 3300 –0.15 — +0.80 dB LOSS T5 3400 0 — 0.80 dB LOSS T6 3968.75 14 — — dB Receive Frequency Response 0 to 3000 –0.15 — +0.20 dB

1020 Reference dB

3300 –0.15 — +0.80 dB0 3400 0 — 0.80 dB 3968.75 14 — — dB Transmit Signal to Distortion Ratio SD T1 35 — 3 SD T2 35 — 0 SD T3 35 — –30 SD T4 1020 28 —–40 SD T5 23 — –45 Receive Signal to Distortion Ratio SD R1 — 3 SD R2 — 0 SD R3 — –30 SD R4 1020 —–40 SD R5 — –45 Transmit Gain Tracking GT T1 –0.2 +0.2 GT T2 Reference GT T3 1020 –0.2 +0.2 –40 GT T4 –0.5 +0.5 GT T5 –1.2 +1.2 –10 –50 –55 Receive Gain Tracking GT R1 –0.2 +0.2 GT R2 Reference GT R3 1020 –0.2 +0.2 GT R4 –0.5 +0.5 GT R5 –1.2 +1.2 –40 –10 –50 –55 Condition LOSS R1 LOSS R2 LOSS R3 LOSS R4 LOSS R5 (*1) (*1) dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB DD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) (dBm0)(Hz) *1 Use the P-message weighted filter

MSM7540/7560¡ Semiconductor FEDL7540-03 Digital Output Delay Time tSDX 50 — 200 tSDR 50 — 200 tXD1, tRD1 50 — 200 tXD2, tRD2 50 — 200 ns

1 LSTTL + 100 pF,

Pull-up: 500 W PSRRT Noise Freq. : 0 to 50 kHz 3 0—— d BPower Supply Noise Rejection Ratio Noise Level : 50 mVPP —PSRRR tXD3, tRD3 50 — 200 Parameter Symbol Level Min. Typ. Max. Unit (VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C) Freq. Others Condition 3 0—— d B ns ns ns ns (dBm0)(Hz) NIDLT —— — –69 (–72) dBm0p (dBmp)NIDLR —— 1020 AVT 0.488 0.548 (*3) 0.615 AVR 0.488 0.548 (*3) 0.615 — –72 (–75) Idle Channel Noise AIN = SG (*1) (*2) Vrms Vrms GSX2Absolute Signal Amplitude VFRO (*1) AC Characteristics (Continued) *1 Use the P-message weighted filter *2 PCMRI input code "11010101"(MSM7540) "11111111"(MSM7560) *3 0.548 Vrms = 0 dBm0= –3 dBm Note: All ADPCM coder and decoder characteristics comply with ITU-T Recommendation G.721.

MSM7540/7560¡ Semiconductor FEDL7540-03 TIMING DIAGRAM Transmit Side PCM/ADPCM Data Interface Receive Side PCM/ADPCM Data Interface MSB MSB LSB LSB 0123456789 1 0 0123456789 1 0 11 12 13 txs tsx txd1 txd2 tsdx txs tsx txd1 txd2 tsdx txd3 MSB LSB txd3 txd3 BCLKB XSYNC PCMSO PCMSO (during linear) BCLKA XSYNC IS tws MSB MSB LSB LSB 0123456789 1 0 0123456789 1 0 1 1 1 2 1 3 tsr tds tdh txd3 txd3 trd3 trs tsr trd1 trd2 BCLKA RSYNC IR BCLKB RSYNC PCMRO PCMRO (during linear) tsdx trs MSB LSB tws Note: Linear format A code of an input/output level is determined by the 14-bit 2'compliment. Refer to the table below for code format. Input/Output level +Full-scall –Full-scall MSB to LSB 01111111111111 00000000000000 10000000000000

MSM7540/7560¡ Semiconductor FEDL7540-03 APPLICATION CIRCUIT MSM7540/7560GS 8 kHz Sync Signal Input Power Down Input Receive ADPCM Input Transmit ADPCM Output Transmit Analog Input Receive Analog Output (Push-Pull) VDD VDD ADPCM Algorithm Reset Input Shift Clock Input for PCM, ADPCM Data (64 kHz to 2048 kHz) SG AOUT– RES PCMRI PCMRO IR IS PCMSI PCMSO LPS DG BCLKB BCLKA XSYNC RSYNC MCK PDN V DD AG AOUT+

MSM7540/7560¡ Semiconductor FEDL7540-03 (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). SOP28-P-430-1.27-K Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.75 TYP. Mirror finish

MSM7540/7560¡ Semiconductor FEDL7540-03 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan