MSM65512A OKI | Alldatasheet

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¡ Semiconductor MSM65512A/65P512A GENERAL DESCRIPTION The MSM65512A is a high-performance 8-bit microcontroller that employs OKI original nX-8/ 50 CPU core. With a minimum instruction execution time of 400 ns (10MHz clock), the MSM65512A is capable of high-speed processing, and includes 8K bytes of program memory, 256 bytes of data memory, timers and serial ports. Also available are the MSM65P512A, which replaces the MSM65512's built-in program memory with one-time PROM, and the MSM65X512A, which uses external program memory.

FEATURES

  • Operating range Operating frequency 0 to 10 MHz (VDD=4.5 to 5.5 V) 0 to 5 MHz (VDD=2.7 to 5.5 V) Operating voltage 2.7 to 5.5 V Operating temperature –40 to +85°C (Operation at +125°C is assured by the other specification.)
  • Memory space 64K bytes Internal program memory 8K bytes Internal data memory 256 bytes
  • Minimum instruction execution time 400 ns @ 10 MHz
  • Powerful instruction set 83 basic instructions 8/16-bit operation instructions Bit manipulation instructions Compound function instructions
  • Abundant addressing modes
  • Multiplication/division operation functions 8 ¥ 8 Æ 16 16/8 Æ 16 ... 8
  • I/O ports Input-output port 4 ports ¥ 8 bits
  • Timers 8-bit auto-reload timer ¥ 2 16-bit auto-reload timer ¥ 1 Watchdog timer ¥ 1
  • Counters Time base counter ¥ 1 16-bit free-running counter ¥ 1
  • Capture input 1 channel
  • Compare output 2 channels
  • Serial ports Shift register ¥ 1 Serial port with baud rate generator (UART/synchronous) ¥ 1
  • External interrupts
  • Interrupt sources
  • Package 40-pin plastic DIP (DIP40-P-600-2.54) (MSM65512A-¥¥¥RS, MSM65P512A-¥¥¥RS) 44-pin plastic QFP (QFP44-P-910-0.80-2K) (MSM65512A-¥¥¥GS-2K, MSM65P512A-xxxGS-2K) 44-pin plastic QFJ (PLCC) (QFJ44-P-S650-1.27): (MSM65512A-¥¥¥JS, MSM65P512A-¥¥¥JS) ¥¥¥ indicates the code number. ¡ Semiconductor MSM65512A/65P512A High Performance 8-Bit Microcontroller E2E1011-27-Y4 This version: Jan. 1998 Previous version: Nov. 1996

¡ Semiconductor MSM65512A/65P512A BLOCK DIAGRAM OSC 0 OSC 1 RESET HSTOP* VDD GND OSC CONT. ROM (8K bytes) EXT.MEM. CONT. CPU CORE INST. DEC. T/C IR ALU GMAR PC AR BR PSW SP LMAR BUS CONT. I/O PORT RAM (256 bytes) TBC WDT 16-bit TIMER 16-bit FRC CAP¥1, CMP¥2 SIO AD0-7* A8-15* RD WR* ALE EA T2CK* GATE* CAP* CMP0* CMP1* TXD* RXD* P0 P1 P2 P3 * Secondary functions of ports. One timer is used for the SIO baud rate generator 8-bit TIMER¥3 T1OUT* T0CK* 8-bit SHIFT-REG. INTERRUPT CONT. SFTO* SFTI* SFTCK* INT0* INT1* INT2* MUL/DIV

¡ Semiconductor MSM65512A/65P512A PIN CONFIGURATION (TOP VIEW) 40-Pin Plastic DIP GND P3.0/T2CK P3.1/CAP P3.2/CMP0 P3.3/CMP1 P3.4/INT2 P3.5/SFTO P3.6/SFTI P3.7/SFTCK RESET P2.0/RXD P2.1/TXD P2.2/INT0 P2.3/INT1/GATE P2.4/T0CK P2.5/HSTOP P2.6/WR P2.7/T1OUT OSC1 OSC0 P1.0/A8 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE RD P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12 P1.3/A11 P1.2/A10 P1.1/A9

¡ Semiconductor MSM65512A/65P512A PIN CONFIGURATION (TOP VIEW) (Continued) NC P3.5/SFTO P3.6/SFTI P3.7/SFTCK RESET P2.0/RXD P2.1/TXD P2.2/INT0 P2.3/INT1/GATE P2.4/T0CK P2.5/HSTOP P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE RD P1.7/A15 P1.6/A14 P1.5/A13 NC P3.4/INT2 P3.3/CMP1 P3.2/CMP0 P3.1/CAP P3.0/T2CK VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 NC P2.6/WR P2.7/T1OUT OSC1 OSC0 GND *VDD P1.0/A8 P1.1/A9 P1.2/A10 P1.3/A11 P1.4/A12 * No-connection pin for MSM65P512A NC: No-connection pin 44-Pin Plastic QFP

¡ Semiconductor MSM65512A/65P512A PIN CONFIGURATION (TOP VIEW) (Continued) P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD P3.0/T2CK P3.1/CAP P3.2/CMP0 P3.3/CMP1 P3.4/INT2 NC P1.4/A12 P1.3/A11 P1.2/A10 P1.1/A9 P1.0/A8 GND OSC0 OSC1 P2.7/T1OUT P2.6/WR P3.5/SFTO P3.6/SFTI P3.7/SFTCK RESET P2.0/RXD P2.1/TXD P2.2/INT0 P2.3/INT1/GATE P2.4/T0CK P2.5/HSTOP P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE RD P1.7/A15 P1.6/A14 P1.5/A13 NC NC NC NC: No-connection pin 44-Pin Plastic QFJ (PLCC)

¡ Semiconductor MSM65512A/65P512A PIN DESCRIPTIONS Basic Functions Function Symbol Type

Description

+5V power supply GND 0V digital ground OSC0 Crystal oscillation input/external clock input OSC1 Crystal oscillation output I O RESET System reset input (program starts from address 0040H); internal pull-up resistor I EA Program memory select input pin. "L" level input for external program memory; "H" level input for internal program memory. I RD Read strobe signal during external memory access O ALE Address latch signal during external memory access O PORT 0 8-bit Input-output port During external memory access, becomes address/data bus for address output, instruction fetch or data read/write along with ALE, RD and WR pins I/O PORT 1 8-bit Input/output port Address bus during external memory access I/O PORT 2 PORT 3 8-bit Input/output port ¥ 2. Secondary functions shown in following table are added for ports 2 and 3. I/O Oscillation Control Port

¡ Semiconductor MSM65512A/65P512A Secondary Functions Symbol Type P2.2 secondary function External interrupt 0 input pin. I INT1/GATE P2.3 secondary functions External interrupt 1 input pin. Also used as input pin for gate signal for timer 0 count enable/disable. I T0CK P2.4 secondary function Timer 0 external clock input pin. I HSTOP P2.5 secondary function Hard stop mode input pin; stops system clock oscillation with "L" level input. I WR P2.6 secondary function Write strobe signal output pin during external data memory access. O T1OUT P2.7 secondary function Output pin for signal obtained by dividing timer overflow by 2. O SFTO P3.5 secondary function Shift register data output pin. O SFTI P3.6 secondary function Shift register data input pin. I SFTCK P3.7 secondary function Shift register synchronizing clock input/output pin. I/O RXD P2.0 secondary functions UART: Input pin for serial port receive data. Synchronous: Input/output pin for serial port transmit/receive data. I/O TXD O T2CK P3.0 secondary function Timer 2 external clock input pin. I CAP P3.1 secondary function Capture trigger input pin. I CMP0 P3.2 secondary function Compare output channel 0 output pin. O CMP1 P3.3 secondary function Compare output channel 1 output pin. O INT2 P3.4 secondary function External interrupt 2 input pin I P2.1 secondary functions UART: Output pin for serial port transmit data. Synchronous: Output pin for serial port synchronizing clock.

¡ Semiconductor MSM65512A/65P512A Port Circuit Configuration Type Port

Electrical Characteristics

(VDD=5V) P0.0/AD0- P0.7/AD7 "H" Input Voltage:

  • VIH=2.4V "L" Input Voltage:
  • VIL=0.8V "H" Output Voltage:
  • VOH=3.75V
  • IOH=–400mA "L" Output Voltage:
  • VOL=0.4V
  • IOL=3.2mA Circuit Configuration P1.0/A8- P1.7/A15 "H" Input Voltage:
  • VIH=2.4V "L" Input Voltage:
  • VIL=0.8V "H" Output Voltage:
  • VOH=3.75V
  • IOH=–200mA "L" Output Voltage:
  • VOL=0.4V
  • IOL=1.6mA P0D DIR Data Bus External Memory Control PORT0 P1D DIR Data Bus External Memory Control PORT1 Data Bus PxD Px DIR Secondary Output Function (x=2 to 5) Px MOD PORTx Secondary Input Function "H" Input Voltage:
  • VIH=2.4V "L" Input Voltage:
  • VIL=0.8V P2.6/WR "H" Output Voltage:
  • VOH=3.75V
  • IOH=–400mA "L" Output Voltage:
  • VOL=0.4V
  • IOL=3.2mA Excluding P2.6/WR "H" Output Voltage:
  • VOH=3.75V
  • IOH=–200mA "L" Output Voltage:
  • VOL=0.4V
  • IOL=1.6mA P2.0/RXD, P2.1/TXD, P2.6/WR, P2.7/T1OUT, P3.2/CMP0, P3.3/CMP1, P3.5/SFT0, P3.7/SFTCK

¡ Semiconductor MSM65512A/65P512A PxD Px DIR Data Bus (x=2 to 5) PORTx Secondary Input Function Type Port (VDD=5V) "H" Input Voltage:

  • VIH=2.4V "L" Input Voltage:
  • VIL=0.8V "H" Output Voltage:
  • VOH=3.75V
  • IOH=–200mA "L" Output Voltage:
  • VOL=0.4V
  • IOL=1.6mA Circuit Configuration P2.2/INT0, P2.3/INT1/GATE, P2.4/T0CK, P2.5/HSTOP, P3.0/T2CK, P3.1/CAP, P3.4/INT2, P3.6/SFTI Port Circuit Configuration (Continued)

¡ Semiconductor MSM65512A/65P512A ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Parameter Unit Supply Voltage VDD –0.3 to 7.0 Symbol Condition Rating Ta=25°C Input Voltage VI –0.3 to VDD+0.3 Output Voltage VO –0.3 to VDD+0.3 Power Dissipation PD 400 Ta=25°C per package Ta=25°C per output Storage Temperature TSTG –55 to +150 V mW *1 This is due to the standard of a crystal oscillator or ceramic resonator. MEMORY MAPS 100H 80H 40H 30H 20H 10H 0FFFFH 2000H 100H 80H 40H 20H Internal Memory Local Memory Space SFR Data Memory Local Register Set 3 Local Register Set 2 Local Register Set 1 Local Register Set 0 General Memory Space External Memory Program Memory Vector Call Table Area Program Memory Interrupt Vector Table Area Vector Call Table Area 17FH Data Memory Page 1 Page 0 Parameter Unit Supply Voltage VDD 2.7 to 5.5 Symbol Condition Range Refer to Figure 1. Memory Hold Voltage VDDMH 2.0 to 5.5 fOSC=0 Hz Oscillation Operating Frequency *1 fOSC 1 to 10 Refer to Figure 1. External Clock Operating Frequency fEXTCLK 0 to 10 Refer to Figure 1. Operating Temperature Top –40 to +85 V MHz MHz

Figure 1. Operating Frequency vs. Power Supply Voltage

  • Oscillates at 1MHz or more.

¡ Semiconductor MSM65512A/65P512A DC Characteristics 1 (VDD=4.5 to 5.5V) (GND=0V, Ta=–40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit "H" Input Voltage 1 *1 VIH1 2.4 VDD+0.3 "H" Input Voltage 2 *2 VIH2 0.7VDD VDD+0.3 "L" Input Voltage VIL –0.3 0.8 "H" Output Voltage 1 *3 VOH1 IOH=–200mA 0.75VDD "H" Output Voltage 2 *4 VOH2 IOH=–400mA 0.75VDD "L" Output Voltage 1 *3 VOL1 IOL=1.6mA 0.4 "L" Output Voltage 2 *4 VOL2 IOL=3.2mA 0.4 Input Leakage Current 1 *5 ILI1 VI=VDD/0V Input Leakage Current 2 *6 ILI2 VI=VDD/0V ±10 "L" Input Current *7 IIL VI=0V –40 –200 –400 Input Capacitance CI f=1MHz, Ta=25°C Current Consumption IDDS 5V, Stop mode *8 10MHz, 5V, no load *9 V mA pF mA IDDS mA *1 Excluding OSC0 and RESET *2 OSC0 and RESET *3 Excluding P0, ALE, RD, P2.6/WR *4 P0, ALE, RD, P2.6/WR *5 EA *6 Excluding RESET, EA *7 RESET The ports configured as inputs should be coupled to VDD or 0V. Other ports should not be loaded. Refer to Figure 2.

¡ Semiconductor MSM65512A/65P512A DC Characteristics 2 (2.7£ VDD<4.5V) *1 Excluding OSC0 and RESET *2 OSC0 and RESET *3 Excluding P0, ALE, RD, P2.6/WR *4 P0, ALE, RD, P2.6/WR *5 EA *6 Excluding RESET, EA *7 RESET *8 The ports configured as inputs should be coupled to VDD or 0V. Other ports should not be loaded. *9 Refer to Figure 2. (GND=0V, Ta=–40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit "H" Input Voltage 1 *1 VIH1 0.5VDD+0.2 VDD+0.3 "H" Input Voltage 2 *2 VIH2 0.6VDD+0.4 VDD+0.3 "L" Input Voltage VIL –0.3 0.15VDD+0.1 "H" Output Voltage 1 *3 VOH1 IOH=–10mA 0.75VDD "H" Output Voltage 2 *4 VOH2 IOH=–20mA 0.75VDD "L" Output Voltage 1 *3 VOL1 IOL=10mA 0.1 "L" Output Voltage 2 *4 VOL2 IOL=20mA 0.1 Input Leakage Current 1 *5 ILI1 VI=VDD/0V Input Leakage Current 2 *6 ILI2 VI=VDD/0V ±10 "L" Input Current *7 IIL VDD=2.7 to 3.3V, VI=0V –40 –120 –240 Input Capacitance CI f=1MHz, Ta=25°C Current Consumption IDDS 3V, Stop mode *8 IDD 5MHz, 3V, no load *9 V mA pF mA mA

Figure 2. Operating Current Consumption vs. Power Supply Voltage

¡ Semiconductor MSM65512A/65P512A AC Characteristics

  • External memory control (VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C) Parameter Symbol Condition Min. Max. Unit Clock Cycle tC VDD=4.5 to 5.5V 100 "L" Clock Pulse Width tCLW VDD=2.7 to 5.5V "H" Clock Pulse Width tCHW CL=100pF Clock Cycle tC 200 "L" Clock Pulse Width tCLW "H" Clock Pulse Width tCHW ALE Pulse Width tAW tC+tCHW–20 ALE Pulse Delay Time 1 tALD1 tCLW–20 ALE Pulse Delay Time 2 tALD2 tCLW–20 RD Pulse Width tRW tC+tCHW–40 RD Pulse Delay Time tRD tCLW–40 tCLW+20 WR Pulse Width tWW tC+tCHW–40 WR Pulse Delay Time tWD tCLW–20 tCLW+40 "L" Address Setup Time tLAS tC–40 "H" Address Setup Time tHAS tC–40 "L" Address Hold Time tLAH tCLW–20 Bus Float Time tLAZ "H" Address Hold Time tHAHR tC–20 "H" Address Hold Time tHAHW tC–20 Read Data Access Time tRDAA tC+tCLW–15 Read Data Access Time tRDAR tCHW+10 Read Data Hold Time tRDH Write Data Setup Time tWDS tC+tCLH–40 Write Data Hold Time tWDH tCLW–20 ns

¡ Semiconductor MSM65512A/65P512A OSC0 tCHW tC tAW tCLW tRD tRDAR tLAS tLAZ tRDAA tHAS tWD tWDS tHAHW tRW tALD1 tLAH tRDH tHAHR tWW tALD2 tWDH ADDRESS L INST or DATA IN ADDRESS H ADDRESS L DATA OUT ADDRESS H ALE RD WR

¡ Semiconductor MSM65512A/65P512A

  • CPU control *1 Excluding power ON, stop mode and hard stop mode. *2 During power ON, in stop mode and hard stop mode. *3 Oscillation stabilization time depends on resonator. (VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C) Parameter Symbol Condition Min. Max. Unit RESET Pulse Width *1 tRESW1 ns RESET Pulse Width *2 tRESW2 RESET pulse width tRESW1, 2 RESET
  • Peripheral control 1 * tT0CLK : Timer 0 count clock cycle selected by T0CON. (VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C) Parameter Symbol Condition Min. Max. Unit Clock Cycle tC 100 ns External Interrupt Pulse Width tEXIW 4 tC External Clock Pulse Width tT0CW 4 tC GATE Pulse Width tT0GW 1 tTOCLK * OSC EXI External Clock Pulse Width tT2CW 4 tC CAP Pulse Width tCAPW 12 tC CAP VDD=4.5 to 5.5V 200 VDD=2.7 to 5.5V

¡ Semiconductor MSM65512A/65P512A 1) EXI pulse width 2) T0 3) T2 4) CAP OSC0 tC tCLW T0CK tT0CW GATE tT0GW T2CK tT2CW CAP tCAPW INT0-2 tEXIW

¡ Semiconductor MSM65512A/65P512A

  • Peripheral control 2 (VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C) Parameter Symbol Condition Min. Max. Unit Clock Cycle tC 100 ns SFTCK Cycle tSFC 8 tC SFTCK "L" Pulse Width tSFCLW 4 tC–20 SFTCK "H" Pulse Width tSFCHW 4 tC–20 OSC SFT SFTCK Setup Time tSFOS tSFCLW–100 SFTO Hold Time tSFOH tSFCHW–100 SFTI Setup Time tSFIS 100 SFTI Hold Time tSFIH 100 CL=100pF Synchronous Clock Cycle tSIC 8 tC Synchronous Clock "L" Pulse Width tSICLW 4 tC–20 Synchronous Clock "H" Pulse Width tSICHW 4 tC–20 Output Data Setup Time tSIOS 6 tC–100 Output Data Hold Time tSIOH 2 tC–100 Input Data Setup Time tSIIS tC+tCLW+100 Input Data Hold Time tSIIH SIO (Clock Syn- chro- nous) VDD=4.5 to 5.5V 200 VDD=2.7 to 5.5V

¡ Semiconductor MSM65512A/65P512A 1) SFT 2) SIO (Clock synchronous mode) tSFCLW tSFCHW tSFC tSFOS tSFOH tSFIS tSFIH SFTCK SFTO SFTI tSICLW tSICHW tSIC tSIOS tSIOH tSIIS tSIIH TXD RXD (transmission) RXD (reception)

¡ Semiconductor MSM65512A/65P512A (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.

¡ Semiconductor MSM65512A/65P512A (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. QFP44-P-910-0.80-2K Mirror finish

¡ Semiconductor MSM65512A/65P512A (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFJ44-P-S650-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Mirror finish