MSM65354 OKI | Alldatasheet

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¡ Semiconductor MSM65354/65353A ¡ Semiconductor MSM65354/65353A 8-Bit Microcontroller with A/D Converter (with LCD Driver) GENERAL DESCRIPTION The MSM65354/MSM65353A is a high performance 8-bit microcontroller that employs OKI original CPU core nX-8/50. The MSM65354 contains 24K-byte program memory, 640- byte data memory, LCD driver, A/D converter and shift register. The MSM65353A contains 16K-byte program memory, 384-byte data memory, LCD driver, A/D converter and shift register. Also available is the MSM65P354, which replace the on-chip program memory with one-time PROM.

FEATURES

  • Operating range Operating voltage : 2.7V to 5.5V Operating temperature : –20 °C to +70°C Operating frequency (dual clock) High speed side : 0 to 10MHz (@V DD=5V±10%) 0 to 5MHz (@VDD=2.7V to 5.5V) Low speed side : 32.768kHz (@V DD=2.7V to 5.5V) Current consumption (Typ.) High speed side : 5mA (@5MHz, V DD=3V) 20mA (@10MHz, VDD=5V) 1.5mA (@5MHz, VDD=3V, Halt mode) 4mA (VDD=3V), Stop mode) Low speed side : 45 mA (@32.768kHz, VDD=3V)
  • Minimum instruction execution time : 400ns (@10MHz), 800ns (@5MHz)
  • CPU core : 8-bit CPU core nX-8/50
  • General memory space : 24K-byte program memory + 256-byte data memory (MSM65354) 16K-byte program memory (MSM65353A)
  • Local memory space : 384-byte data memory + SFR
  • LCD driver : 32 · 4 (selectable duty cycle from 1/4, 1/3 or 1/2 with software)
  • I/O port Input-output port : 5 ports · 8 bits Input port : 1 port · 1 bit, 1 port · 8 bits Output port : 1 port · 1 bit
  • Timer : 8-bit auto-reload timer · 3 (one of them can be used for the shift clock of shift register) : Watch timer counter · 1
  • Counter : Time base counter · 1 (14 bits)
  • Buzzer output circuit : 1 line, selectable from 1000Hz to 16000Hz (@10MHz)
  • Shift register : 2ch, with 16-byte automatic transfer function · 1, clock sync mode · 1
  • A/D converter : 8ch, 8 bits (4ch of them can start the CPU according to level detection interrupt) E2E1020-27-Y3 This version: Jan. 1998 Previous version: Nov. 1996

¡ Semiconductor MSM65354/65353A

  • External interrupt : Three lines, selectable from rising edge/ falling edge/both edges
  • Remote control circuit : Receives signal in 32.768kHz/5MHz/ 10MHz operations
  • Interrupt source : 13
  • Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (Product name:MSM65354- ··· GS-BK4, MSM65353A-··· GS-BK4)
  • ·· indicates the code number.
  • Others : CPU clock can be an OSC, half-OSC, XT or 4 times XT clock : Time base counter clock can be selected with 1/4n of a CPU clock (n=1 to 8) : Stop status can be set at each port (high impedance or prior status is retained) : Pull-up or open can be set for each input- output port

¡ Semiconductor MSM65354/65353A BLOCK DIAGRAM VDD GND RAM (384 bytes) TBC WDT BUZZER OUTPUT 8-bit TIMER · 3 8-bit SHIFT REG. (16-BYTE AUTOMATIC TRANSFER FUNCTION) BZ* T1OUT* T0CK* GATE* SFTO0* SFTI0* SFTCK0* 8-bit SHIFT REG. SFTO1* SFTI1* SFTCK1* INTERRUPT CONT. INT0* INT1* INT2* INT3* REMOTE CONT. RMCIN* BUS CONT. RAM (256 bytes) ROM (24K bytes) LCD DRIVER VDD3 VDD2 VDD1 VDDL COM1 COM4 SEG0 SEG31 I/O PORT8-bit A/D C

  • 8ch AVDD VRH AGND AI0-7* GMAR PC LMARSPPSWBRAR ALU IR T/C INST. DEC. OSC. CONT. XT XT OCS0 OSC1 RESET CLKOUT* XSTOP* *secondary function of each port **The MSM65353A contains 16K byte ROM only CPU CORE WATCH TIMER

¡ Semiconductor MSM65354/65353A PIN CONFIGURATION (TOP VIEW) OSC0 P6.0 (IN) P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P1.7/SFTO1 P1.6/SFTI1 P1.5/SFTCK1 P1.4/RMCIN P1.3 P1.2 P1.1 P1.0 V DD P0.7/BZ P0.6 P0.5/CLKOUT P0.4/INT1/GATE P0.3/T1OUT P0.2/T1OUT P0.1/HSTOP P0.0/INT0 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM4 COM3 COM2 COM1 P5.5 P5.6 P5.7 AVDD VRH P3.7/AI7 P3.6/AI6 P3.5/AI5 P3.4/AI4 P3.3/AI3/INT3 P3.2/AI2/INT3 P3.1/AI1/INT3 P3.0/AI0/INT3 AGND SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 100 OSC1 GND XT XT P2.7 P2.6 P2.5 P2.4 P2.3/INT2 P2.2/SFTO0 P2.1/SFTI0 P2.0/SFTCK0 RESET P6.1 (OUT) V DDL VDD1 VDD2 VDD3 /,/#02 /#06/#08 100-Pin Plastic QFP

¡ Semiconductor MSM65354/65353A PIN DESCRIPTIONS Basic Function Function Pin Type Description 72 — Digital supply voltage (5V) 83 — Digital ground 47 — Analog supply voltage (5V) 37 — Analog ground 98 — Bias supply pin for LCD driver 99 — Bias supply pin for LCD driver 100 — Bias supply pin for LCD driver 97 — Bias control pin for LCD driver Power Supply 82 I Oscillation input pin on the OSC side: Connect to a quartz oscillator (ceramic resonator), or input external clock. 81 O Oscillation output pin on the OSC side: Connect to a quartz oscillator (ceramic resonator). When external clock is input to the OSC0 pin, the OSC1 pin should be open.

84 I Oscillation input pin on the XT side:

Connect to a quartz oscillator of 32.768kHz.

85 O Oscillation output pin on the XT side:

Connect to a quartz oscillator of 32.768kHz. Oscillation Symbol VDD GND AVDD AGND VDD1 VDD2 VDD3 VDDL OSC0 OSC1 XT XT

¡ Semiconductor MSM65354/65353A Function Pin Type Description System reset input: When this pin is set to the "L" level, the internal status is initialized to start execution of instructions from address 0040H. The input is pulled up to V DD with an internal pull-up resistor. 8-bit input-output port (port 0): Each of bits 0 to 7 is configured to be input or output by use of the direction register of port 0 (P0DIR). In addition to the basic function as the input-output port, a secondary function is allocated to each of P0.0 through P0.7. See Secondary function. Control I/O Ports I to 8-bit input-output port (port 1): Each of bits 0 to 7 is configured to be input or output by use of the direction register of port 1 (P1DIR). In addition to the basic function as the input-output port, a secondary function is allocated to each of P1.0 through P1.7. See Secondary function. I/O to 8-bit input-output port (port 2): Each of bits 0 to 7 is configured to be input or output by use of the direction register of port 2 (P2DIR). In addition to the basic function as the input-output port, a secondary function is allocated to each of P2.0 through P2.3. See Secondary function. I/O to Symbol RESET P0.7 P0.0 to P1.7 P1.0 to P2.7 P2.0 to Basic Function (Continued)

¡ Semiconductor MSM65354/65353A Function Pin Type Description 8-bit input port (port 3): Each of P3.0 to P3.7 funcitons as analog input channel of A/D converter. Ports LCD Driver I 1-bit output port (port 6.1): Pulled high at the time of reset. If this pin is set to the "0" level during reset, this IC goes into a test mode, disabling execution of the user program. O to 8-bit input-output port (port 4): 8-bit input-output port.I/O to 8-bit input-output port (port 5): Each of bits 0 to 7 is configured to be input or output by the direction register of port 5 (P5DIR). I/O to 1-bit input port (port 6.0): 1-bit input port.I95 LCD common signal output pins.O to LCD segment signal output pins.O to Symbol P3.7 P3.0 to P4.7 P4.0 to P5.7 P5.0 to P6.0 (IN) P6.1 (OUT) COM4 COM1 to SEG31 SEG0 to Basic Function (Continued)

¡ Semiconductor MSM65354/65353A Secondary Function Function Pin Type Description Secondary function of P0.0: Input pin for external interrupt 0. This pin can receive input at the rising edge, falling edge, or both the rising/falling edges. External Interrupt Control I80 to Secondary function of P0.4: Input pin for external interrupt 1. This pin can receive input at the rising edge, falling edge, or both the rising/falling edges. Also used as a gate signal input pin to enable or disable the count of timer 0. I76 Secondary function of P2.3: Input pin for external interrupt 2. This pin can receive input at the rising edge, falling edge, or the both rising/falling edges. I90 Secondary function of P3.0 to 3.3: Input pin for external interrupt 3. This pin can receive input at the rising edge, falling edge, or both the rising/falling edges. I Secondary function of P0.1: Hardware stop mode input pin. When this pin is set to the "L" level while the HSTP bit in SBYCON is set to "1", the hardware stop mode is entered. In the hardware stop mode, oscillation on the OSC side is stopped for low power consumption. I79 Secondary function of P0.3: External clock input pin for timer 0.ITimer 0 Secondary function of P0.2: Output pin that provides waveform with a cycle twice the overflow of timer 1. OTimer 1 Secondary function of P3.0 to 3.7: These are used for analog input channels in A/D conversion. IA/D Converter to Symbol INT0 INT1 INT2 INT3 HSTOP T0CK T1OUT AI7 AI0 to

¡ Semiconductor MSM65354/65353A Secondary Function (Continued) Function Pin Type Description Secondary function of P0.5: Output pin for OSCCLK divided by 2 or 4 or for XTCLK divided by 2 or 4. Clock Output O75 Secondary function of P0.7: Output pin for buzzer.O73Buzzer Output Secondary function of P1.4: Input pin for remote control.I67Remote Control Input Shift Register Secondary function of P2.2: Data output pin for shift register 0.O91 Secondary function of P2.1: Data Input pin for shift register 0.I92 Secondary function of P2.2: Sync. clock input-output pin for shift register 0. This provides a clock output when used as the master, or it functions as clock input when used as a slave. I/O93 Secondary function of P1.7: Data output pin for shift register 1.O64 Secondary function of P1.6: Data Input pin for shift register 1.I65 Secondary function of P1.5: Sync. clock input-output pin for shift register 1. This provides a clock output when used as the master, or it functions as clock input when used as a slave. I/O66 Symbol CLKOUT BZ RMCIN SFTO0 SFTI0 SFTCK0 SFTO1 SFTI1 SFTCK1

¡ Semiconductor MSM65354/65353A MEMORY MAPS Local Register Set 3 Local Register Set 2 Local Register Set 1 Local Register Set 0 R Data Memory SFR Data Memory 1FFH 100H 80H 40H 30H 20H 10H Page 1 Page 0 Program Memory Interrupt Vector Table Vector Call Table Vector Call Table Data Memory 0FFFFH 6000H* 100H 80H 40H 20H Internal Memory Program Memory 0FF00H Local Memory Space General Memory Space Unused space * 4000H, in the case of MSM65353A

¡ Semiconductor MSM65354/65353A ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Supply Voltage VDD –0.3 to 7.0 Input Voltage VI –0.3 to VDD+0.3 Output Voltage VO –0.3 to VDD+0.3 Maximum Allowable Dissipation PD 400 Ta = 25°C Ta = 25°C, per package 50Ta = 25°C, per output Storage Temperature T STG — –55 to +150 V mW RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit Supply Voltage VDD 2.7 to 5.5 Memory Hold Voltage VDDMH 2.0 to 5.5 fOSC 1 to 10 Oscillation Frequency*1 fXT 32.768/75 fOSC = 0Hz VDD = 2.7 to 5.5 1 to 10— Operating Temperature Top — –20 to +70 V MHz fEXTCLK External Clock Operating Frequency*2 kHz MHz *1 Determined by the crystal oscillator or ceramic resonator to be used. *2 External clock cannot be used in the XT pin.

¡ Semiconductor MSM65354/65353A

ELECTRICAL CHARACTERISTICS

DC Characteristics 1 (VDD=4.5 to 5.5V) Parameter Symbol Condition Typ. Unit "H" Input Voltage 1 VIH1 — "H" Input Voltage 2 VIH2 — VIL —"L" Input Voltage VOH1 — CPUCLK=1MHz IOH = –200mA —IOH = –400mA "L" Output Voltage 1 VOL1 IOL = 1.6mA — CPUCLK=1MHz CPUCLK=1MHz VOH2"H" Output Voltage 2 "H" Output Voltage 1 *3 Segment and Common Driver Output Voltage "L" Output Voltage 2 *4 VOL2 Input Leakage Current *5 "L" Input Current *6 ILI2 IIL Input Capacitance CI IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Operating Current Consumption VDD = 5V XT = 32kHz OSC = 10MHz I OL = 3.2mA I = +10mA VDD1 = 1.4V, I = ±10mA VDD2 = 2.8V, I = ±10mA VDD3 = 4.2V, I = –10mA VI = VDD/0V VI = 0V, VDD = 5V f = 1MHz, Ta = 25˚C Stop mode, during LCD stop, no load *7 Stop mode, during LCD operation, no load*7 CPUCLK = 32kHz, HALT mode *8 CPUCLK = 32kHz, no load *9 CPUCLK = 10MHz, HALT mode CPUCLK = 10MHz, no load Min. Max. 2.4 0.75VDD 0.75VDD 0.75VDD 0.8 0.4 —— 0.4 —— 0.4 —VDD1–0.4 V DD1+0.4 —VDD2–0.4 V DD2+0.4 —VDD3–0.4 — —— ±10 –200–40 –400 5—— 7—1 4 15—3 0 30—6 0 80— 160 8—1 6 20—5 0 mA mA mA mA mA mA pF mA V (GND = 0V, Ta = –20 to +70˚C) *1 Excluding OSC0 and RESET *2 Only for OSC0 and RESET *3 Excluding P4 *4 Only for P4 *5 Excluding RESET *6 Only for RESET *7 Including hardware stop mode *8 Measured when OSC clock is stopped but LCD is operated without load *9 Measured when OSC clock is stopped

¡ Semiconductor MSM65354/65353A DC Characteristics 2 (2.7V £££££ VDD < 4.5V) Parameter Symbol Condition Typ. Unit "H" Input Voltage 1 VIH1 — "H" Input Voltage 2 VIH2 — VIL —"L" Input Voltage VOH1 — CPUCLK=1MHz IOH = –10mA —IOH = –20mA "L" Output Voltage 1 VOL1 IOL = 10mA — CPUCLK=1MHz CPUCLK=1MHz VOH2"H" Output Voltage 2 "H" Output Voltage 1 *3 Segment and Common Driver Output Voltage "L" Output Voltage 2 *4 VOL2 Input Leakage Current *5 "L" Input Current *6 ILI2 IIL Input Capacitance CI IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Operating Current Consumption VDD = 3V XT = 32kHz OSC = 5MHz I OL = 20mA I = +10mA VDD1 = 1.4V, I = ±10mA VDD2 = 2.8V, I = ±10mA VDD3 = 4.2V, I = –10mA VI = VDD/0V VI = 0V, VDD = 3V f = 1MHz, Ta = 25˚C Stop mode, during LCD stop, no load *7 Stop mode, during LCD operation, no load*7 CPUCLK = 32kHz, HALT mode *8 CPUCLK = 32kHz, no load *9 CPUCLK = 5MHz, HALT mode CPUCLK = 5MHz, no load Min. Max. 0.3VDD +0.9 0.6VDD +0.6 0.75VDD 0.75VDD 0.3VDD –0.1 0.1 —— 0.1 —— 0.4 —VDD1–0.4 V DD1+0.4 —VDD2–0.4 V DD2+0.4 —VDD3–0.4 — —— ±10 –125–40 –250 5—— 4—8 8—1 6 15—3 0 45—9 0 1.5—3 5—1 6 mA mA mA mA mA mA pF mA V (GND = 0V, Ta = –20 to +70˚C) *10 *11 *1 Excluding OSC0 and RESET *2 Only for OSC0 and RESET *3 Excluding P4 *4 Only for P4 *5 Excluding RESET *6 Only for RESET *7 Including hardware stop mode *8 Measured when OSC clock is stopped but LCD is operated without load *9 Measured when OSC clock is stopped *10 More than 3.375V *11 Less than 0.8V

¡ Semiconductor MSM65354/65353A AC Characteristics

  • CPU control
  • Peripheral control 1 Parameter Symbol Condition Unit tC VDD = 4.5 to 5.5V Min. Max. (VDD = 2.7 to 5.5V, GND = 0V, Ta = –20 to +70˚C) 100 ns OSC Clock Cycle — 0.55t C0.45tC EXI External Interrupt Pulse Width tEXIW External Clock Pulse Width tT0CW GATE Pulse Width tT0GW 4CPUCLK 4CPUCLK 4 tT0CLK 2.7V £ VDD < 4.5V — 200 Clock "L" Pulse Width tCLW
  • Peripheral control 2 Parameter Symbol Condition Unit tC VDD = 4.5 to 5.5V MIN MAX (VDD = 2.7 to 5.5V, GND = 0V, Ta = –20 to +70˚C) 100 ns OSC Clock Cycle 2.7V £ VDD < 4.5V — 200 SFTCK Cycle tSFC0, 1 SFT0, 1 SFTCK "L" Pulse Width tSFCLW0, 1 SFTCK "H" Pulse Width tSFCHW0, 1 CL = 100 pF 8CPUCLK 4CPUCLK –20 4CPUCLK –20 SFTO Setup Time tSFOS0, 1 SFTO Hold Time tSFOH0, 1 SFTI Setup Time tSFIS0, 1 SFTI Hold Time tSFIH0, 1 tSFCLW0, 1 –100 tSFCHW0, 1 –100 100 100 *1 CPUCLK : Supply clock to the CPU selected by SBYCON. See Timing Diagram. *1 CPUCLK : Supply clock to the CPU selected by SBYCON. *2 tT0CLK : Cycle time of timer 0 count clock selected by T0CON. RESET Pulse Width tRESW (VDD = 2.7 to 5.5V, GND = 0V, Ta = –20 to +70˚C) ns Parameter Symbol Condition Unit Min. Max. —20

¡ Semiconductor MSM65354/65353A A/D Converter Characteristics 1 * The conversion time immediately after GO bit is set to "1" is 14.8 ms/CH. Resolution n (VDD = AVDD = VRH = 4.5 to 5.5V, GND = AGND = 0V, Ta = –20 to +70˚C) Parameter Symbol Condition Unit Refer to recommended circuit. Analog input source impedance RI £ 5kW/CR Typ. Max. Min. Linearity Error EL bit Differential Linearity Error ED Zero Scale Error EZS Full Scale Error Crosstalk ECT EFS Conversion Time* tCONV +1.5—— LSB –1.5 ±0.5—— LSB +1.5—— LSB –1.5—— LSB ±0.5—— LSB —16— ms/CH Refer to measuring circuit. fOSC = 10MHz A/D Converter Characteristics 2 * The conversion time immediately after GO bit is set to "1" is 29.6 ms/CH. Resolution n (VDD = AVDD = VRH, 2.7V £ VDD < 4.5V, GND = AGND = 0V, Ta = –20 to +70˚C) Parameter Symbol Condition Unit Refer to recommended circuit. Analog input source impedance RI £ 5kW/CR Typ. Max. Min. Linearity Error EL bit Differential Linearity Error ED Zero Scale Error EZS Full Scale Error Crosstalk ECT EFS Conversion Time* tCONV +2—— LSB ±1—— LSB +2—— LSB –2—— LSB ±1—— LSB —32— ms/CH Refer to measuring circuit. fOSC = 5MHz

¡ Semiconductor MSM65354/65353A Resolution Definition of Terms Recognizable minimum input analog value. This can be resolved into 28 = 256, that is VRH ÷ 256 Linearity Error Deviation between ideal conversion characteristics as an 8-bit A/D converter and actual conversion characteristics. (Not including quantization error.) Ideal conversion characteristics means a step which divides voltage between V RH and AGND into 256. Differential Linearity Error Shows the smoothness of conversion characteristics. 1LSB = V RH ÷ 256 is ideal for analog input voltage width corresponding to change per 1 bit of digital output. The differential linearity error is the deviation between this ideal bit size and a bit size at arbitrary point in conversion range. Zero Scale Error Deviation between ideal conversion characteristics of transfer point for digital outputs "000H" to "001H" and actual conversion characteristics. Full Scale Error Deviation between ideal conversion characteristics of transfer point for digital outputs "0FEH" to "0FFH" and actual conversion characteristics.

¡ Semiconductor MSM65354/65353A

  • Recommended circuit
  • Crosstalk measuring circuit AI0 AI7 Analog Voltage Input 0.1 µF 5kW AI1 to VREF or AGND Crosstalk is defined as the difference of A/D conversion result between supplying the same voltage to AI0 to AI7 and supplying voltage shown in this left diagram. MSM65354 /MSM65353A VRH AI0-7 AGND AVDD VDD GND Analog Voltage Input 0.1 µF 0.1 µF µF VDD RI (Analog input source impedance) £ 5kW RI

¡ Semiconductor MSM65354/65353A RESET tRESW 1) RESET Pulse width

  • Peripheral control 1 OSC0 tC tCLW INT0 - 2 tEXIW 1) EXI Pulse width T0CK tT0CW GATE tT0GW 2) T0 Timing Diagram
  • CPU control

¡ Semiconductor MSM65354/65353A

  • Peripheral control 2 SFTO SFTI tSFIS 1) SFT0, 1 SFTCK tSFIH tSFOS tSFOH tSFCLW tSFCHW tSFC

¡ Semiconductor MSM65354/65353A (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFP100-P-1420-0.65-BK4 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.54 TYP. Mirror finish