MSM6242B OKI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
¡ Semiconductor MSM6242B
DESCRIPTION
The MSM6242B is a silicon gate CMOS Real Time Clock/Calendar for use in direct bus- connection Microprocessor/Microcomputer applications. An on-chip 32.768 KHz crystal oscillator time base is divided to provide ad- dressable 4-bit I/O data for SECONDS, MINUTES, HOURS, DAY OF WEEK, DATE, MONTH and YEAR. Data access is controlled by 4-bit address, chip selects ( CSO, CS1), WRITE, READ, and ALE. Control Registers D, E and F provide for 30 SECOND error adjustment, INTERRUPT REQUEST (IRQ FLAG) and BUSY status bits, clock STOP, HOLD, and RESET FLAG bits, 4 selectable INTERRUPTS rates are available at the STD.P ¡ Semiconductor MSM6242B DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR (STANDARD PULSE) output utilizing Con- trol Register inputs T0, T1 and the ITRPT/ STND (INTERRUPT/STANDARD). Mask- ing of the interrupt output (STD.P) can be accomplished via the MASK bit. The MSM6242B can operate in a 12/24 hour for- mat and Leap Year timing is automatic. The MSM6242B normally operates from a 5V –10% supply at –40 to 85°C. Battery backup operation down to 2.0V allows continuation of time keeping when main power is off. The MSM6242B is offered in a 18-pin plastic DIP and a 24-pin plastic Small Outline package.
FEATURES
DIRECT MICROPROCESSOR/MICROCONTROLLER BUS CONNECTION TIME MONTH DATE YEAR DAY OF WEEK 23:59:59 12 31 80 7
- 4-bit data bus
- 4-bit address bus
- READ, WRITE, ALE and CHIP SELECT INPUTS
- Status registers – IRQ and BUSY
- Selectable interrupt outputs – 1/64 second, 1 second, 1 minute, 1 hour
- Interrupt masking
- 32.768 KHz crystal controlled operation
- 12/24 hour format
- Auto leap year
- –30 second error correction
- Single 5V supply
- Battery backup down to V DD = 2.0V
- Low power dissipation: 20mW max at VDD = 2V 150mW max at VDD = 5V
- 18 pin Plastic DIP (DIP18-P-300)
- 24 Pin-V Plastic SOP (SOP24-P-430-VK)
¡ SemiconductorMSM6242B FUNCTIONAL BLOCK DIAGRAM GATE & LATCH GATE GATE DECODER RESET bit STOP bit bit ADJ HOLD bit BUSY bit 30 sec ADJ bit 24/12bit S10 MI1 H1 WMI10 H10 D1 D10 MO1 Y1MO10 Y10 CD CE CF 64Hz 1-sec carry 1-min carry 1-hour carry STDP S CF XT COUNTEROSC 1 Hz32.768KHz XT ALE CS1 CS0 WR RD S1~W~Y10 are time counter register C0~CF are control register 18 pin Plastic DIP 1 18STD.P CS0 ALE GND VDD CS1 XT2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 24 pin Plastic Small Outline Package PIN CONFIGURATION RD XT WR STD.P NC ALE NC NC GND VDD CS1 XT XT WR NC NC NC CS0 RD A 0-A3: D0-D3: CSO , CS1: RD: ALE: STD.P: VDD: VSS: Address input Data input/output CHIP SELECTS 0,1 READ enable WRITE enable Address latch enable Standard pulse output XTAL oscillator input/output +5V supply ground WR: XT, XT:
Bit * does not exist (unrecognized during a write and held at "0" during a read). Be sure to mask the AM/PM bit when processing 10's of hour's data. PM at 1 and AM at 0 for PM / AM bit. Figure 1. Register Table
Figure 2. Frequency Deviation (PPM) vs Temperature Figure 3. Frequency Deviation (PPM) vs Voltage
- The graghs above showing frequency deviation vs temperature/voltage are primarily characteristic of the
MSM6242B with the oscillation circuit described below.
¡ Semiconductor MSM6242B Parameter Symbol Condition Rating Unit Power Supply Voltage Input Voltage Output Voltage Storage Temperature Ta = 25°C ABSOLUTE MAXIMUM RATINGS -0. 3 to 7 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -55 to +150 VDD VI VO TSTG V V V Parameter Symbol Condition Rating Unit Power Supply Voltage Standby Supply Voltage Crystal Frequency Operating Temperature OPERATING CONDITIONS 4 to 6 2 to 6 32.768 -40 to +85 V DD VBAK f(XT) TOP kHz V Parameter Condition Min. Unit "H" Input Voltage "L" Input Voltage Input Leak Current Input Leak Current "L" Output Voltage "H" Output Voltage "L" Output Voltage OFF Leak Current D.C. Characteristics Current Con- sumption Current Con- sumption "H" Input Voltage "L" Input Voltage Input Capacitance All input termin- als except CS1, XT Input terminals other than D0 ~ D3, XT D0 ~ D3 D0 ~ D3 STD.P All input terminals VDD CS1 Applicable Terminal VI = VDD/0V KHz CS1 0 VDD = VDD = f(xt) = 32.768 Symbol VIH1 VIL1 ILK1 ILK2 VOL1 VOH VOL2 IOFFLK CI IDD1 IDD2 VIH2 VIL2 IOL = 2.5mA IOH = -400µA IOL = 2.5mA V = VDD/0V VDD = 2 ~ 5.5V Input frequency 1MHz V µA PF V V µA µA V Typ. Max. 2.2 2.4 4/5VDD 0.8 1/-1 10/-10 0.4 0.4 1/5V DD —~~
1 Hold Time
Figure 4. Write Cycle — (ALE = V DD)
Figure 7. Read Cycle — (With Use of ALE)
December 1, 1985 at the exact time at which a carry pulse occurs for the day's digit. f) The Register W data limits are 0 – 6 (Tabel 1 shows a possible data definition). Figure 10. Reading and Writing of Registers S1 ~ W 16KHz. It is recommended to allow an idling time of 62ms or more.
¡ Semiconductor MSM6242B CD REGISTER (Control D Register) a) HOLD (D0) – Setting this bit to a "1" inhibits the 1Hz clock to the S1 counter, at which time the Busy status bit can be read. When Busy = 0, register's S1 ~ W can be read or written. During this procedure if a carry occurs the S1 counter will be incremented by 1 second after HOLD = 0 (this condition is guaranteed as long as HOLD = 1 does not exceed 1 second in duration). If CS1 = 0 then HOLD = 0 irrespective of any condition. b) BUSY (D1) – Status bit which shows the interface condition with microcontroller/ microprocessors. As for the method of writing into and reading from S 1 ~ W (address f ~ C), refer to the flow chart described in Figure 10. c) IRQ FLAG (D2) – This status bit corresponds to the output level of the STD.P output. When STD.P = 0, then IRQ = 1; when STD.P = 1, then IRQ = 0. The IRQ FLAG indicates that an interrupt has occurred to the microcomputer if IRQ = 1. When D0 of register C E (MASK) = 0, then the STD.P output changes according to the timing set by D3 (t1) and D2 (t0) of register E. When D1 of register E (ITRPT/STND) = 1 (interrupt mode), the STD.P output remains low until the IRQ FLAG is written to a "0". When IRQ = 1 and timing for a new interrupt occurs, the new interrupt is ignored. When ITRPT/STND = 0 (Standard Pulse Output mode) the STD.P output remains low until either "0" is written to the IRQ FLAG; otherwise, the IRQ FLAG automatically goes to "0" after 7.8125ms. When writing the HOLD or 30 second adjust bits of register D, it is necessary to write the IRQ FLAG bit to a "1". d) –30 ADJ (D3) – When 30-second adjustment is necessary, a "1" is written to bit D3 during which time the internal clock registers should not be read from or written to 125ms after bit D3 = 1 it will automatically return to a "0", and at that time reading or writing of registers can occur. For example t1 = 0 and tO = 1 when required to a unit of second; t 1 = 1 and tO = 0 when required to a unit of minute; and t 1 = 1 and tO = 1 when required to a unit of hour; t1 *1 t0 *2 ITRPT/STNT 1 MASK 0 Reading Method 2 when Not Using HOLD Bit IRQ FLAG 0 IRQ FLAG = 0 WAIT t TIME DATA READ REGISTER CD READ Normal read YES NO See Note below Retried the reading, since a carry occurred during the operation. (Note) Do this process within the following time requirements by combination between t 1 and t0: t1 = 0 and tO = 1 . . . Less than 1 second t1 = 1 and tO = 0 . . . Less than 1 minute t1 = 1 and tO = 1 . . . Less than 1 hour t : 12 HOUR MODE . . . 35µS 24 HOUR MODE . . . 3µS Initialization only at power ON *1 and *2 represent the minimum required time out. t1 *1 t0 *2 ITRPT/STNT 1 MASK 0 Reading Method 3 when Not Using HOLD Bit IRQ FLAG 0 IRQ FLAG = 1 WAIT t TIME DATA READ REGISTER CD READ YES NO The other IC causes the interruption. The interruption is caused by this IC due to the occurrence of a carry. The IRQ FLAG is cleared to read the next time data. Initialization only at power ON *1 and *2 represent the minimum required time unit. CPU senses the interruption. END For example t1 = 0 and tO = 1 when required to a unit of second; t 1 = 1 and tO = 0 when required to a unit of minute; and t 1 = 1 and tO = 1 when required to a unit of hour;
¡ Semiconductor MSM6242B c) 24/12 (D2) – This bit is for selection of 24/12 hour time modes. If D2 = 1–24 hour mode is selected and the PM/AM bit is invalid. If D2 = 0–12 hour mode is selected and the PM/AM bit is valid. "24/HOUR/ Setting of the 24/12 hour bit is as follows:
12 HOUR" 1) REST bit = 1
2) 24/12 hour bit = 0 or 1 3) REST bit = 0 * REST bit must = 1 to write to the 24/12 hour bit. d) TEST (D3) – When the TEST flag is a "1", the input to the SECONDS counter comes from the counter/divider stage instead of the 15th divider stage. This makes the SECONDS counter count at 5.4163KHz instead of 1Hz. When TEST = 1 (Test Mode) the STOP & REST (Reset) flags do not inhibit internal counting. When Hold = 1 during Test (Test = 1) internal counting is inhibited; however, when the HOLD FLAG goes inactive (Hold = 0) counter updating is not guaranteed. STOP BIT TIMING OF "CARRY" TO 8192Hz "CARRY" EXECUTED "0" "1" "CARRY" NOT EXECUTED "1" "1" Figure 13 (EXAMPLE) WHEN t1 = 1, t0 = 1 and MASK = 0. PM12:00 WHEN ITRPT/STND BIT is "1" STD.P OUTPUT OPEN LOW LEVEL WHEN ITRPT/STND BIT is "0" PM1:00 OPEN LOW LEVEL The timing of the STD.P output designated by T1 and T0 occurs the moment that a carry occurs to a clock digit. d) The low-level pulse width of the fixed cycle waveform (ITRPT/STND = 0) is 7.8125ms independent of T0/T1 inputs. e) The fixed cycle waveform mode can be used for adjustment of the oscillator frequency time base. (See Figure 14). f) During –30 second adjustment a carry can occur that will cause the STD.P output to go low when T0/T1 = 1,0 or 1,1. However, when T1/T0 = 0, 0 and ITRPT/STND = 0, carry does not occur and the STD.P output resumes normal operation. g) The STD.P output is held (frozen) at the point at which STOP = 1 while ITRPT/STND = 0. h) No STD.P output change occurs as a result of writing data to registers S1 ~ H1. C F REGISTER (Control F Register) a) REST (D0) – This bit is used to clear the clock's internal divider/counter of less than a "RESET" second. When REST = 1, the counter is Reset for the duration of REST. In order to release this counter from Reset, a "0" must be written to the REST bit. If CSI = 0 then REST = 0 automatically. b) STOP (D1) – The STOP FLAG Only inhibits carries into the 8192Hz divider stage. There may be up to 122 ms delay before timing starts or stops after changing this flag; 1 = STOP/0 = RUN.
¡ SemiconductorMSM6242B TYPICAL APPLICATION INTERFACE WITH MSM6242B AND MICROCONTROLLERS CS0 ALE RD WR AD AD2 AD1 AD0 A8 ~ A15 IO/M ALE RD WR
8085 MSM6242B
Figure 15. DECODER CS0 ALE RD WR A/D A 8 ~ A15 IO/M RD WR A4 ~ A15 IORQ MREQ RD WR Z80 MSM6242B DECODER VDD Figure 16. MEMORY MAPPED CS0 ALE RD WR ALE RD WR MCS48 MSM6242B DECODER Figure 17. CS0 ALE BUS3 BUS2 BUS1 BUS0 BUS 4-7 A8 ~ A12 DECODER Note : If 8085 does not enter into the state of HALT or HOLD during CS1 = "H" of MSM6242B, R1 and R2 are not required. Note : It depends upon the switching characterisrics decided by a X'tal used for a Z80 that either of IORQ and MREQ is used.
¡ Semiconductor MSM6242B TYPICAL APPLICATIONS — INTERFACE WITH MSM80C49 Figure 18. INT ALE RD WR MSM 80C49RS DB0 DB1 DB2 DB3 DB7 VDD P17 VSS 10KTR1 VDD SDT.P ALE RD WR MSM 6242BRS A/D0 A/D1 A/D2 A/D3 CS0 CS1 820 X VCC P27 VSS XT XT
32.768 KHz
H 26 18K LITHIUM BATTERY H3.9V 100µf H (VFWD = < 0.3V) i.e. GERMANIUM
4.553 KHz
4.7µf (tantalum) TR2 220 1.8K 1.8K 1.8K TR3 H H 1.8K 1.8K 10µf 5.2V TR1 = 2N2907 TR2 = 2N2907 TR3 = 2N2222 H = 1N4148 RS232 INTERFACE RS232 DB25 CONNECTOR 220
¡ SemiconductorMSM6242B 2. Adjustment of Frequency VDD XT XT SDT.P 18 17 16 12 3 VDD Frequency counter Screwdriver Eye CD ~ CF are to be set at as described in the figure and the capacitor is to be adjusted to meet the settle frequency of t 0 and t1. If the right oscillation can not be obtained, 1. Check the waveform of XT 2. Check CD ~ CF content 3. Check the noise VDD XT XT a b cd a b 0.1 INCH : INHIBIT 2 1 1 ‡ 0.3 INCH ‡ 0.2 INCH2 VDD Set the current time START Power On APPLICATION NOTE 1. Power Supply TEST Bit ‹ 0 REST Bit ‹ 0 24/12 Bit ‹ 1* STOP Bit ‹ 1 HOLD Bit ‹ 0 STOP Bit ‹ 0 Start Operation VDD = 5V STD.P Output = undifined 1* = 2* (1 or 0) REST Bit ‹ 0 24/12 Bit ‹ 2*
¡ Semiconductor MSM6242B 3. CH1 (Chip Select) VIH and VIL of CH1 has 3 functions. a) To accomplish the interface with a microcontroller/microprocessor. b) To inhibit the control bus, data bus and address bus and to reduce input gate pass current in the stand-by mode. c) To protect internal data when the mode is moved to and from standby mode. To realize the above functions: a) More than 4/5 V DD shoud be applied to the MSM6242B for the interface with a microcontroller/microprocessor in 5V operation. b) In moving to the standby mode, 1/5 V DD should be applied so that all data buses should be disabled. In the standby mode, approx. 0V should be applied. c) To and from the standby mode, obey following Timing chart. To Standby Mode VDD CS1 From Standby Mode 4 ~ 6V 2 ~ 4V 4V 4V 2µs (MIN) VDD 2µs (MIN) VDD VDD CS0 : H or WR : H YES NO 4. Set SDT.P at alarm mode Set alarm at 9:00 Read Register CD D2 = 1? AM 9:00? Read H10 and H10 Cotent MASK BIT ‹ 0 ITRPT/STND BIT ‹ 1 t1, t0 ‹ 1 Start interruption CPU Activation CPU HALT or CPU STAND BY Repeat YES NO