MSM512200 OKI | Alldatasheet

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Technical content

¡ Semiconductor MSM512200/L

DESCRIPTION

The MSM512200/L is a 1,048,576-word ¥ 2-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM512200/L achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM512200/L is available in a 26/20-pin plastic SOJ or 26/20-pin plastic TSOP. The MSM512200L (the low-power version) is specially designed for lower-power applications.

FEATURES

  • 1,048,576-word ¥ 2-bit configuration
  • Single 5 V power supply, ±10% tolerance
  • Input : TTL compatible, low input capacitance
  • Output : TTL compatible, 3-state
  • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
  • Fast page mode, read modify write capability
  • CAS before RAS refresh, hidden refresh, RAS-only refresh capability
  • Multi-bit test mode capability
  • Package options: 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM512200/L-xxSJ) 26/20-pin 300 mil plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product : MSM512200/L-xxTS-K) xx indicates speed rank. PRODUCT FAMILY ¡ Semiconductor MSM512200/L 1,048,576-Word ¥ 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE MSM512200/L-70 70 ns 130 ns 150 ns 385 mW 330 mW 5.5 mW/ Family Access Time (Max.) Cycle Time (Min.) Standby (Max.) Power Dissipation MSM512200/L-80 tRAC 80 ns 35 ns tAA 40 ns 20 ns tCAC 20 ns 20 ns tOEA 20 ns MSM512200/L-60 60 ns 110 ns 440 mW 30 ns 15 ns 15 ns Operating (Max.) 0.55 mW (L-version) E2G0017-17-42 This version: Jan. 1998 Previous version: May 1997

¡ Semiconductor MSM512200/L PIN CONFIGURATION (TOP VIEW) WE RAS VCC CAS1 CAS2 OE DQ2 25 NC DQ1

26 VSS

(K Type) Pin Name Function A0 - A9 Address Input RAS Row Address Strobe CAS1, CAS2 Column Address Strobe DQ1, DQ2 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (5 V) NC No Connection VSS Ground (0 V)

¡ Semiconductor MSM512200/L BLOCK DIAGRAM Timing Generator RAS CAS1 CAS2 Timing Generator Column Address Buffers Internal Address Counter Row Address Buffers A0 - A9 VCC VSS On Chip VBB Generator Row De- coders Word Drivers Memory Cells Refresh Control Clock Sense Amplifiers Column Decoders Write Clock Generator I/O Selector Output Buffers WE OE DQ1, DQ2 Input Buffers

¡ Semiconductor MSM512200/L

ELECTRICAL CHARACTERISTICS

Recommended Operating Conditions Capacitance *: Ta = 25°C Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature VT Symbol IOS PD* Topr Tstg –1.0 to 7.0 0 to 70 –55 to 150 Rating mA W Parameter V Unit Power Supply Voltage Input High Voltage Input Low Voltage VCC Symbol VSS VIH VIL 5.0 Typ. Parameter 4.5 2.4 –1.0 Min. 5.5 6.5 0.8 Max. (Ta = 0°C to 70°C) V Unit V V V Input Capacitance (A0 - A9) Input Capacitance Output Capacitance (DQ1, DQ2) CIN1 Symbol CIN2 CI/O Max. pF Unit pF pF Parameter (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Typ. (RAS, CAS1, CAS2, WE, OE)

¡ Semiconductor MSM512200/L DC Characteristics Parameter Symbol Condition MSM512200 /L-60 MSM512200 /L-70 MSM512200 /L-80 (VCC = 5 V ±10%, Ta = 0°C to 70°C) IOH = –5.0 mA Output High Voltage IOL = 4.2 mA Output Low Voltage 0 V £ VI £ 6.5 V; All other pins not Input Leakage Current under test = 0 V DQ disable Output Leakage Current 0 V £ VO £ 5.5 V RAS, CAS1, CAS2 Average Power tRC = Min. Supply Current (Operating) RAS, CAS1, CAS2 = VIH Power Supply RAS, CAS1, CAS2 Current (Standby) RAS cycling, Average Power CAS1, CAS2 = VIH, Supply Current tRC = Min. (RAS-only Refresh) RAS = VIH, Power Supply CAS1, CAS2 = VIL, Current (Standby) DQ = enable Average Power CAS1, CAS2 Supply Current (CAS before RAS Refresh) RAS = VIL, Average Power CAS1, CAS2 cycling, Supply Current tPC = Min. (Fast Page Mode) tRC = 125 ms, Average Power VOH VOL ILI ILO ICC1 ICC2 ICC3 ICC5 ICC6 ICC7 ICC10 CAS1, CAS2 Supply Current (Battery Backup) ≥ VCC –0.2 V Min. 2.4 –10 –10 Max. VCC 0.4 200 100 Min. 2.4 –10 –10 Max. VCC 0.4 200 100 Min. 2.4 –10 –10 Max. VCC 0.4 200 100 Unit V V mA mA mA mA mA mA mA mA mA mA Note 1, 2 1, 2 1, 2 1, 3 1, 4, 1, 5 RAS cycling, cycling, before RAS before RAS, tRAS £ 1 ms Notes : ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS1, CAS2 = VIH. L-version.

¡ Semiconductor MSM512200/L AC Characteristics (1/2) Parameter Random Read or Write Cycle Time (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 MSM512200 /L-60 Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from OE Output Low Impedance Time from CAS Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width (Fast Page Mode) RAS Hold Time CAS Precharge Time (Fast Page Mode) CAS Pulse Width RAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time Access Time from CAS Precharge OE to Data Output Buffer Turn-off Delay Time RAS Hold Time referenced to OE Note 4, 5, 6 4, 5 4, 6 4, 14 RAS Hold Time from CAS Precharge CAS to Data Output Buffer Turn-off Delay Time Symbol tRC tRWC tPC tPRWC tRAC tCAC tAA tOEA tCLZ tOFF tT tREF tREF tRP tRAS tRASP tRSH tCP tCAS tCSH tCRP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL tCPA tOEZ tROH tRHCP Min. 110 150 Max. 128 10,000 100,000 10,000 Unit ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. 130 180 Max. 128 10,000 100,000 10,000 Max. 128 10,000 100,000 10,000 Min. 150 200 100 MSM512200 /L-70 MSM512200 /L-80

¡ Semiconductor MSM512200/L AC Characteristics (2/2) Symbol Parameter Read Command Set-up Time tRCS Read Command Hold Time tRCH MSM512200 /L-60 Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time tRRH tWCS tWCH tWCR tWP tRWL tCWL tDS Data-in Hold Time tDH Data-in Hold Time from RAS tDHR CAS to WE Delay Time tCWD Column Address to WE Delay Time tAWD RAS to WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tRWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH OE Command Hold Time tOEH OE to Data-in Delay Time tOED (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 CAS Precharge WE Delay Time tCPWD Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. Min. Max. Min. 105 Max. MSM512200 /L-70 MSM512200 /L-80 Note 8, 13 9, 13 9, 14 10, 13 10, 13

¡ Semiconductor MSM512200/L Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA0 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 13. These parameters are determined by the falling edge of either CAS1 or CAS2, whichever is earlier. 14. These parameters are determined by the rising edge of either CAS1 or CAS2, whichever is later. 15. tCWL, tDH and tDS should be satisfied by both CAS1 and CAS2. 16. tCP is determined by the time both CAS1 and CAS2 are high.

¡ Semiconductor MSM512200/L Notes concerning CAS1 and CAS2 control Overlap the active-low timings of CAS1 and CAS2. Skew between CAS1 and CAS2 is allowed under the following conditions: (1) The timing specification for CAS1 and CAS2 should be met individually. (2) Different operation modes for CAS1/CAS2 are not allowed (as shown below). RAS CAS1 CAS2 WE Delayed write Early write (3) Closely separated CAS1/CAS2 control is not allowed. However, when the condition (tCP ≤ tUL) is satisfied, fast page mode can be performed. RAS CAS1 CAS2 tUL

¡ Semiconductor MSM512200/L "H" or "L" RAS CAS VIH VIL VIH VIL DQ VOH VOL Address VIH VIL WE VIH VIL OE VIH VIL tRC tRAS tRP tAR tCRP tCSH tCRP tRCD tRSH tCAS tRAD tASR tRAH tASC tCAH tRAL Row Column tRCS tRRH tRCH tAA tROH tOEA tCAC tRAC tOEZ tOFF Open tCLZ Valid Data-out "H" or "L" RAS CAS VIH VIL VIH VIL DQ VIH VIL Address VIH VIL WE VIH VIL OE VIH VIL tRC tRAS tRP tAR tCRP tRCD tCSH tRSH tCRP tCAS tRAD tRAH tASR tASC tCAH Row Column tWCS tWCH tWCR tDHR tDS tDH Valid Data-in tWP tRAL Open tCWL tRWL TIMING WAVEFORM Read Cycle Write Cycle (Early Write) E2G0094-17-41G

¡ Semiconductor MSM512200/L Read Modify Write Cycle "H" or "L" RAS CAS VIH VIL VIH VIL DQ VI/OH VI/OL Address VIH VIL WE VIH VIL OE VIH VIL tRWC tRAS tRP tAR tCRP tCSH tRCD tCRP tRSH tCAS tASR tRAH tASC tCAH Row Column tCWD tCWL tRWD tRWL tWP tAA tAWD tOEA tOED tCAC tRAC tOEZ tDS tDH tCLZ Valid Data-out Valid Data-in tRAD tRCS tOEH

¡ Semiconductor MSM512200/L Fast Page Mode Read Cycle Fast Page Mode Write Cycle (Early Write) "H" or "L" RAS CAS VIH VIL VIH VIL DQ VIH VIL Address VIL WE VIH VIL tRASP tRP tAR tCRP tRCD tCAS tCP tCAS tRSH tCRP tCAS tASR tRAH tCAH tCSH tASC tCAH tASC tCAH tRAL Row Column Column Column tRAD tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH tWP tDS tDH tDS tDH tDS tDH Valid Data-in Valid Data-in Valid Data-in tDHR Note: OE = "H" or "L" VIH tASC tPC tRHCP tCP tCWL tCWL tRWL tCWL tWCR "H" or "L" RAS CAS VIH VIL VIH VIL DQ VOH VOL Address VIH VIL WE VIH VIL OE VIH VIL tRASP tRP tAR tCRP tRCD tPC tRSH tCRP tCAS tCAS tCP tCAS tRAD tASR tRAH tASC tCAH tCSH tASC tCAH tASC tCAH tRAL Row Column Column Column tRCS tRCH tRCS tRCS tRCH tAA tOEA tAA tAA tRRH tOEA tOEA tCAC tRAC tOFF tOEZ tCAC tCLZ tOFF tOEZ tCAC tCLZ tOEZ tOFF tCLZ Valid Data-out Valid Data-out Valid Data-out tRHCP tCP tRCH tCPA tCPA

¡ Semiconductor MSM512200/L Fast Page Mode Read Modify Write Cycle tWP RAS CAS Address OE VIH VIL VIH VIL VIH VIL VIH VIL WE VIH VIL DQ VI/OH VI/OL tRASP tAR tRP tCSH tPRWC tRSH tRCD tCAS tCP tCAS tCP tCAS tCRP tRAD tRAH tASR tASC tCAH tASC tCAH tASC tCAH tRAL Row Column Column Column tRWD tRCS tCWD tCWL tCWD tCWL tCWD tRWL tCWL tAWD tAWD tAWD tOEA tWP tOEA tWP tOEA tAA tOED tCAC tDS tDH tCAC tAA tRAC tDS tDH tCPA tOED tCAC tAA tDS tDH tCLZ tCLZ tCLZ Out In Out Out In In tROH tOEZ tOEZ tCPA tOED tRCS tRCS tCPWD tCPWD "H" or "L" tOEZ RAS-Only Refresh Cycle RAS CAS VIH VIL VIH VIL Address VIH VIL tRC tRAS tRP tCRP tRPC tASR tRAH Row "H" or "L" DQ VOH VOL Note: WE, OE = "H" or "L" Open tOFF

¡ Semiconductor MSM512200/L RAS CAS VIH VIL VIH VIL Column Row DQ VOH VOL WE VIH VIL OE VIH VIL Address VIH VIL tRC tRC tRAS tRP tRAS tRP tAR tCRP tRCD tRSH tCHR tRAD tASR tASC tRAH tCAH tRCS tRAL tRRH tAA tROH tOEA tCAC tCLZ tRAC tOFF tOEZ Valid Data-out "H" or "L" CAS before RAS Refresh Cycle Hidden Refresh Read Cycle P Q R S K L M VIH VIL RAS tRP CAS VIH VIL VIH VIL WE V V tRC tRAS tRPC tCHR tRP tRPC tCP tCSR tWRP tWRH tOFF tWRP Open OL OH – DQ Note: OE, Address = "H" or "L" "H" or "L"

¡ Semiconductor MSM512200/L Hidden Refresh Write Cycle Test Mode Initiate Cycle tASR Row Column VIH VIL RAS Address WE CAS VIH VIL VIH VIL VIH VIL tCRP tRC tASC tRP tRAS tRCD tRSH tRAD tCAH tRAH tRAL DQ VIH VIL tWCS tCHR tRAS tWRH tWRP tRC tRP tAR OE VIH VIL tDHR tDS tWP tWCH tDH Valid Data-in "H" or "L" VIH VIL RAS CAS VIH VIL tRAS VOH VOL VIH VIL Open tRC tWTH tRPC tWTS tCP tCSR tCHR tOFF Note: OE, Address = "H" or "L" tRP WE DQ "H" or "L"

¡ Semiconductor MSM512200/L (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Mirror finish

¡ Semiconductor MSM512200/L (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). TSOPII26/20-P-300-1.27-K Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.38 TYP. Mirror finish