MSM512100 OKI | Alldatasheet

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¡ Semiconductor MSM512100/L

DESCRIPTION

The MSM512100/L is a 2,097,152-word ¥ 1-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM512100/L achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM512100/L is available in a 26/20-pin plastic SOJ. The MSM512100L (the low-power version) is specially designed for lower-power applications.

FEATURES

  • 2,097,152-word ¥ 1-bit configuration
  • Single 5 V power supply, ±10% tolerance
  • Input : TTL compatible, low input capacitance
  • Output : TTL compatible, 3-state
  • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
  • Fast page mode, read modify write capability
  • CAS before RAS refresh, hidden refresh, RAS-only refresh capability
  • Multi-bit test mode capability
  • Package: 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM512100/L-xxSJ) xx indicates speed rank. PRODUCT FAMILY ¡ Semiconductor MSM512100/L 2,097,152-Word ¥ 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE MSM512100/L-70 70 ns 130 ns 150 ns 385 mW 330 mW 5.5 mW/ Family Access Time (Max.) Cycle Time (Min.) Standby (Max.) Power Dissipation MSM512100/L-80 tRAC 80 ns 35 ns tAA 40 ns 20 ns tCAC 20 ns MSM512100/L-60 60 ns 110 ns 440 mW 30 ns 15 ns Operating (Max.) 0.55 mW (L-version) 20 ns tOEA 20 ns 15 ns E2G0016-17-41 This version: Jan. 1998 Previous version: May 1997

¡ Semiconductor MSM512100/L PIN CONFIGURATION (TOP VIEW) RAS NC A10R VCC CAS OE WE

25 DOUT

26 VSS

A0 - A9, A10R Address Input RAS Row Address Strobe CAS Column Address Strobe DIN Data Input DOUT Data Output WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection OE Output Enable

¡ Semiconductor MSM512100/L BLOCK DIAGRAM WE Timing Generator Timing Generator Column Decoders Write Clock Generator Sense Amplifiers I/O Selector Output Buffer DOUT DIN Input Buffer Memory Cells Row Address Buffers On Chip VBB Generator VCC VSS Internal Address Counter Column Address Buffers Refresh Control Clock A0 - A9 RAS CAS Row De- coders Word Drivers A10R OE

¡ Semiconductor MSM512100/L

ELECTRICAL CHARACTERISTICS

Recommended Operating Conditions Capacitance *: Ta = 25°C Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature VT Symbol IOS PD* Topr Tstg –1.0 to 7.0 0 to 70 –55 to 150 Rating mA W Parameter V Unit Power Supply Voltage Input High Voltage Input Low Voltage VCC Symbol VSS VIH VIL 5.0 Typ. Parameter 4.5 2.4 –1.0 Min. 5.5 6.5 0.8 Max. (Ta = 0°C to 70°C) V Unit V V V Input Capacitance (A0 - A9, A10R, DIN) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DOUT) CIN1 Symbol CIN2 COUT Max. pF Unit pF pF Parameter (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Typ.

¡ Semiconductor MSM512100/L DC Characteristics Parameter Symbol Condition MSM512100 /L-60 MSM512100 /L-70 MSM512100 /L-80 (VCC = 5 V ±10%, Ta = 0°C to 70°C) IOH = –5.0 mA Output High Voltage IOL = 4.2 mA Output Low Voltage 0 V £ VI £ 6.5 V; All other pins not Input Leakage Current under test = 0 V DOUT disable Output Leakage Current 0 V £ VO £ 5.5 V RAS, CAS cycling, Average Power tRC = Min. Supply Current (Operating) RAS, CAS = VIH Power Supply RAS, CAS Current (Standby) RAS cycling, Average Power CAS = VIH, Supply Current tRC = Min. (RAS-only Refresh) RAS = VIH, Power Supply CAS = VIL, Current (Standby) DOUT = enable Average Power CAS before RAS Supply Current (CAS before RAS Refresh) RAS = VIL, Average Power CAS cycling, Supply Current tPC = Min. (Fast Page Mode) tRC = 125 ms, Average Power VOH VOL ILI ILO ICC1 ICC2 ICC3 ICC5 ICC6 ICC7 ICC10 CAS before RAS, Supply Current tRAS £ 1 ms (Battery Backup) ≥ VCC –0.2 V Min. 2.4 –10 –10 Max. VCC 0.4 200 100 Min. 2.4 –10 –10 Max. VCC 0.4 200 100 Min. 2.4 –10 –10 Max. VCC 0.4 200 100 Unit V V mA mA mA mA mA mA mA mA mA mA Note 1, 2 1, 2 1, 2 1, 3 1, 4, 1, 5 RAS cycling, Notes : ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. L-version.

¡ Semiconductor MSM512100/L AC Characteristics (1/2) Parameter Random Read or Write Cycle Time (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 MSM512100 /L-60 Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Output Low Impedance Time from CAS Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width (Fast Page Mode) RAS Hold Time CAS Precharge Time (Fast Page Mode) CAS Pulse Width RAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time Access Time from CAS Precharge Note 4, 5, 6 4, 5 4, 6 RAS Hold Time from CAS Precharge CAS to Data Output Buffer Turn-off Delay Time Symbol tRC tRWC tPC tPRWC tRAC tCAC tAA tCLZ tOFF tT tREF tREF tRP tRAS tRASP tRSH tCP tCAS tCSH tCRP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL tCPA tRHCP Min. 110 130 Max. 128 10,000 100,000 10,000 Unit ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. 130 155 Max. 128 10,000 100,000 10,000 Max. 128 10,000 100,000 10,000 Min. 150 175 MSM512100 /L-70 MSM512100 /L-80 Access Time from OE tOEA ns OE to Data Output Buffer Turn-off Delay Time tOEZ ns ns RAS Hold Time referenced to OE tROH

¡ Semiconductor MSM512100/L AC Characteristics (2/2) Symbol Parameter Read Command Set-up Time tRCS Read Command Hold Time tRCH MSM512100 /L-60 Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time tRRH tWCS tWCH tWCR tWP tRWL tCWL tDS Data-in Hold Time tDH Data-in Hold Time from RAS tDHR CAS to WE Delay Time tCWD Column Address to WE Delay Time tAWD RAS to WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tRWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 CAS Precharge WE Delay Time tCPWD Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. Min. Max. Min. Max. MSM512100 /L-70 MSM512100 /L-80 Note OE Command Hold Time tOEH ns OE to Data-in Delay Time tOED ns

¡ Semiconductor MSM512100/L Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 4-bit parallel test function. RA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data output pin will indicate a high level. If any internal bits are not equal, the data output pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.

¡ Semiconductor MSM512100/L RAS CAS Address WE DOUT VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tRC tRAS tRP tCSH tCRP tRCD tRSH tCRP tCAS tRAD tRAL tASR tRAH tASC tCAH Row Column tAR tRCS tRCH tRRH tCAC tAA tCLZ tRAC tOFF Open Valid Data "H" or "L" OE VIH VIL tROH tOEA tOEZ TIMING WAVEFORM Read Cycle Write Cycle (Early Write) RAS CAS Address WE DOUT VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL "H" or "L" DIN VIH VIL tRC tRAS tRP tCSH tCRP tRCD tRSH tCRP tCAS tAR tRAD tRAL tRAH tASR tASC tCAH Row Column tCWL tWCR tWCS tWCH tRWL tDHR tDS tDH Valid Data Open tWP OE VIH VIL E2G0089-17-41B

¡ Semiconductor MSM512100/L Read Modify Write Cycle RAS CAS Address WE DOUT VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL "H" or "L" DIN VIH VIL tRWC tRP tRAS tCRP tRCD tRSH tRWL tCAS tCRP tCSH tAR tCWL tRAD tRAL tASR tRAH tASC tCAH Row Column tAWD tRWD tCWD tWP tRCS tDS tDH Valid Data tCAC tAA tRAC Open tCLZ OE VIH VIL tOEH tOED tOEA tOEZ Valid Data

¡ Semiconductor MSM512100/L Fast Page Mode Read Cycle RAS CAS Address WE DOUT VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL "H" or "L" DIN VIH VIL tRASP tRP tCRP tRCD tCAS tCP tPC tCAS tCP tCAS tRSH tCRP tAR tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRAL Row Column Column Column tRAD tWCR tWCS tWCH tWCS tWCH tWCS tWCH tDS tDH tDS tDH tDS tDH Valid Data Valid Data Valid Data Open tDHR tRHCP tWP tCWL tWP tWP tCWL tCWL tRWL Note: OE = "H" or "L" Fast Page Mode Write Cycle (Early Write) RAS CAS Address WE DOUT VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL "H" or "L" tRASP tRP tCSH tCRP tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tCRP tAR tASR tRAH tASC tCAH tASC tCAH tRAL tASC tCAH Row Column Column Column tRAD tRCS tRCH tRCS tRCH tRCS tRRH tRCH tCAC tAA tRAC tCAC tAA tCPA tCAC tAA tCPA Valid Data Valid Data Valid Data tCLZ tOFF tCLZ tOFF tCLZ tOFF tRHCP OE VIH VIL tOEA tOEA tOEA tOEZ tOEZ tOEZ

¡ Semiconductor MSM512100/L Fast Page Mode Read Modify Write Cycle RAS CAS Address WE DOUT VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL "H" or "L" DIN VIH VIL tRASP tCSH tPRWC tRCD tCAS tCP tCAS tRSH tRP tCRP tCAS tAR tASR tRAHtASC tCAH tASC tCAH tASC tCAH tRAL Row Column Column Column tRWD tRCS tCWD tCWL tCWD tCWL tCWD tCWL tAWD tAA tRAD tCAC tDS tAWD tCPA tAA tCAC tWP tAWD tCPA tAA tCAC tWP Valid Data Valid Data Valid Data tRAC tCLZ tDH tCLZ tDH tCLZ tDH Valid Data Valid Data Valid Data tCP tRCS tRCS tRHCP tCPWD tCPWD tRWL OE VIH VIL tOEA tOEA tOEA tWP tDS tDS tOED tOED tOED tOEZ tOEZ tOEZ

¡ Semiconductor MSM512100/L RAS-Only Refresh Cycle CAS before RAS Refresh Cycle VIH VIL RAS CAS VIH VIL tCRP tRP tRAS DOUT "H" or "L" VOH VOL tRPC Row VIH VIL Open Address tASR tRAH tRC Note: WE, OE = "H" or "L" tOFF VIH VIL RAS CAS VIH VIL tRP tRAS DOUT "H" or "L" VOH VOL tRPC VIH VIL Open WE tRC tWRH tWRP tRPC tWRP tCP tCSR tCHR tOFF Note: OE, Address = "H" or "L"

¡ Semiconductor MSM512100/L Hidden Refresh Read Cycle Hidden Refresh Write Cycle tASR Row Column VIH VIL RAS Address CAS VIH VIL VIH VIL tCRP tRC tASC tRP tRAS tRCD tRSH tRAD tCAH tRAH tAR tRAL tCHR tRAS tWRH tWRP WE DIN VIH VIL VIH VIL DOUT "H" or "L" VOH VOL Valid Data tDS tDH tRWL tWP tDHR tWCH tWCS tWCR Open OE VIH VIL tASR Row Column VIH VIL RAS Address WE CAS VIH VIL VIH VIL VIH VIL tCRP tRC tASC tRP tRAS tRCD tRSH tRAD tCAH tRAH tAR tRAL DOUT "H" or "L" VOH VOL tRRH tRCS Valid Data tRAC tAA tOFF tCLZ tCHR tRAS tWRH tWRP tCAC OE VIH VIL tROH tOEA tOEZ

¡ Semiconductor MSM512100/L Test Mode Initiate Cycle VIH VIL RAS CAS VIH VIL tRAS DOUT "H" or "L" VOH VOL VIH VIL Open WE tRC tWTH tRPC tWTS tCP tCSR tCHR tOFF Note: OE, Address, DIN = "H" or "L" tRP

¡ Semiconductor MSM512100/L (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Mirror finish