MSM5117805D

MSM5117805D OKI | Alldatasheet

Document overview

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Technical content

2,097,152-Word ´´´´ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

DESCRIPTION

The MSM5117805D is a 2,097,152-word ´ 8-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM5117805D achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117805D is available in a 28-pin plastic SOJ, 28-pin plastic TSOP.

FEATURES

• 2,097,152-word ´ 8-bit configuration
• Single 5V power supply, ±10% tolerance
• Input : TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 2048 cycles/32 ms
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Package options: 28-pin 400mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM5117805D-xxJS) 28-pin 400mil plastic TSOP (TSOPII28-P-400-1.27-K) (Product : MSM5117805D-xxTS-K) (TSOPII28-P-400-1.27-L) (Product : MSM5117805D-xxTS-L) xx : indicates speed rank. PRODUCT FAMILY Access Time (Max.) Power Dissipation Family tRAC tAA tCAC tOEA Cycle Time (Min.) Operating (Max.) Standby (Max.) MSM5117805D-50 50ns 25ns 13ns 13ns 84ns 550mW MSM5117805D-60 60ns 30ns 15ns 15ns 104ns 495mW MSM5117805D-70 70ns 35ns 20ns 20ns 124ns 440mW 5.5mW This version:Apr.1999

PIN CONFIGRATION (TOP VIEW) Pin Name Function A0 – A9, A10R Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 – DQ8 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (5V) VSS Ground (0V) NC No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 28-Pin Plastic SOJ 28-Pin Plastic TSOP (L Type) 28-Pin Plastic TSOP (K Type) 27DQ1 DQ2 V CC VCC VSS VSS DQ6 A10R WE RAS NC DQ3 OE DQ8 DQ7 CAS DQ4 DQ5 281 27DQ1 DQ2 V CC VCC VSS VSS DQ6 A10R WE RAS NC DQ3 OE DQ8 DQ7 CAS DQ4 DQ5 28 1 DQ1 DQ2 V CC VCC VSS VSS DQ8 DQ7 WE RAS NC A10R CAS OE DQ4 DQ325 DQ6 DQ5

A0 – A9 Timing Generator Column Address Buffers Internal Address Counter Row Address Buffers Refresh Control Clock Column Decoders Sense Amplifiers Memory Cells Word Drivers Row Deco- ders I/O Selector Input Buffers Output Buffers DQ1 – DQ8 OEWERAS CAS VCC VSS On Chip VBB Generator I/O Controller On Chip IVCC Generator A10R 1

ELECTRICAL CHARACTERISTICS

Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to VCC + 0.5 V Voltage VCC supply Relative to VSS VCC 0.5 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg -55 to 150 °C *: Ta = 25°C Recommended Operating Conditions (Ta = 0°C to 70°C) Parameter Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V Power Supply Voltage VSS 000 V Input High Voltage VIH 2.4 ¾ VCC + 0.5*1 V Input Low Voltage VIL -0.5*2 ¾ 0.8 V Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). Capacitance (VCC = 5V ± 10%, Ta = 25°C, f=1MHz) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 – A9, A10R) C IN1 ¾ 5p F Input Capacitance (RAS, CAS, WE, OE) C IN2 ¾ 7p F Output Capacitance (DQ1 – DQ8) C I/O ¾ 7p F

(VCC = 5V ± 10%, Ta = 0°C to 70°C) MSM5117805 D-50 MSM5117805 D-60 MSM5117805 D-70Parameter Symbol Condition Min. Max Min. Max Min. Max Unit Note Output High VoltageVOH IOH = -5.0mA 2.4 V CC 2.4 V CC 2.4 V CC V Output Low Voltage VOL IOL = 4.2mA 00 . 400 . 400 . 4 V Input Leakage Current ILI 0V £ VI £ 6.5V ; All other pins not under test = 0V -10 10 -10 10 -10 10 mA Output Leakage Current ILO DQ disable 0V £ VO £ VCC -10 10 -10 10 -10 10 mA Average Power Supply Current (Operating) ICC1 RAS, CAS cycling, tRC = Min. ¾ 100 ¾ 90 ¾ 80 mA 1,2 RAS, CAS = VIH ¾ 2 ¾ 2 ¾ 2Power Supply Current (Standby) ICC2 RAS, CAS ³ VCC – 0.2V ¾ 1 ¾ 1 ¾ 1 mA 1 Average Power Supply Current (RAS-only Refresh) ICC3 RAS cycling, CAS = VIH, tRC = Min. ¾ 100 ¾ 90 ¾ 80 mA 1,2 Power Supply Current (Standby) ICC5 RAS = VIH, CAS = VIL, DQ = enable ¾ 5 ¾ 5 ¾ 5m A 1 Average Power Supply Current (CAS before RAS Refresh) ICC6 RAS = cycling, CAS before RAS ¾ 100 ¾ 90 ¾ 80 mA 1,2 Average Power Supply Current (Fast Page Mode) ICC7 RAS = VIL, CAS cycling, tPC = Min. ¾ 100 ¾ 90 ¾ 80 mA 1,3 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH.

AC Characteristic (1/2) (VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12 MSM5117805 D-50 MSM5117805 D-60 MSM5117805 D-70Parameter Symbol Unit Note Random Read or Write Cycle TimetRC 84 ¾ 104 ¾ 124 ¾ ns Read Modify Write Cycle Time tRWC 110 ¾ 135 ¾ 160 ¾ ns Fast Page Mode Cycle Time tHPC 20 ¾ 25 ¾ 30 ¾ ns Fast Page Mode Read Modify Write Cycle Time tHPRWC 58 ¾ 68 ¾ 78 ¾ ns Access Time from RAS tRAC ¾ 50 ¾ 60 ¾ 70 ns 4,5,6 Access Time from CAS tCAC ¾ 13 ¾ 15 ¾ 20 ns 4,5 Access Time from Column AddresstAA ¾ 25 ¾ 30 ¾ 35 ns 4,6 Access Time from CAS Precharge tCPA ¾ 30 ¾ 35 ¾ 40 ns 4 Access Time from OE tOEA ¾ 13 ¾ 15 ¾ 20 ns 4 Output Low Impedance Time from CAS tCLZ 0 ¾ 0 ¾ 0 ¾ ns 4 Data Output Hold After CAS Low tDOH 5 ¾ 5 ¾ 5 ¾ ns CAS to Data Output Buffer Turn-off Delay Time tCEZ 01 301 502 0 n s 7 , 8 RAS to Data Output Buffer Turn-off Delay Time tREZ 01 301 502 0 n s 7 , 8 OE to Data Output Buffer Turn-off Delay Time tOEZ 01 301 502 0 n s 7 WE to Data Output Buffer Turn-off Delay Time tWEZ 01 301 502 0 n s 7 Transition Time tT 15 015 015 0 n s 3 Refresh Period tREF ¾ 32 ¾ 32 ¾ 32 ms RAS Precharge Time tRP 30 ¾ 40 ¾ 50 ¾ ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode)tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH 7 ¾ 10 ¾ 13 ¾ ns RAS Hold Time referenced to OE tROH 7 ¾ 10 ¾ 13 ¾ ns CAS Precharge Time (Fast Page Mode) tCP 7 ¾ 10 ¾ 10 ¾ ns CAS Pulse Width tCAS 7 10,000 10 10,000 13 10,000 ns CAS Hold Time tCSH 35 ¾ 40 ¾ 45 ¾ ns CAS to RAS Precharge Time tCRP 5 ¾ 5 ¾ 5 ¾ ns RAS Hold Time from CAS PrechargetRHCP 30 ¾ 35 ¾ 40 ¾ ns OE Hold Time from CAS (DQ Disable)tCHO 5 ¾ 5 ¾ 5 ¾ ns RAS to CAS Delay Time tRCD 11 37 14 45 14 50 ns 5 RAS to Column Address Delay TimetRAD 9 2 51 23 01 23 5 n s 6

AC Characteristic (2/2) (VCC = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12 MSM5117805 D-50 MSM5117805 D-60 MSM5117805 D-70 Note Parameter Symbol Unit Row Address Set-up Time tASR 0 ¾ 0 ¾ 0 ¾ ns Row Address Hold Time tRAH 7 ¾ 10 ¾ 10 ¾ ns Column Address Set-up Time tASC 0 ¾ 0 ¾ 0 ¾ ns Column Address Hold Time t CAH 7 ¾ 10 ¾ 13 ¾ ns Column Address to RAS Lead TimetRAL 25 ¾ 30 ¾ 35 ¾ ns Read Command Set-up Time tRCS 0 ¾ 0 ¾ 0 ¾ ns Read Command Hold Time tRCH 0 ¾ 0 ¾ 0 ¾ ns 9 Read Command Hold Time referenced to RAS tRRH 0 ¾ 0 ¾ 0 ¾ ns 9 Write Command Set-up Time tWCS 0 ¾ 0 ¾ 0 ¾ ns 10 Write Command Hold Time tWCH 7 ¾ 10 ¾ 13 ¾ ns Write Command Pulse Width tWP 7 ¾ 10 ¾ 10 ¾ ns WE Pulse Width (DQ Disable) tWPE 7 ¾ 10 ¾ 10 ¾ ns OE Command Hold Time tOEH 7 ¾ 10 ¾ 13 ¾ ns OE Precharge Time tOEP 7 ¾ 10 ¾ 10 ¾ ns OE Command Hold Time tOCH 7 ¾ 10 ¾ 10 ¾ ns Write Command to RAS Lead Time tRWL 7 ¾ 10 ¾ 13 ¾ ns Write Command to CAS Lead Time tCWL 7 ¾ 10 ¾ 13 ¾ ns Data-in Set-up Time tDS 0 ¾ 0 ¾ 0 ¾ ns 11 Data-in Hold Time tDH 7 ¾ 10 ¾ 13 ¾ ns 11 OE to Data-in Delay Time tOED 13 ¾ 15 ¾ 20 ¾ ns CAS to WE Delay Time tCWD 30 ¾ 34 ¾ 44 ¾ ns 10 Column Address to WE Delay TimetAWD 42 ¾ 49 ¾ 59 ¾ ns 10 RAS to WE Delay Time tRWD 67 ¾ 79 ¾ 94 ¾ ns 10 CAS Precharge WE Delay Time tCPWD 47 ¾ 54 ¾ 64 ¾ ns 10 CAS Active Delay Time from RAS Precharge tRPC 5 ¾ 5 ¾ 5 ¾ ns RAS to CAS Set-up Time (CAS before RAS) tCSR 5 ¾ 5 ¾ 5 ¾ ns RAS to CAS Hold Time (CAS before RAS) tCHR 10 ¾ 10 ¾ 10 ¾ ns WE to RAS Precharge Time (CAS before RAS) tWRP 10 ¾ 10 ¾ 10 ¾ ns WE Hold Time from RAS (CAS before RAS) tWRH 10 ¾ 10 ¾ 10 ¾ ns RAS to WE Set-up Time (Test Mode)tWTS 10 ¾ 10 ¾ 10 ¾ ns RAS to WE Hold Time (Test Mode)tWTH 10 ¾ 10 ¾ 10 ¾ ns

Notes: 1. A start-up delay of 200ms is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume t T = 2ns. 3. V IH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF. 5. Operation within the t RCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC . 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA . 7. t CEZ (Max), tREZ (Max), tWEZ (Max), tOEZ (Max) define the time at which the output achived the open circuit condition and are not referenced to output voltage levels. 8. t CEZ and tREZ must be satisfied for open circuit condition. 9. t RCH or tRRH must be satisfied for a read cycle. 10. tWCS , tCWD , tRWD , tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ³ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ³ tCWD (Min.), tRWD ³ tRWD (Min.), tAWD ³ tAWD (Min.) and tCPWD ³ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.

• Read Cycle
• Write Cycle (Early Write) tRAS tCEZ tCLZ tCAC tAOE tASC tRRH tRAHtASR tRAD tRAL tCRP tCAH tCRP tRCD tRC tRP tCSH tRSH tCAS tRAC tAA tRCS tROH tRCH tREZ tOEZ Row Column Valid Data-outOpen RAS VIH VIL CAS VIH VIL AddressVIH VIL WE VIH VIL OE VIH VIL DQ VOH VOL “H” or “L” tWCS tWCH tCWL tASR tRAH tASC tCRP tRP tRC tRAS tDH tRWL tCSH tCRP tRCD tRSH tCAS tCAH tRAD tRAL tDS tWP Valid Data-in Row Column RAS VIH VIL CAS VIH VIL AddressVIH VIL WE VIH VIL OE VIH VIL DQ VIH VIL “H” or “L” Open

• Read Modify Write Cycle tDH tDStOEZ tCLZ tOED tAA tOEH tRWD tCWD tCWL tRWLtCAH tASCtASR tRAH tRAD tCRP tRCD tRSH tCAS tCRP tCAC tCSH tRAC tOEA tRCS tAWD tWP tRWC tRAS tRP Valid Data-out Row Column RAS VIH VIL CAS VIH VIL AddressVIH VIL WE VIH VIL OE VIH VIL DQ VI/OH VI/OL “H” or “L” Valid Data-in

• Fast Page Mode Read Cycle (Part-1)
• Fast Page Mode Read Cycle (Part-2) tAA tOEP tCHO tCAC tOEP tCAC tCPA tAA tOEA tAA tRAC tRRHtOCH tCAHtASCtRAH tRAD tRCS tASR tASC tCAH tCP tCAS tHPC tRASP tCAS tCPtCSHtCRP tCLZ tCAH tOEA tOEA tOEZtCAC tASC tRP tRHCP tCAS tDOH tOEZ tREZ tRCD Valid Data-out Valid * Data-out Valid * Data-out Valid Data-out RAS VIH VIL CAS VIH VIL AddressVIH VIL WE VIH VIL OE VIH VIL DQ VOH VOL Row Column Column Column tCEZ tCAC tDOHtCAC tCPA tRCH tRCS tOEA tRAC tAA tRCS tCRP tASR tCAHtASCtRAH tRAD tASC tCP tASCtCAH tCAS tCP tCAS tRHCP tCSH tHPC tCLZ tCAH tAA tWEZtCAC tCAS tRPtRASP tWPE tRCD Valid * Data-out Valid * Data-out Valid * Data-out tAA RAS VIH VIL CAS VIH VIL AddressVIH VIL WE VIH VIL OE VIH VIL DQ VOH VOL Row Column Column Column

• Fast Page Mode Write Cycle (Early Write)
• Fast Page Mode Read Modify Write Cycle tDHtDStDHtDStDHtDS tWCHtWCStWCS tWCHtWCHtWCS tASC tCAHtASC tCAH tRAD tASR tASCtRAH tRCDtCRP tCAS tCAS tRSHtCP tCAS tRP tHPCtCSH tCAH tCP tHPC tRASP Valid * Data-in Valid * Data-in Valid * Data-in “H” or “L” RAS VIH VIL CAS VIH VIL AddressVIH VIL WE VIH VIL OE VIH VIL DQ VIH VIL Row Column Column Column tOED tDHtOEZ tOEH tCAC tOED tDHtOEZ tOEH tAWD tAWD tWPtDStAA tDS tCWDtRCS tRAH tCAH tASR tRAD tHPRWC tCPA tCWL tCAH tASC tCP tRWL tRWD tCWD tRCDtCRP tRASP tOEA tRCS tASC tWP tCPWD tRAC tCAC tCLZ tCLZ Column RAS VIH VIL CAS VIH VIL AddressVIH VIL WE VIH VIL OE VIH VIL DQ VI/OH VI/OL Row Column Valid * Data-in Valid * Data-out Valid * Data-in Valid * Data-out “H” or “L”

• RAS-Only Refresh Cycle
• CAS before RAS Refresh Cycle tCEZ tRPC tRP tRC tRAS tCHR tCSR tRP tCP tRPCRAS VIH VIL CAS VIH VIL VOH VOL DQ Open Note: WE, OE, Address = “H” or “L” tASR tRAH tCRP tRPC tRP tRAS tRC tCEZ RAS VIH VIL CAS VIH VIL VIH VIL Address VOH VOL DQ Row Open

• Hidden Refresh Read Cycle
• Hidden Refresh Write Cycle tDHtDS tWCHtWCS tRWL tRAL tRAD tCAH tRAH tASR tASC tRCDtCRP tRSH tRP tCHR tRP tRAS tRCtRC tRAS tWP RAS VIH VIL CAS VIH VIL AddressVIH VIL WE VIH VIL OE VIH VIL DQ VIH VIL Row Column Valid Data-in “H” or “L” tRAC tCLZ tOEZ tROH tOEA tCAC tRRH tAA tRAL tRCS tCAH tRAH tASR tASC tRAD tRP tRAS tRC tRP tCHR tRAS tRSHtRCDtCRP tRC tWRH tWRP Column RAS VIH VIL CAS VIH VIL AddressVIH VIL WE VIH VIL OE VIH VIL DQ VOH VOL Open Row Valid Data-out “H” or “L”

1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit and assembly designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. OKI assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to:traffic control, automotive, safety, aerospace, nuclear power control, and medical, including lift support and maintenance. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 1997 OKI ELECTRIC INDUSTRY CO.,LTD.