MSM5117400A OKI | Alldatasheet

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4,194,304-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION i The MSMS5117400A is a 4,194,304-word x 4-bit dynamic RAM fabricated in OKI's CMOS silicon gate | technology. The MSM5117400A achieves high integration, high-speed operation, and low-power | consumption due to quadruple polysilicon double metal CMOS. The MSM5117400A is available in | a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP. | FEATURES | * 4,194,304-word x 4-bit configuration * Single 5 V power supply, +10% tolerance *Input —: TTL compatible, low input capacitance * Output =: TTL compatible, 3-state * Refresh : 2048 cycles/32 ms * Fast page mode, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Multi-bit test mode capability * Package options: 26/24-Pin 300 mil plastic SO} (SOJ26/24-P-300) (Product : MSM5117400A-xxS]) 26/24-Pin 300 mil plastic TSOP (TSOP26/24-P-300-K) (Product : MSM5117400A-xxTS-K) (TSOP26/24-P-300-L) (Product : MSM5117400A-xTS-L) xx indicates speed rank. PRODUCT FAMILY ramiy [_-Aesess Time (Max) [Oyole Timo] Power Dissipation . [ tan | tcac| toca | (ln) [Operating (Max.)| Standby (Max. | MSM5117400A-60 151s 10 ns 660 mW ; MSM5117400A-70 __| 70 ns | 35 ns | 20ns 130 ns 605 mW 5.5 mW wsisir7400a-80 | 60s [40s | 200s] 20ns| 150ns [550 mw | 255

MSMS5117400A OKI Semiconductor | PIN CONFIGURATION (TOP VIEW) 7 ~ | Veo L1] [26] vss Vee[1] 0 [26] Vss Vs [26] © [1] Veo vaif2] O [es] 004 oar [2 [25] pas pas 5] pai : paz [2a] 03s Daa [24] pas_~—« a3 [24] e) paz | We [3] CAS «= WE [4] [23] CAS CAS We : RAS(5 | [22] OE = RAS[S] [22] OE OE [22| [5] RAS : nc(6] 21] ag nc(6| [21] AQ Ag[21] [6] Nc | Ato(8| As ato[a| [19] as as [19] [8] A10 Ao{a] [18] a7 Ao[a] Av Av [9] ao A1 {10} AG At AB AB [70] At a(t] [16] AS A2 [16] AS a5 [16] O A2 A3 [12] [15] A4 AS Ad Aa AS Voc [13] [14] Vss Voc [14] Vss Ves [14] 13] Voc 26/24-Pin Plastic SOU 26/24-Pin Plastic TSOP 26/24-Pin Plastic TSOP (K Type) ( Type) | Pin Name Function AQ- A10 Address Input RAS. Row Address Strobe CAS Column Address Strobe Dai - 004 Data Input/Data Output OE Output Enable WE Write Enable j Voc Power Supply (5 V) | Vss Ground (0 V) i NC No Connection ! Note: The same power supply voltage must be provided to every Vcc pin, and the same GND | voltage level must be provided to every Vsg pin. 256 1

OKI Semiconductor __ MSM5117400A BLOCK DIAGRAM —_ Timing RAS Generator Tm ming os a) Write Column 1K} Column Clock WE 11) Address 11) Decoders Generator tv Butters | | Output Buffers Internal . Retresh Sense UC) by - A0- A10 Address Control Clock | | Ampiifiers Selector cs Dat - Do4 Row 1" Adsress |) Row [ke 1 Memory Butters [| coders Drivers Cells Veo ~ On Chip Ves Generater Vss_ + i I 257 i

MSM5117400A OKI Semiconductor |

ELECTRICAL CHARACTERISTICS

Parameter Symbol Rating Unit Voltage on Any Pin Relative to Vss Vr o_o -1.0to 7.0 Vv Short Circuit Output Current log 50 mA Power Dissipation a Operating Temperature _____ 0070 °c Storage Temperature -55 to 150 °C *: Ta = 25°C i Recommended Operating Conditions (fa = 0°C to 70°C) Parameter Symbol |_n| tye | Man] Unit__ Power Supply Votage | vec [4s [so [ss _— | vss [oo InputHigh Voge | mw fd 88 v Input Low Voltage Mu | -10 ‘| 08 vo : i | Capacitance (Voc = 5 V #10%, Ta = 25°C, f= 1 MHz) —Faremeter [Symbol [ye MoT Ot Input Capacitance (AO - A10) Cw | 6 _ oF Output apetines (001-096) | Ge [=| 10 oF 258

OKI Semiconductor MSM5117400A H DC Characteristics (Vcc = 5 V £10%, Ta = 0°C to 70°C) : IMSMS5117400|MSMS51174001MSM51 17400 | Parameter 'symboll A-60 A-70 A-80 Note | Gai tne [fet fee {a [oa Pe [2a | vs |v , Output Low Voltage | Vo. [in =42mA | o | o4 | o | o4 | o | oa | v I | OVEVIS65V; Input Leakage Current | yy {All other pins not 10 | -10} 10 | -10); 10 | pa under test = 0 V : 00 disable 10 | BA ouput eatage Current | lo lov sve 88V ee ee | Average Power — Supply Current lect BAS. CIS cyl, 110 4.2 (Operating) Reem jp owt Suny 7. ene RAS, CA 1 Average Power RAS cycling, Supply Current loca | CAS = Vin, mAs 1,2 (RAS-only Refresh) tac = Min. RAS = Vin, Power Supply " Current (Standby) CAS = Vi, 1 00 = enable Average Power a Supply Current loce eas —} 120] — | 10 100 | mal 1,2 1 (CAS betore RAS Refresh) | | ‘ Average Power RAS = Vit, | Supply Current Icc7 | TAS cycling, — | 10 400 mA} 1,3 (Fast Page Mode) tec = Min. Notes: 1. Igc Max. is specified as Icc for output open condition. 2. Address can be changed once or less while RAS = Vi. 3. Address can be changed once or less while CAS = Vin. 259

MSM5117400A OKI Semiconductor AC Characteristics (1/2) Parameter A-60 A-70 A-80 Note Max. Random Read or Write Cycle Time a __ Read Modity Write Gycle Time [ tawe | 155 =} i= _ : Fast Page Mode Cycle Time 40 [45 | — | 50 | _ Fast Pane Mode Read Modity Write 85 [ 190 | = | 5 | = | Access Time from RAS _ ee 4,5,6 \\ ‘Access Time trom Column Address | taa_| | — | 40 4.6 Access Time from TAS Precharge pe f= ts tote 45 te 4 Access Time from OE | 15 | — | 20 | 20 | ns | 4 j Output Low Impedance Time tromtaS | taz | o | — | o | — | — [ns[ 4 | TAS to Data Output Butter Turn-off Delay Time | torr | 0 | 15 | 0 | 20 | 0 | 20 | ns | 7 : ‘GE to Data Output Butfer Turn-off Delay Time Lee} os | fo [of | os] 7 Transition Time [tr [| 3 [50 | 50 [50 [ns | 3 Refresh Period _ bette te EH RAS Precharge Time He |e a so | — [asp RAS Pulse Width tras | 60 80 RAS Pulse Width (Fast Page Mode) [ tease | 60 [100,000] 70 fasacn|_0_frnsolo _ RAS Hold Time | tasu | 15 [| — | 20 | — [20 | — [ns RAS Hold Time referenced to OF M tron | 10 | — [ 10 | — [| 10 [ — [os | TAS Precharge Time (Fast Page Mode) top ot a tt tee ; TAS Pulse width teas 40,000] 20 [10.000] 20 [10,000] ns | CAS Hold Time i tesu | 60 | — [70 | — [oo | = Jos | CAS to RAS Precharge Time [tone | 10 ) | — | 10 | — [10 | t=+4 ’ TAS to RAS Precharge Time [tance | 35 | pete s Lo RAS to CAS Delay Time [treo | 20 | 2a | cs \\ RAS to Column Address Delay Time [tao | 15 | 30 | 15 | 35 | 15 | ns | 6 Row Address Set-up Time [tase | 0 _| ofS pa Row Address Hold Time | to; — | 15 | ] Column Address Set-up Time T tasc_| [—|[o | | — | ! Column Address Hold Time | tcan_| [ — [15 | | — | ns | Column Address Hold Time from RAS. we] elas | 60 | _ Column Address to RAS Lead Time He 2 a _ : Read Command Set-up Time tacs | 0 [— To | Read Command Hold Time pu o = to fap ofa om i Read Command Hold Time referenced to RAS. [tan | o | — [To | — | —_| ns 8 j 260 :

OKI semiconductor MSM 1174008 AC Characteristics (2/2) (Wee = 5 V 210%, Ta = 0°C to 70°C) Note 1, 2,3, 11, 12 MSM5117400|MSM5117400|MSM5117400| Write Command Set-up Time [wes{ o | — [ o |—J[o | [as] Write Command Hold Time —__| twee | [io | — | is | = 45 |= a Write Command Hold Time from RAS | twa | 45 | — | 55 | 60 ns | i Write Command Pulse Width | twe | 10 | — | 10 | — | 10 [ns | : OE Command Hold Time a Write Command to RAS Lead Time 15 [20 | — {20 | Write Command to CAS Lead Time [tom | 15 | — [2 | — [2 | — [ns | | Data-in Set-up Time [ws {o | — | o |=] o | [ns | 10 Data-in Hold Time [tow | 15 | — | 15 _| is | =| as | 10 : Data-in Hold Time trom RAS. [town | 50 | — | 55 | 60 | — | ns | ' ‘OE to Data-in Delay Time pte B=] eS 20 _ TAS to WE Delay Time [tow | 40 | — | [= | 9 Column Address to WE Delay Time [ tawo | 55 | — | 9 | AS to WE Delay Time He st a = i CAS Precharge WE Delay Time [tcpwo| 60 | — | vo | — | 75 | [ns | 9 i TAS Active Delay Time from RAS Precharge pee fe fatwa fe | | BAS to CAS Set-up Time (CAS before RAS)| tose | | 10 | — | 10 | FAS to CAS Hold Time (CAS before RAS) | town | 20 | — | 20 | — | 20 | — | ns | CAS Precharge Time (Refresh Counter Test) Ftcor | 40 | — | 40 | — | @ | — | __ ' WE to RAS Precharge Time (CAS before RAS)| [twae| 10 | —~ | 10 | — | - | ‘WE Hold Time trom RAS (CAS before RAS)| twan | 10 | — | 10 | — | Pas | | BAS to WE Set-up Time (Test Mode) | twrs| 10 | — | 10 | — | ms | : BAS to WE Hold Time (Test Mode] [twa | 20 [ — [20 | as i 261

MSM5117400A OKI Semiconductor Notes: 1. A start-up delay of 2001s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh orCAS before RAS refresh) before properdevice operation is achieved. 2. The AC characteristics assume ty = 5 ns. 3. Vin (Min. and Vj, (Max.) are reference levels for measuring input timing signals. Transition times (tr) are measured between Vjy and Vj. ! 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. } 5. Operation within the tacp (Max.) limit ensures that trac (Max.) can be met. Hl trcp (Max.) is specified as a reference point only. If tycp is greater than the specified i trcp (Max.) limit, access time is controlled by tcac. 6. Operation within the trap (Max.) limit ensures that trac (Max.) can be met. trap (Max. is specified as a reference point only. If trap is greater than the specified trap (Max.) limit, access time is controlled by ta. | 7. torr (Max.) and tozz (Max.) define the time at which the output achieves the open i circuit condition and are not referenced to output voltage levels. | 8. tack or taRH must be satisfied for a read cycle. 9. twos, twp, twp, tawpand tcpwpare not restrictive operating parameters. They are : included in the data sheet as electrical characteristics only. If twcs 2 twcs (Min.), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tewp2 tcwp (Min.) , tawp2 trwp (Min.), tawp2 tawD. ' (Min.) and tcpwo2 tcpwo (Min), the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 10. These parametersare referenced toCAS leading edgein an early writecycle,andtoWE leading edge in an OE control write cycle or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This modeis latched and remains in effect until the exit cycle is generated. Ina test mode CAO,CA1 and CA 10 are not used and each DQ pin now accesses 8-bit locations. Since all4 DQ pins are used, a total of 32 data bits can be written in parallel into the memory array. Ina read cycle, if 8 data bits are equal the DQ pin will indicate a high level. If the 8 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS- only refresh cycle or a CAS before RAS refresh cycle. 12. Ina test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. | See ADDENDUM G for AC Timing Waveforms | 262