MSM511664CL-XXTS-K

MSM511664C OKI | Alldatasheet

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Technical content

¡ Semiconductor MSM511664C/CL

DESCRIPTION

The MSM511664C/CL is a 65,536-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM511664C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM511664C/CL is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP. The MSM511664CL (the low-power version) is specially designed for lower-power applications.

FEATURES

• 65,536-word ¥ 16-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input : TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 256 cycles/4 ms, 256 cycles/32 ms (L-version)
• Byte write and fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM511664C/CL-xxJS) 44/40-pin 400 mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM511664C/CL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY ¡ Semiconductor MSM511664C/CL 65,536-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE (BYTE WRITE) MSM511664C/CL-70 70 ns 120 ns 495 mW Family Access Time (Max.) Cycle Time (Min.) Standby (Max.) Power Dissipation tRAC 40 ns tAA 25 ns tCAC 25 ns tOEA Operating (Max.) MSM511664C/CL-80 80 ns 135 ns 440 mW 45 ns 30 ns 30 ns 5.5 mW/ 1.1 mW (L-version) MSM511664C/CL-60 60 ns 110 ns 550 mW 30 ns 20 ns 20 ns E2G0014-17-41 This version: Jan. 1998 Previous version: May 1997

¡ Semiconductor MSM511664C/CL PIN CONFIGURATION (TOP VIEW) VCC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 NC VCC UWE LWE RAS VCC VSS DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 NC VSS CAS OE NC NC NC VSS VCC 40-Pin Plastic SOJ 44/40-Pin Plastic TSOP (K Type) VCC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 NC VCC UWE LWE RAS

44 VSS

23 VSS

43 DQ16

42 DQ15

41 DQ14

40 DQ13

39 DQ12

38 DQ11

37 DQ10

36 DQ9

32 VSS

31 CAS

Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. Pin Name Function A0 - A7 Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ16 Data Input/Data Output OE Output Enable LWE Lower Byte Write Enable VCC Power Supply (5 V) NC No Connection UWE Upper Byte Write Enable VSS Ground (0 V)

¡ Semiconductor MSM511664C/CL BLOCK DIAGRAM Timing Generator RAS CAS Timing Generator Internal Address Counter Row Address Buffers A0 - A7 VCC VSS On Chip VBB Generator Row De- coders Word Drivers Memory Cells Refresh Control Clock Sense Amplifiers Column Decoders Write Clock Generator I/O Selector Output Buffers LWE OE DQ1 - DQ16 Input Buffers Column Address Buffers UWE FUNCTION TABLE Function Mode RAS H L Input Pin CAS H UWE LWE H L H OE L H L L L L L L H H L H Word Read Refresh Standby Lower Byte Write DQ Pin DQ1 - DQ8 High-Z High-Z DIN DQ9 - DQ16 High-Z High-Z DOUT Don't Care DOUT Don't Care DIN Upper Byte Write L L L L H DIN DIN Word Write H L L H H High-Z High-Z

¡ Semiconductor MSM511664C/CL

ELECTRICAL CHARACTERISTICS

Recommended Operating Conditions Capacitance *: Ta = 25°C Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature VT Symbol IOS PD* Topr Tstg –1.0 to 7.0 0 to 70 –55 to 150 Rating mA W Parameter V Unit Power Supply Voltage Input High Voltage Input Low Voltage VCC Symbol VSS VIH VIL 5.0 Typ. Parameter 4.5 2.4 –1.0 Min. 5.5 6.5 0.8 Max. (Ta = 0°C to 70°C) V Unit V V V Input Capacitance (A0 - A7) Input Capacitance Output Capacitance (DQ1 - DQ16) CIN1 Symbol CIN2 CI/O Max. pF Unit pF pF Parameter (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Typ. (RAS, CAS, UWE, LWE, OE)

¡ Semiconductor MSM511664C/CL DC Characteristics Parameter Symbol Condition MSM511664 C/CL-70 MSM511664 C/CL-80 MSM511664 C/CL-60 (VCC = 5 V ±10%, Ta = 0°C to 70°C) IOH = –2.5 mA Output High Voltage IOL = 2.1 mA Output Low Voltage 0 V £ VI £ 6.5 V; All other pins not Input Leakage Current under test = 0 V DQ disable Output Leakage Current 0 V £ VO £ 5.5 V RAS, CAS cycling, Average Power tRC = Min. Supply Current (Operating) RAS, CAS = VIH Power Supply RAS, CAS Current (Standby) RAS cycling, Average Power CAS = VIH, Supply Current tRC = Min. (RAS-only Refresh) RAS = VIH, Power Supply CAS = VIL, Current (Standby) DQ = enable Average Power CAS before RAS Supply Current (CAS before RAS Refresh) RAS = VIL, Average Power CAS cycling, Supply Current tPC = Min. (Fast Page Mode) tRC = 125 ms, Average Power VOH VOL ILI ILO ICC1 ICC2 ICC3 ICC5 ICC6 ICC7 ICC10 CAS before RAS, Supply Current tRAS £ 1 ms (Battery Backup) ≥ VCC –0.2 V Min. 2.4 –10 –10 Max. VCC 0.4 300 200 Min. 2.4 –10 –10 Max. VCC 0.4 300 200 Min. 2.4 –10 –10 Max. VCC 0.4 100 100 100 300 200 Unit V V mA mA mA mA mA mA mA mA mA mA Note 1, 2 1, 2 1, 2 1, 3 1, 4, 1, 5 RAS cycling, Notes : ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. L-version.

¡ Semiconductor MSM511664C/CL AC Characteristics (1/2) Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge CAS to Data Output Buffer Turn-off Delay Time Transition Time RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time CAS Pulse Width CAS Hold Time RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Access Time from OE OE to Data Output Buffer Turn-off Delay Time Refresh Period RAS Hold Time referenced to OE Unit RAS Hold Time from CAS Precharge Note Output Low Impedance Time from CAS CAS Precharge Time (Fast Page Mode) Refresh Period (L-version) Symbol tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOFF tT tRP tRAS tRASP tRSH tCAS tCSH tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tOEA tOEZ tREF tROH tRHCP tCLZ tCP tAR tREF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns 4, 5, 6 4, 5 4, 6 MSM511664 C/CL-60 Min. 110 155 Max. 10,000 100,000 10,000 ns MSM511664 C/CL-70 MSM511664 C/CL-80 Min. 135 185 100 Max. 10,000 100,000 10,000 Min. 120 170 Max. 10,000 100,000 10,000

¡ Semiconductor MSM511664C/CL AC Characteristics (2/2) Write Command Pulse Width Write Command to CAS Lead Time Write Command to RAS Lead Time Data-in Set-up Time Data-in Hold Time from RAS CAS to WE Delay Time RAS to WE Delay Time Column Address to WE Delay Time RAS to CAS Hold Time (CAS before RAS) CAS Active Delay Time from RAS Precharge Data-in Hold Time Write Command Hold Time Write Command Hold Time from RAS OE Command Hold Time OE to Data-in Delay Time (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Write Command Set-up Time Parameter Unit Note RAS to CAS Set-up Time (CAS before RAS) CAS Precharge WE Delay Time Symbol tWP tCWL tRWL tDS tDHR tCWD tRWD tAWD tCHR tRPC tDH tWCH tWCR tOEH tOED tWCS tCSR tCPWD MSM511664 C/CL-70 MSM511664 C/CL-80 MSM511664 C/CL-60 Min. Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. 105 Max. Min. Max. ns

¡ Semiconductor MSM511664C/CL Notes: 1. A start-up delay of 100 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle.

¡ Semiconductor MSM511664C/CL TIMING WAVEFORM Read Cycle "H" or "L" RAS CAS VIH VIL VIH VIL DQ VIH VIL Address VIH VIL WE VIH VIL OE VIH VIL tRC tRAS tRP tAR tCRP tRCD tCSH tRSH tCRP tCAS tRAD tRAH tASR tASC tCAH Row Column tWCS tWCH tWCR tDHR tDS tDH Valid Data-in tWP tRAL Open tCWL tRWL "H" or "L" RAS CAS VIH VIL VIH VIL DQ VOH VOL Address VIH VIL WE VIH VIL OE VIH VIL tRC tRAS tRP tAR tCRP tCSH tCRP tRCD tRSH tCAS tRAD tASR tRAH tASC tCAH tRAL Row Column tRCS tRRH tRCH tAA tROH tOEA tCAC tRAC tOEZ tOFF Open tCLZ Valid Data-out Write Cycle (Early Write) E2G0092-17-41E

¡ Semiconductor MSM511664C/CL "H" or "L" RAS CAS VIH VIL VIH VIL DQ VI/OH VI/OL Address VIH VIL WE VIH VIL OE VIH VIL tRWC tRAS tRP tAR tCRP tCSH tRCD tCRP tRSH tCAS tASR tRAH tASC tCAH Row Column tCWD tCWL tRWD tRWL tWP tAA tAWD tOEA tOED tCAC tRAC tOEZ tDS tDH tCLZ Valid Data-out Valid Data-in tRAD tRCS tOEH Read Modify Write Cycle

¡ Semiconductor MSM511664C/CL Fast Page Mode Read Cycle Fast Page Mode Write Cycle (Early Write) "H" or "L" RAS CAS VIH VIL VIH VIL DQ VIH VIL Address VIL WE VIH VIL tRASP tRP tAR tCRP tRCD tCAS tCP tCAS tRSH tCRP tCAS tASR tRAH tCAH tCSH tASC tCAH tASC tCAH tRAL Row Column Column Column tRAD tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH tWP tDS tDH tDS tDH tDS tDH Valid Data-in Valid Data-in Valid Data-in tDHR Note: OE = "H" or "L" VIH tASC tPC tRHCP tCP tCWL tCWL tRWL tCWL tWCR "H" or "L" RAS CAS VIH VIL VIH VIL DQ VOH VOL Address VIH VIL WE VIH VIL OE VIH VIL tRASP tRP tAR tCRP tRCD tPC tRSH tCRP tCAS tCAS tCP tCAS tRAD tASR tRAH tASC tCAH tCSH tASC tCAH tASC tCAH tRAL Row Column Column Column tRCS tRCH tRCS tRCS tRCH tAA tOEA tAA tAA tRRH tOEA tOEA tCAC tRAC tOFF tOEZ tCAC tCLZ tOFF tOEZ tCAC tCLZ tOEZ tOFF tCLZ Valid Data-out Valid Data-out Valid Data-out tRHCP tCP tRCH tCPA tCPA

¡ Semiconductor MSM511664C/CL RAS CAS VIH VIL VIH VIL Address VIH VIL tRC tRAS tRP tCRP tRPC tASR tRAH Row "H" or "L" DQ VOH VOL Note: WE, OE = "H" or "L" Open tOFF Fast Page Mode Read Modify Write Cycle tWP RAS CAS Address OE VIH VIL VIH VIL VIH VIL VIH VIL WE VIH VIL DQ VI/OH VI/OL tRASP tAR tRP tCSH tPRWC tRSH tRCD tCAS tCP tCAS tCP tCAS tCRP tRAD tRAH tASR tASC tCAH tASC tCAH tASC tCAH tRAL Row Column Column Column tRWD tRCS tCWD tCWL tCWD tCWL tCWD tRWL tCWL tAWD tAWD tAWD tOEA tWP tOEA tWP tOEA tAA tOED tCAC tDS tDH tCAC tAA tRAC tDS tDH tCPA tOED tCAC tAA tDS tDH tCLZ tCLZ tCLZ Out In Out Out In In tROH tOEZ tOEZ tCPA tOED tRCS tRCS tCPWD tCPWD "H" or "L" tOEZ RAS-Only Refresh Cycle

¡ Semiconductor MSM511664C/CL RAS CAS VIH VIL VIH VIL Column Row DQ VOH VOL WE VIH VIL OE VIH VIL Address VIH VIL tRC tRC tRAS tRP tRAS tRP tAR tCRP tRCD tRSH tCHR tRAD tASR tASC tRAH tCAH tRCS tRAL tRRH tAA tROH tOEA tCAC tCLZ tRAC tOFF tOEZ Valid Data-out "H" or "L" CAS before RAS Refresh Cycle Hidden Refresh Read Cycle RAS CAS VIH VIL VIH VIL tCHR Note: WE, OE, Address = "H" or "L" DQ VOH VOL tRC tRP tRAS tRP tRPC tCP tCSR tRPC tOFF Open "H" or "L"

¡ Semiconductor MSM511664C/CL Hidden Refresh Write Cycle RAS CAS VIH VIL VIH VIL DQ VIH VIL WE VIH VIL OE VIH VIL Address VIH VIL tRC tRC tRAS tRP tRAS tRP tAR tCRP tRCD tRSH tCHR tRAD tASC tASR tRAH tCAH tRAL Row Column tWCS tWCH tWP tDS tDH Valid Data-in tDHR "H" or "L" tWCR

¡ Semiconductor MSM511664C/CL Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (Unit : mm) PACKAGE DIMENSIONS SOJ40-P-400-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP. Mirror finish

¡ Semiconductor MSM511664C/CL Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (Unit : mm) Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP. TSOPII44/40-P-400-0.80-K Mirror finish