MSM5116160F OKI | Alldatasheet

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Technical content

This version: August. 2002 Previous version : Sep..2001 MSM5116160F 1,048,576-Word × 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE

DESCRIPTION

The MSM5116160F is a 1,048,576-word × 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM5116160F achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5116160F is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP.

FEATURES

  • 1,048,576-word × 16-bit configuration
  • Single 5V power supply, ±10% tolerance
  • Input : TTL compatible, low input capacitance
  • Output : TTL compatible, 3-state
  • Refresh : 4096 cycles/64ms
  • Fast page mode, read modify write capability
  • CAS before RAS refresh, hidden refresh, RAS-only refresh capability
  • Packages 42-pin 400mil plastic SOJ (SOJ42-P-400-1.27) (Product : MSM5116160F-xxJS) 50/44-pin 400mil plastic TSOP (TSOPII50/44-P-400-0.80-K) (Product : MSM5116160F-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Power Dissipation Family tRAC tAA tCAC tOEA Cycle Time (Min.) Operating (Max.) Standby (Max.) 50ns 25ns 13ns 13ns 90ns 495mW 60ns 30ns 15ns 15ns 110ns 468mW MSM5116160F 70ns 35ns 20ns 20ns 130ns 440mW 5.5mW

PIN CONFIGURATION (TOP VIEW) Pin Name Function A0–A7 A8R-A11R Address Input RAS Row Address Strobe LCAS Lower Byte Column Address Strobe UCAS Upper Byte Column Address Strobe DQ1–DQ16 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (5V) VSS Ground (0V) NC No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 42-Pin Plastic SOJ 50/44-Pin Plastic TSOP (K Type) DQ1 DQ2 DQ3 DQ4 VCC VCC VCC VSS VSS VSS DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 A9R A8R DQ5 DQ6 DQ7 DQ8 NC NC WE RAS A11R A10R NC LCAS UCAS OE DQ1 DQ2 DQ3 DQ4 VCC VCC VSS VSS VSS DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 A9R A8R A10R DQ5 DQ6 DQ7 DQ8 NC NC NC WE RAS A11R NC LCAS UCAS OE VCC NC

H High-Z High-Z Standby L H H High-Z High-Z Refresh L L H H L DOUT High-Z Lower Byte Read L H L H L High-Z DOUT Upper Byte Read L L L H L DOUT DOUT Word Read L L H L H DIN Don’t Care Lower Byte Write L H L L H Don’t Care DIN Upper Byte Write L L L L H DIN DIN Word Write L L L H H High-Z High-Z A0-A7 Timing Generator Column Address Buffers I/O Controller Internal Address Counter Row Address Buffers Refresh Control Clock I/O Controller Column Decoders Sense Amplifiers Memory Cells Word Drivers Row Deco- ders I/O Selector Input Buffers Input Buffers Output Buffers Output Buffers DQ1-DQ8 DQ9-DQ16 OE WE RAS LCAS UCAS VCC VSS On Chip VBB Generator On Chip IVCC Generator A8R-A11R

ELECTRICAL CHARACTERISTICS

Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to VCC+ 0.5 V Voltage VCC Supply relative to VSS VCC –0.5 to 7 V Short Circuit Output Current IOS mA Power Dissipation PD* W Operating Temperature Topr 0 to 70 Storage Temperature Tstg –55 to 150 *: Ta = 25°C RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70°C) Parameter Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V Power Supply Voltage VSS V Input High Voltage VIH 2.4 VCC + 0.5*1 V Input Low Voltage VIL − 0.5*2 0.8 V Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS − 2.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). PIN CAPACITANCE (Vcc = 5V ± 10%, Ta = 25°C, f = 1 MHz) Parameter Symbol Min. Max. Unit Input Capacitance (A0 – A7, A8 – A11R) CIN1 pF Input Capacitance (RAS, LCAS, UCAS, WE, OE) CIN2 pF Output Capacitance (DQ1 - DQ16) CI/O pF

(VCC = 5V ± 10%, Ta = 0 to 70°C) MSM5116160 F-50 MSM5116160 F-60 MSM5116160 F-70 Parameter Symbol Condition Min. Max. Min. Max. Min. Max. Unit Note Output High Voltage VOH IOH = −5.0mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2mA 0.4 0.4 0.4 V Input Leakage Current ILI 0V ≤ VI ≤ 6.5V; All other pins not under test = 0V − 10 − 10 − 10 µA Output Leakage Current ILO DQ disable 0V ≤ VO ≤ VCC − 10 − 10 − 10 µA Average Power Supply Current (Operating) ICC1 RAS, CAS cycling, tRC = Min. mA 1,2 RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC − 0.2V mA Average Power Supply Current (RAS-only Refresh) ICC3 RAS cycling, CAS = VIH, tRC = Min. mA 1,2 Power Supply Current (Standby) ICC5 RAS = VIH, CAS = VIL, DQ = enable mA Average Power Supply Current (CAS before RAS Refresh) ICC6 RAS = cycling, CAS before RAS mA 1,2 Average Power Supply Current (Fast Page Mode) ICC7 RAS = VIL, CAS cycling, tPC = Min. mA 1,3 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH.

AC CHARACTERISTICS (1/2) (VCC = 5V ± 10%, Ta = 0 to 70°C) Note1,2,3 MSM5116160 F-50 MSM5116160 F-60 MSM5116160 F-70 Parameter Symbol Min. Max. Min. Max. Min. Max. Unit Note Random Read or Write Cycle Time tRC 110 130 ns Read Modify Write Cycle Time tRWC 131 155 185 ns Fast Page Mode Cycle Time tPC ns Fast Page Mode Read Modify Write Cycle Time tPRWC 100 ns Access Time from RAS tRAC ns 4, 5, 6 Access Time from CAS tCAC ns 4, 5 Access Time from Column Address tAA ns 4, 6 Access Time from CAS Precharge tCPA ns 4, 12 Access Time from OE tOEA ns Output Low Impedance Time from CAS tCLZ ns CAS to Data Output Buffer Turn- off Delay Time tOFF ns OE to Data Output Buffer Turn-off Delay Time tOEZ ns Transition Time tT ns Refresh Period tREF ms RAS Precharge Time tRP ns RAS Pulse Width tRAS 10,000 10,000 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 100,000 100,000 100,000 ns RAS Hold Time tRSH ns RAS Hold Time referenced to OE tROH ns CAS Precharge Time (Fast Page Mode) tCP ns CAS Pulse Width tCAS 10,000 10,000 10,000 ns CAS Hold Time tCSH ns CAS to RAS Precharge Time tCRP ns RAS Hold Time from CAS Precharge tRHCP ns RAS to CAS Delay Time tRCD ns RAS to Column Address Delay Time tRAD ns Row Address Set-up Time tASR ns

AC CHARACTERISTICS (2/2) (VCC = 5V ± 10%, Ta = 0 to 70°C) Note1,2,3 MSM5116160 F-50 MSM5116160 F-60 MSM5116160 F-70 Parameter Symbol Min. Max. Min. Max. Min. Max. Unit Note Row Address Hold Time tRAH ns Column Address Set-up Time tASC ns Column Address Hold Time tCAH ns Column Address to RAS Lead Time tRAL ns Read Command Set-up Time tRCS ns Read Command Hold Time tRCH ns 8, 11 Read Command Hold Time referenced to RAS tRRH ns Write Command Set-up Time tWCS ns 9, 11 Write Command Hold Time tWCH ns Write Command Pulse Width tWP ns OE Command Hold Time tOEH ns Write Command to RAS Lead Time tRWL ns Write Command to CAS Lead Time tCWL ns Data-in Set-up Time tDS ns 10, 11 Data-in Hold Time tDH ns 10, 11 OE to Data-in Delay Time tOED ns CAS to WE Delay Time tCWD ns Column Address to WE Delay Time tAWD ns RAS to WE Delay Time tRWD 100 ns CAS Precharge WE Delay Time tCPWD ns CAS Active Delay Time from RAS Precharge tRPC ns RAS to CAS Set-up Time (CAS before RAS) tCSR ns RAS to CAS Hold Time (CAS before RAS) tCHR ns

Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. -50 is measured with a load circuit equivalent to 2 TTL load and 50pF, and -60/-70 is measured with a load circuit equivalent to 2 TTL load and 100pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 12. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 13. tCWL should be satisfied by both UCAS and LCAS. 14. tCP is determined by the time both UCAS and LCAS are high.

Write Cycle (Early Write) tOFF tCLZ tCAC tOEA tASC tRRH tRAH tASR tRAD tRAL tCRP tCAH tCRP tRCD tRC tRAS tRP tCSH tRSH tCAS tRAC tAA tRCS tROH tRCH tOEZ Row Column Valid Data-out Open RAS VIH VIL CAS VIH VIL Address VIH VIL WE VIH VIL OE VIH VIL DQ VOH VOL “H” or “L” tCRP tRP tRWL Valid Data-in tD tDS tWCS tWCH tCWL tASR tRAH tASC tRC tRAS Row tCSH tCRP tRCD tRSH tCAS Column tCAH tRAD tRAL tWP RAS VIH VIL CAS VIH VIL Address VIH VIL WE VIH VIL OE VIH VIL DQ VIH VIL “H” or “L” Open

“H” or “L”

Fast Page Mode Write Cycle (Early Write) tWP tCWL tWCH tASC tCP tPC tRASP Column tRAL tCRP tASC tCAH tCAH tCAS tRSH tCP tCAS tRP tRHPC Column tWP tWCH tDH tDS tDH tDS Valid * Data-in tWCS tWCS Valid * Data-in tCWL tCSH tRAD tASR tASC tRAH tRCD tCRP tCAS tCAH Row Column tWP tRWL tWCH tCWL tDH tDS tWCS Valid * Data-in “H” or “L” RAS VIH VIL CAS VIH VIL Address VIH VIL WE VIH VIL DQ VIH VIL Note: OE = “H” or “L” tPC tCAS tOEZ tCAC tOFF tCAC tCLZ tOEA tCSH tCAC tOEZ tRRH tRAC tOEA tRAL tASC tCAH tRCS tRCH tCPA tAA tAA tRCH tRCS tCAH tASC tRAH tRAD tRCS tASR tASC tCP tCAS tRSH tRASP tCAS tCP tRCD tCRP tCLZ tCAH Valid Data-out tCPA tRP RAS VIH VIL CAS VIH VIL Address VIH VIL WE VIH VIL OE VIH VIL DQ VOH VOL tRHCP Row Column Column Column “H” or “L” tCRP tRCH tAA tOEA tOFF tOEZ Valid Data-out tCLZ tOFF Valid Data-out

Fast Page Mode Read Modify Write Cycle RAS-only Refresh Cycle tDS tAA tDH tROH tOEA tWP tCPA tDS tOEZ tCPWD tWP tCWD tAWD tDH tAWD tAA tRAC tRCS tRCS tAA tCPA tOEA tPWD tCWD tASC tRAH tASR tRAD tCSH tCAS tRASP tCWL tRCD tCP tCAH tASC Row Column tRWL tCWL tRCS Column tCWL tCWD tRAL tCAH tCR tCP tCAS tCLZ tCAS tASC tOED tOEZ tOED tCAC tOED tDH tOEZ In tWP tDS Column tRP tRSH tCAH Out tCAC tPRWC tCAC tCLZ tCLZ tAWD tOEA In In Out Out tCPWD RAS VIH VIL CAS VIH VIL Address VIH VIL WE VIH VIL OE VIH VIL DQ VI/OH VI/OL “H” or “L” Note: In = Valid Data-in, Out = Valid Data-out tASR tRA tCRP tRPC tRP tRAS tRC tOFF Row RAS VIH VIL CAS VIH VIL VIH VIL Address VOH VOL DQ “H” or “L” Open Note: WE, OE = “H” or “L”

CAS before RAS Refresh Cycle Hidden Refresh Read Cycle RAS tOFF tRPC tRP tRC tRAS tCHR tCSR tRP tCP tRPC VIH VIL CAS VIH VIL VOH VOL DQ Open Note: WE, OE, Address = “H” or “L” “H” or “L” tCAC tCAH Column tRSH tRRH tRP tRAS tRP tCHR tOFF tOEZ tRAC tCLZ tROH tOEA tAA tRAL tRCS tRAH tASR tASC tRAD tRAS tRCD tCRP tRC Row tRC RAS VIH VIL CAS VIH VIL Address VIH VIL WE VIH VIL OE VIH VIL DQ VOH VOL Open Valid Data-out “H” or “L”

Hidden Refresh Write Cycle tRP tRAS tRC tRP tCHR tDS tDH tWCH tWP tWCS Column Row Valid Data-in tRAL tCAH tRA tASR tASC tRAD tRAS tRSH tRCD tCRP tRC RAS VIH VIL CAS VIH VIL Address VIH VIL WE VIH VIL OE VIH VIL DQ VIH VIL “H” or “L”

  1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.