MSM41256A

MSM41256A OKI | Alldatasheet

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Technical content

58E D MM G724240 COL2bSb 741) MMOKIY ® K I SEMICONDUCTOR GROUP OKI semiconductor T= 46-23 -1S MSM41256A 262,144-WORD x 1-BIT DYNAMIC RAM <PAGE MODE TYPE> GENERAL DESCRIPTION The Oki MSM41256A is a fully decoded, dynamic NMOS random access memory organized as 262,144-word x 1 bit. The design is optimized for high-speed, high-performance applications such as mainframe memory, buffer memory, peripheral storage and environments where low- power dissipation and compact layout are required. Multiplexed row and column address input permits MSM41 256A housing ina standard 16 pin DIP or 18pin PLCC. Pin-outs conform to the JEDEC approved pin out. Additionally, the MSM41256A, offers new functional enhancements that make it more versatile than previous dynamic RAMs. CAS-before-RAS refresh provides an on-chip refresh capability. The MSM41256A is fabricated using silicon gate NMOS and Oki’s advanced VLSI Polysilicon process. This process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum chip size. Dynamic circuitry, including the sense amplifiers, is employed in the design. Clock timing requirements are noncritical, and power supply tolerance is very wide. Allinputs and output are TTL compatible.

FEATURES

+ 262,144 x 1 RAM, 16 or 18 pin package _—_* Allinputs are TTL compatible, low-capacitive + Silicon-gate, double-poly NMOS, singletran- _ load sistor cell + Three-state TTL compatible output + Row access time: + Gated CAS 100 ns max (MSM41256A-10) + 256 refresh cycles/4ms 120 ns max (MSM41256A-12) + Common VO capability using Early Write 150 ns max (MSM41256A-15) operation + Cycle time: + Output unlatched at cycle end to allow ex- 200 ns min (MSM41256A-10) tended page boundary and two-dimensional 220 ns min (MSM41256A-12) chip select . 260 ns min (MSM41256A-15) + Read-Modify-Write and RAS-only refresh, + Low power: capability 330 mW active (MSM41256A-10) * On-chip latches for addresses and data-in 303 mW active (MSM41256A-12) * On-chip substrate bias generator for high 275 mW active (MSM41256A-15) performance 28 mW max standby + CAS-before-FAS refresh capability + Single +5V power supply, +10% tolerance * Page Mode capability

S8E D MM 6724240 0012687 688 MMOKIU PIN CONFIGURATION (TOP VIEW) To Vss —_ As 1 161 Vss Pi at ny cas On 2 151) CAS 211817 We Dy — We C3 141) Pout WE3 16D Dour Ras C]4 13[7) Act Rasg4 15B ast NCO5S 140 NC Act 15 1217) as ao 6 13B Ast av C6 WO Ae ag? wep Ae art]? 107) As* 89101 Voc C18 9D ar An AP AS * Refresh Address Pin Names. Function ‘AO ~ AB Address inputs RAS Row Address Strobe CAS Column Adress Strobe WE Write Enable DIN Data Input DouT Data Output Vcc Power Supply (+5V) Vss Ground (0V) NC No Connection FUNCTIONAL BLOCK DIAGRAM cae [generator] ers * enerator rite — ee nn CE Be We Butters Decoders enerator _ | | Address| Butfers Row! Mord! | Memory Data pe eer] | Celts Input Din ore Register Voc: Vss-——e On-chip Ve

S6E D MM 6724240 0012688 S14 MMOKIJ uMSM41256Aa ——————-_ 0 K I SEMICONDUCTOR GROUP ———

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (See Note) Rating [ Symbol [Condition] Value _| Unit Voltage on any pin relative to Vss [Viv.Vour] | -1to+7_| Vv Voltage on Voo supply relative to Ves | Veco | - | -ito+7 | Vv Operating temperature | Toor | — | Oto 70 °C Storage temperature [ Tx | - | -55 to +150] °C Power dissipation [Po | - | 10 |w Short circuit output current r- [ - [ 5 | mA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are ex- ceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Referenced to Vss) [value Operating coo vos Le p= [as [sot ss |v [vss [= fo fe |e [VI pct sz00 Input high vokage, allinputs | Vm | - | 24 | — [es | v | Inputiow votage, alinputs [Vn | [10 | = [os | V |

S8E D MM 6724240 0012689 450 MBOKIU —— ° Kk I SEMICONDUCTOR GRoup — "MSM41256A8 DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Bymboiconation,MSME!TEEA Ti [nots OPERATING CURRENT" [so | Average power suply current loos [55 | mA (RAS, CAS cycling; tac= min) —_ [ MSM41256A-15| [50 | STANDBY CURRENT Power supply current (RAS = Cas Via) REFRESH CURRENT 1° [ss | Average power supply current lees | 50 | (RAS cycling, CAS = Wasi tac = min, [45 | PAGE MODE CURRENT* [ Msmai2s6a-10| | 40 | Average power supply current loca [35] (RAS = Vit , CAS cycling; tec = min. MSM41256A-15| [30 | REFRESH CURRENT 2° [Mswa1256A-10| [ ss | Average power supply current [MSM41256A-12| [50 | mA (CAS before, RAS; tac= min.) [45 | INPUT LEAKAGE CURRENT Input leakage current, any input pA (OVS Vin $ 5.5V, alt other pins not under test = OV) OUTPUT LEAKAGE CURRENT ho pA (Data out is disabled, OV < Vour < 5.5V) OUTPUT LEVELS Output high voltage (lox = -5 mA) Vou Vv Output low volage (lon = 4.2 mA) Vou Md Note”: ICC depends on output loading and cycle rates. Specified values are obtained with the output open. CAPACITANCE (Ta = 25°C, f = 1 MHz) Input capacitance (My ~Ag Dw) | Ons | - | = | 6 | oF Input capacitance (RAS, CAS, WE| | Ca | =| =| 7 | pr Output capacitance (Dour) [con [= | - [7 | pF * Capacitance measured with Boonton Meter.

58E D MM 6724240 0012690 172 MMOKIJ =MSM41256A" —————_ 9 K I SEMICONDUCTOR GROUP AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Notes 1, 2,3 a Parameter 12 -15 Notes Refresh period [ter |-| 4 [-[ 4 [-[ 4 [ms] - cycle time Z Read-wrte oyclotime | tao | 205] — | 225| - [260] — | ns | — ‘Access time from RAS | _tanc |. - | 100 | - | 120 | - | 150 [ins | 45 Access ime trom CAS | torc | - | 50 | - | 60 | - | 75 [ns | 45 ‘Output buffer turn-off oe peo [ef [elo [ol] |e] - Transition time [es [3s|s0 | s| so | 3 | s0 [ns] - RAS prochargetime | tar | 90] - | 90] - rool - [ns] - FAS pulse width [tras | 100 [10,000] 120 [10,000] 150 10,000 | ns | — RAS hold time [tan [sof - | 60] - [7s] - {ns} - GAS pulse width [_toas | 50 |10,000| 60 |10,000] 75 |10,000| ns | - CAS hold time [tosn | t00[ - [v20[ = [150] - [ns - FAS to CAS delay time | taco | 25| 50 | 25 | 60 |25| 75 |ns| 4 CAS to RAS setup time| tons | 20] - | 25 | - [ao] - [ne] - — po[- [ef = |x| time ~ Row address hoidtime | twa | ts] - | 15| - [15] - [ns] - adel aes eee . tasc _ time time toan time Res retcomees| = [°|-[2|- fel - |m|* time referenced to CAS Sse [al =|- ep time referenced to RAS eee set-up time

S8E D MM 6724240 0012691 005 MBOKIU —— _ 0 K I SEMICONDUCTOR GROUP ______ anenaya5gan AC CHARACTERISTICS (CONT.) . (Recommended operating conditions unless otherwise noted:) Parameter -10 Notes Write command pulse 6 _ width Write command hold _ width Write command to Write command to _ CAS lead time Datainsetuptime | tos [0 | = | o | = fo [= [as] = Data-in hold time [ton [20] = [20 [= [as [= Tns | CAS to WE delaytime | town [15 | = | 20 | - [25 | - [ns | 6 Refresh set-up time for | _ CAS referenced to RAS | "CS Refresh hold time for tro _ TAS referenced to RAS 4 CAS i precharge time ‘cra ns | - (C before R cycle) RAS precharge to _ CAS active time ce fe fl fol el [aI . tec 7 time Page mode read t _ write cycle time PRWe Page mode CAS. to - Precharge time P Refresh counter test ' _ cycle time ‘RTC Refresh counter test 10,000 10,000 10,000 - Fianna | tos [261020 foe] es oon] we Refresh counter test to 70 _ TKS precharge time Pr

SBE D MM 6724240 OOlebIe THS MMOKIU =@MSM41256A8 oKt SEMICONDUCTOR GRO — Notes: 1 Aninitial pause of 100 ps is required after power-up followed by a minimum of any eight RAS cycles (example: RAS only Refresh) before proper device operation is achieved. 2 The AC measurements assume the transition time (tr) = 5 ns. 3 Vin (min.) and Vi. (max.) are reference levels for measuring the timing of the input signals. Transition times are measured between Vin and Vi. 4 Operating within the taco (max.) limit insures that trac (max.) can be met. The spec. trcp (max.) is for reference only. If taco is greater than the specified taco (max.) limit, then the access time will be controlled exclusively by tcac. 5 Measured using an equivalent load circuit of 2 TTL loads and 100 pF. 6 The specs twes, tawo, and tow are not restrictive operating parameters. They are included in the data sheet for reference only. If twcs 2 twes (min.) then the cycle is an "Early Write" cycle and the data out will remain in a high impedance state throughout the entire cycle. If towo 2 tewo (min.) and tawo 2 tawo (min.) then the cycle is a "Read- Write" cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions are satisfied then the condition of data out will be indeterminate at access time. 7 Either the tart or the tacH spec. must be satified for a proper read cycle.

58E D MM 6724240 0012693 981 MBOKI¥ READ CYCLE . "ae oF EZ vont care WRITE CYCLE (EARLY WRITE) naam Do es, WOOK Sse WLLL pp No py Pp oor ou ZZ vont care

58E D Mm b7e4e40 00122694 818 MMOKIJ READ WRITE/READ-MODIFIY-WRITE CYCLE ZZ vont care PAGE MODE READ CYCLE = She OE ne ay Oe Wi i lle “ vwrcare

58E D MM G724240 OOL2b95 754 MMOKIU PAGE MODE WRITE CYCLE = hy tt co rae ass FZ vom care PAGE MODE READ-MODIFY-WRITE CYCLE “SEE | 'CAH on \\ VHLLLLLIS TIX, WLLL LLL

7 OFF SCAC—H OFF RCAC

our or OPEN 6: vor the EZ von care

S8E D MM 6724240 0012696 690 MMOKIJ =MSM41256As ———— 9 K I SEMICONDUCTOR GROUP —_— RAS-ONLY REFRESH CYCLE NOTE: GAS = Vin, WE, Din = Dont Care tac ass OV tras. we tre tran. tase Via- Dont Care CAS-BEFORE-RAS REFRESH CYCLE NOTE: Address, WE, Diy = Don't Care: axe Yu~ tras ad Vu we Vyo a OS VILL Lore Sour — oreN, -J Don't Care

S8E D MM 6724240 0012697 527 MMOKIU — 0 K I SEMICONDUCTOR GROUP —___ syygiat256a0 HIDDEN REFRESH CYCLE aus vos Tas tee. tras. tase] tase toan | ; D EH = En WE (Read) ven | ese \\ ‘= tw, Low, “ae (Read-Write) Vi~ Don't Care CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE pets Yn CLI. — HCL TTT Don't Care

S8E D MM 6724240 0012698 463 MMOKIJ aMsmai256Aa ———— 0 K I SEMICONDUCTOR GROUP MSM41256A BIT MAP (PHYSICAL-DECIMAL) as 7] 0 257 Sit | 510 | 508 [608 128 120 | 128 128 12a | 12a | 128 | 120 0 258 510 | 609 ea 384 04 | 304 256 | 257 [250 |250 120 | 129 | 129 | 129 255 § 259 509 38s 8 385 aes 7 5 ae [250 608 | 508 254 3 254 | 254 254 | 254 252 1 257 [260 | 250 sit | 610 510 510 510 | 510 | 510 10 | 510 257 [250 | 259 508 255 | 255 | 256 255 252 1 257 [258 | 259 510 sit sit sit [511 [511 sit [cn | oe 352 0 256 | 257 393 383 363 | 389 262 [289 | 254 | 256 a] 2 ° 257 | 260 | 259 sit 509 | 508 27 | 127 | 127 | 127 127 | v27 | v27 | 127 27 | 127 | 127 127 | 127| v27 | raz 254 256 | 257 [258 | 250 509 | 508 302 ae2 | se2 | see | 982 ae2 | 382 282 1 & 257 126 126 4 126 waa [ase [ase [5 stay ay al] § ar a | 3 | 257 | 257 | 257 | 257 257 | 267 | 257 | 257 || 8 257 | 267 | 257 2s7 | 287 257 [268 | 250 510 1 4 1 Bee [ase | 258 358 [a8 08 256 | 266 | 256 256 | 256 256 253 257 ° a Aa ROW « LOW, AB ROW = HIGH REFRESH ADDRESS REFRESH ADDRESS (0-255) (0-255) fine ine As ROW ADDRESS (DECIMAL) 8 = COLUMN ADDRESS (DECIMAL) ROW ADDRESS COLUMN ADDRESS eNs6, ONe7, BN, BN! 2N PosiTive ENs2,0Ne9, BNA, BS 2N NEGATIVE BNG6, Ne?, BN, ENst 2Net NEGATIVE BNS2,BNs9, ONo4, ONS ONS POSITIVE NO 1 8S Nao, 1.2,.285