MSM3764A

MSM3764A OKI | Alldatasheet

Document overview

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Technical content

65,536-WORD x 1-BIT DYNAMIC RAM GENERAL DESCRIPTION The Oki MSM3764< is a tully decoded, dynamic NMOS random access memory organized as 65,536 words x 1 bit. The design is optimized for high-speed, high-performance applications such as mainframe memory, buffer memory, peripheral storage, and environments where low power dissipation and compact layout are required. Multiplexed row and column address inputs permit the MSM3764A to be housed in a standard 16 pin DIP or 18 pin PLCC. Pin-outs conform to the JEDEC approved pin out. The MSM3764A is fabricated using silicon gate NMOS and Oki’s advanced Double-Layer Polysilicon process. This progess, coupled with single-transistor memory storage cells, permits maximum circuit density and minimum chip size. Oynamic circuitry, including the sense amplifiers, is employed in the design. Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and output are TTL compatible.

FEATURES

+ 65,536 x 1 RAM, 16 or 18 pin package + Three-state TTL compatible output * Silicon-gate, double-poly NMOS, single- + Gated CAS transitor cell * 128 refresh cycles/2 ms + Row access time: * Common I/O capability using Early Write 120 ns max (MSM3764A-12) operation 150 ns max (MSM3764A-15) + Output unlatched at cycle end to allow * Cycle time: extended page boundary and two-dimen- 220 ns min (MSM3764A- 12) sional chip select . 260 ns min (MSM3764A-15) + Read-Modify-Write, RAS-only refresh, and + Low power: Page-Mode capability 330 mW active, 28 mW max standby * On-chip latches for addresses and data-in + Single +5V power supply, +10% tolerance + On-chip substrate bias generator for high * TTL compatible, low-capacitive load input performance

= MSM37644 8 AA PIN CONFIGURATION (TOP VIEW) . Din NC vss CAS ad fell het nc [4] 16] Vcc din [2] fis] CAS we Gi] fr6) Dout We GI fa] Dout Ras G] FB] Ag — RAS Ag’ ne Bi fa] Nc fislAe ag’ El a) As” ao [8 f2}As* At PA. ay [Bl aA,” Ay Hola” v A CENTS EO co [8] 214, Aivoc A7 As * Refresh Address Pin Names Function Ao ~ Az ‘Address Inputs RAS Row Address Strobe CAS Column Address Strobe We Write Enable Din Data Input Dout Data Output Vee Power Supply (+5V) Vss Ground (OV) NC No Connection FUNCTIONAL BLOCK DIAGRAM RAS Timin — imi ons =D Timi = cor “ Column Column enerato Address ff aen, | iecress Decoders sare a ted Row Word ul fore De- | |Drivers| Memory Pata Din coders Registor Veo Vss + On-chip Vag

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (see Note) Voltage onanypinrelativetoVss | ~ —‘(|Vmw Nour] -1t0+7 [Vv Voltage on Vecsupply relativetoVes | - | Veo | -1t0+7 [ v Operating temperature [| Tom | Oto 70 °C Storage temperature | - | Tey _| —55 to +150 °C Power dissipation ee Short circuit output current | - [ - [ s | mA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Referenced to Vss) [value iy y|_ Operating Peemenet smoot | conauons Fp [mz ree Supply voltage [Veo [= | 45 [50 [ 55 [v] [Ves [| - [| o fo [ o [Tv

{Recommended operating conditions unless otherwise noted.) MSM3764A Poona | smeet eononn pa om" | ets Operating Current” Average power supply current loc1 mA (RAS, CAS cycling; tac= min.) Standby Current Power supply current \\oc2 mA (RAS = CAS = Vy, ) Refresh Current™ Average power supply current (RAS cycling, CAS = Vy ; tac = min.) Page Mode Current" Average power supply current loca (RAS = Vy. , GAS cycling; tpg = min.) Input Leakage Current Input leakage current, any input 1 (OV s Vy <5.5V, all other pins not u under test =OV) Output Leakage Current (Data out is disabled, hse -10 OV < Vours 5.5V) Output Levels. Output high voltage (low = -5 mA) Vou 24 v Output low voltage (Iq, = 4.2 mA) Vou - v * Icc depends on output loading and cycle rates. Specified values are obtained with the output open. CAPACITANCE * (Ta = 25°C, f = 1 MHz) aia | win. [ Max. | * Capacitance measured with Boonton Meter.

9 MSM3764A8

Recommended operating conditions unless otherwise noted. Notes 1,2,3 ran rd Min. | Mex. | Min. | Max. | Refresh period [tre | - | 2 | - | 2 | ns | = Random read or write cycle time | tac | 220 | - | 200 | - | ns | = Read-write cycle time [tawe [245 | — [260 | - | ns | - Page mode cycle time [tec [120 | - [tas | - | ns | = Access time from RAS [tac [ - [120 | - | 150 | ns [46 Access time from CAS [teas [| = | eo | - | 75 | rs | 46 Output buffer turn-off delay [torr | o | 35 | o | 40 | ns | = Transition time [tr [3 [as [3 | as | ns | = FAS precharge ie [ge feo =| v0 | [ns FAS pulse width | tras | 120 [10,000] 150 [10,000] ns | - RAS hold time [tron [eo | - | 7s [| - [ons | - GAS precharge time (Page cycle) | ter | 50 | - | 60 | - | ns | = GAS pulse width [ teas | 60 [10,000 | 75 [10,000] ns | CAS hold time [tose | 120 | - | 150 | - | ns | - FAS to CAS delay time | taco | 25 | 60 | 25 | 75 | ns | 7 CAS to RAS precharge time [tore | o | - | o | - | ns | = Row address set-up time [tan | o | - | o | - | ons | = Flow address hold time [te [is | - [as [| - [ons | = Column address set-up time [tasc | o | - | o | - | ns | = Column address hold time [toa | 20 | - | 20 | - | ns | - ceavar™ [fe [-[*[-[[- referenced to RAS Read command set-up time = Read command hold time [tron | o | - | o | - [ns | - Write command set-up time [twos | -10 | - | -10 | - | ns | 8 Write command hold time | twen | 40 [ - [as [ = | ns | - meee [=| -[=[- le referenced to RAS Write command pulse width [tw | 40 | - | 45 | — | os | = Write command to RAS leadtime| tam | 40 | - | 45 | - | ns | - Write command to CAS lead time [tem | ao | - | 45 | - | ns | = Data-in set-up time tos | o | - | o | - | ns | = Data-in hold time [tor [ao | = [45 | - | ns | = Data-in hold time referenced ftom | woo | - | of - | ms | - to RAS <a a GAS to WE delay [ tow] ao | - | a5 | - | RAS to WE delay [ two | 100 | - | 120 | - | ns | 8 Read command hold time frm | oo | - | 0 | - | | - referenced to RAS GAS precharge time [tcen | 30 | - | 35 | - | ns [ -

Notes: 1. Aninitial pause of 100 usis required after power-up followed by a minimum of any eight RAS cycles (example: RAS only Refresh) before proper device operation is achieved. 2. The AC measurements assume the transition time (tT) = 5 ns. 3. Vin (min.) and Vi. (max.) are reference levels for measuring the timing of the input signals. Transition times are measured between Vin and Vi. 4. Assumes that taco < taco (max.) If taco is greater than the maximum recommended value shown in this table, trac will increase by the amount that taco exceeds the value shown. 5. Assumes that taco < taco (max.) 6. Measured using an equivalent load circuit of 2 TTL loads and 100 pF. tcp (max.) is for reference only. If taco is greater than the specified tacp (max.) limit, then access time will be controlled exclusively by tcac. 8. The specs twcs, trwo, and tcwo are not restrictive operating parameters. They are included in the data sheet for reference only. If twos 2 twcs (min.) then the cycle is an “Early Write" cycle and the data out will remain in a high impedance state throughout the entire cycle. If tewo 2 tewo (min.) and trwo 2 trwo (min.) then the cycle is a "Read- Write" cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions are satisfied then the condition of data out will be indeterminate at access time. 9. Either the taRH or the tRcH spec. must be satified for a proper read cycle. READ CYCLE TIMING tag tras tl tre. tes taco I< tore ag Vin- teas oS KN LA tase | ea | nacosses i" 2D Elves KA 8 KYL tron, tes | |, Fn we YH Vie [+ Ice : trac ———— lorr Dour YOR, 3 EZ Don't Care

• _ MSM9764A8 WRITE CYCLE TIMING (EARLY WRITE) READ-WRITE READ-MODIFY-WRITE CYCLE we Ve Y LR LC Va- Yl LL Se . Don't Gare

| MSM3764A 8 RAS ONLY REFRESH TIMING Dour 1! Open HK Dont Care (GAS: Vin, WE & Din: Don't care) PAGE MODE READ CYCLE aS feel hag bee = | We we Don't Care

a #MS5764A8 PAGE MODE WRITE CYCLE Vu- . — _ f a We taco t tcas—e| toas—e | bal oAE vn es N fa aa i Dont Care PAGE MODE, READ-MODIFY-WRITE CYCLE a Se = .\\— <a way LES ees | Kes), we YY sg (WH —-—.0oD ¢qM"MM]. ; J fenton hoe eo teAe hoe [atone Dont Care

= MSM3764A @ — Aa eee HIDDEN REFRESH be Se Don't Care

— I Access time from RAS. cect (tras: Constant) (Relative value) vs. V oc vs. V cc ~~ Ta = 25°C an RTs trcle 220 5 trop min = tras: 120ns} ae tno ns » TIN =” AF tic 260 ns 8 § H % 10 ISN 3 =— trac = 330 ns 5 aa |e | Ser fs) % oe S 20 | tac = 500 ns % 8 Fs trac = 1000 ns ~ 40 45 50 55 60 40 45 50 55 60 VeclV] VoclVI —— ‘cor (tras: Constant) Access time from RAS. wo ceewe (Relative value) vs. Ta - Cy 14 50 ~ Voc = 5.0V _ Ta = 25°C Vo. = 55v ° trop min = tras: 120 ns cc = 9: a 12 = 40 Fa Vic = 5.0V re ai nenVAae Ly & 10 = — A 30 Sa Pir | ma S 08 8 20} a - 0 2 50 75 1 2 3 4 5 Ta[°c) Cycle Rate (1/ tag) [MHz] Access time trom RAS 'ce1 (tras : Constant) (Relative value) vs. V cg vs. Ta 14 50 ¥ : oc = 5.8V & | vere || = eS 6 " E Ac = 220 ns v1.2 = 40 | “@ 1.0 NS i 30 2 i So & tre = 330 ns 8 os Pee OC % 20 tac = 500 ns = ae) | 3 tac = 1000 ns “40 45 50 55 60 0 2 «§0 75 VeclV] Ta[°C}

MSM 7.64 A 8 AR loot (tap : Constant) vs. Veg loca vs. Veo 50 50 Egy Re eS Le tad = 260 ns 2 € a tpg = 330 ns = } | & 30 se tags = 500 ns 2 30 se Tor oor i RC = ete Ta = & | tad = 1000 ns g E== a2 50 = 20 ee 20 Ce epermny— Ta = 40 45 50 55 60 40 45 50 55 60 Veco] Vec(V) 1 oc1 (tap : Constant) vs. Cycle rate Igoe vs. Ta

50 Ta = 25°C =58V _ 890 Wee=sav

= | tap =90 ns ‘co = 8: z Vin: max £ 40 ie Vicg = 5.0V £ 40 tal Leer ZA ATS | 4 ee S 20 - AA 8 20 [— - EI tT “tet ty 1 2 3 4 5 0 2 80 75 Cycle Rate (1/ tac) [MHz] Ta[°C] loc (tap: Constant) vs, Ta “TET TT = f=—a tac = 220 ns = = tric = 260 ns 8 yg (tte = 990 ns & =a tric = 500 ns 5 20 | | tle = 1000 ns < Voc = 5.5¥ trp: 90ns 0 86250650 Ta [°C}

— —OQ0 a AAS MIS M3764 A 1 ¢¢g (tras : Constant) vs. V co | coa (tap: Constant) vs. Voc 40 40 z [Te=25c z ° [Ta=esec | 220 ns é tase tne] ‘cy 220.n8 E | tre = 900s = tee F360 ns = 30 . 5 30 = e a aoe inc = 330 ns 2 20 I the = 1000 ns 3” —= tac = 500 ns 3 LT

2 TL tcl 1000 z _|

< 10 — AC = ns 5 10 40. 45 50 55 60 40.45 5.0 65 60 Voc Vecl¥} I ccs (tras : Constant) Voca (tap : Constant) vs. Cycle rate vs. Cycle rate 40 40 - = 25°C 1” Fras 25°C Z| mass 100 m8 oo =85V Z| tae 90 ns Yoo = 58¥ = x0 Vig = 5.0V = 30 = oc = 3 LZ vec = 45 3 = Voc = 4.5V

5 LA, S +

‘A nian 3 | 3 io € 10 @ su [| | el | S 9 20 1 2 39 4 5 1 2 3 4 5 Cycle Rate (1/ tac) [MHz] Cycle Rate (1/ tag) [MHz] loca (tras: Constant) vs. Ta fo aR tRP' Constant) v8 Ta z Veo =5.5V Ps Voo=5.5V < thas = 120 ns i _= tap = 90 ns = 390 Co tac = 220 ns i ae en tac = 220 ns 3 =e tac = 260 ns | eS the = 330 ns 1 fs) § 20}—} pm tac = 330 ns 3% _— (Reo Foo ns a fi = Teepe Re evry Tir" 8 Ltt = | | ~ 0 ° oO 25 50 7 oO 25 50 7s Talc} Ta [°C]

=| MSM3764A me Voce (tcas : Constant) 1 oc4 (tp : Constant) vs. V co vs. V cc 50 (752 25°C 50 Ta = 25°C = 40 toast 60 06 t 120 ns = 40 top = $008 t 120 ns — PC = é poe g 30 =a ted = 230 ns § 30 —-_ pe = 230 ns Fa Ess te = 400 ns 3 | teg = 400 ns E 2 =| & 2 ae 40 45 50 55 60 40. 45 50 55 60 Veo VeclV] loca (tas : Constant) loca (tgp: Constanty vs, Cycle rate vs. Cycle rate 50 (Tas 250 _ [tae 25°C = toas = 60 ng z top = 50 ns 3” LA Voc = 5.5V = 40 lA Voc = 5.5V $ LT Neo = 504 g LE vec =50v 30 Lg Voc = 4.5V 30 Be Voc = 4.5V eZ ae aa £ a | e | 20 % 20 BET TT a 2 4 6 8B 10 2 4 6 6 10 Cycle Rate (1/ tp¢) [MHz] Cycle Rate (1/ tpg) (MHz) ‘eq (teas: Constant) vs. Ta loca ttcp : Constant) vs. Ta 50 Voc =5.5V 50 Voo=5.5V z tas = 60 ns z tcp = 50 ns £ ot E a}+— 4 s =— tp = 120s B =_— tec = 120 ns § 20 +t tpo= 145s 30 == tec = 145 ns 3 = the = 230 ns & == the = 230 ns & 2 ot e400 ns 99 | | tpg = 400 ns a(t] [| a{i [| | 0. 2 50 75 0 2 60 75 Talc} Ta[°C}

ss sSSS0.- om MSM3764 A Address Input vs. V cc Address Input vs. Ta Ta = 25°C | | | Vec= 5.0V | 2.0) — a 2.0 Est ae 2. Vip max i [ee | | Be TTT TI “THETA Veco [VI Ta [°C] Data Input vs. V ¢¢ Data Input vs. Ta 2.0} ia 2.0 : | eT | : = | < 2 —— Bis aa Bis Vit max ghee | 2 i 3 2 TTT TET TET 40 45 5.0 5.5 6.0 Oo 25 50 75 Voc [VI Ta{°C] Clock Input vs. V og Clock Input vs. Ta 2.0] ee 20 > ' oF 2 | el _| 2 ito 1 TET TEE ET 4.0 45 5.0 5.5 6.0 [) 25 50 75 Vee 1 Ta[c]

a (Vcc = 5.5V, Ta = 25°C, 50ns/div) RAS/CAS CYCLE, LONG RAS/CAS CYCLE, RAS-ONLY CYCLE, PAGE MODE CYCLE es FATT TUE TT = NTT INTE 140 We CECEEEEEEEEeCCCECE EEE COBAMAROEET CUNSEHERERRRRRREOOUUENERRE SUNY A! REREA QAO0UE (SEEREREREENT SPUH0' W000 MERI CHI OO\\INNREY UHOEAAE @ CCPNCTCTIRTAAIN CRITE CCUNCA WIA ® CEPR TACIMNECCINGA COGAN ECCT CAENPTE CSTD LC CAT BELT T

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