MSM16911 OKI | Alldatasheet
Document overview
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Technical content
1,024-BIT SERIAL E7PROM eee SSS
FEATURES
+ CMOS Floating Gate Technology + Self timed programming cycle with Auto- * Single +5-volt supply Erase + Eight pin plastic package + Word and chip erasable * 64 x 16 or 128 x 8 user selectable serial + Operating range 0°C to 70°C memory * 10,000 erase/write cycles + Compatible with GI5911 * 10 year data retention PIN CONFIGURATION (TOP VIEW) FUNCTIONAL BLOCK DIAGRAM Vee GND tl
8 Pin Dual-In-Line MEMORY
8 Pin S.O. Package ‘ong | |asa] orgerte ~ rH] cea] debnowaun ~ CLK 2] RoyBusy | ,, Pane 01] [6] ORG ; cs Do [4] [5] GND Sais novus cs Chip Select ORG Memory Array Organization Selec- CLK Clock Input tion Input. When the ORG pin is ol Serial Data Input connected to +5 V the 64 x 16 bo Serial Data Output organization is selected. When it Voc +5 V Power Supply is connected to ground the 128 x 8 RDY/BUSY Status Output organization is selected. If the ORG GND Ground pin is left unconnected, an internal pull-up device selects the 64 x 16 organization. 761
=2MSM169118_ ——A Aa INSTRUCTION SET instruction] S¥"t[opcoue_—_Aaaress_[_Data__| comments Bt |PredelF6 x6 | 66x | T20x8 | C4 x16 | READ 1 | 1000 | Ag—Ay | As—Ao Read Address Ay-Ao PROGRAM] 1 | x100 | Ag—Ao | As —Ao| Dy —Do | Dis~ Do | Program Address An-Ao PEN 1 0011 0000000 | 000000 Program Enable PDS 1 0000 | 0000000 | 000000 Program Disable ERAL 1 0010 | 0000000 | 000000 Erase All Addresses WRAL 4 | 0001 | 0000000 | 000000 | D, — Dy | Dys— Do | Write All Addresses DIDO: The Data In and Data Out pins can be tied together, however bus contention can occur if ‘A0is held ata high level during the required dummy bit (logical 0) that precedes the read operation. Under these conditions, the voltage level on the Data Out pin is undefined and depends on the relative impedance between the signal source driving AO and the Data Out pin. The higher the current sourcing capability of the signal driving AO, the higher the voltage level is on the Data Out pin. Power-On Data Protection Circuitry: During power-up all modes of operation are inhibited until Voc reaches a level of approximately 3.0 volts. During power-down the source data protection circuitry acts to inhibit all modes when Vcc falls below the voltage range of approximately 3.0 volts.
ELECTRICAL CHARACTERISTICS
Input Voltage Ta = 25°C 0.3 ~ Voc+ 0.3 Vv ‘Output Voltage 0.3 ~ Voo+ 0.3 v ‘Storage Temperature —55 ~ + 150 °C Note: Permanentdevice damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted tothe conditions as recommended. Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE 762
(Voc = 4.5V to 5.5V, Ta = 0°C ~ 70°C, unless otherwise specified.) Parameter [symeat| ——_conanone ft | un Notes [teen iegrgowes-1 |=} 9 [ma] Power Supply Current Veo = 5.5V CS, CLK, DI = OV’ lece 100 | pa DO, ORG = OPEN "L" Input Voltage Vi ~0.1 | 08 [rrin-2ima | =| oe | V| “L" Output Voltage Vou | oMosin=100ya |= [on |v | “H" Output Voltage Vou ot Y [24 | = | CMOS fon = -100 pA [veces | - | ¥ | Input Leakage Current | lu | Van = 55V [10 | va] Output Leakage Current Vou =55V CS=0 [10 | | AC CHARACTERISTICS (Vcc = 4.5V to 5.5V, Ta = 0°C ~ 70°C, unless otherwise specitied.) meer arcane peta moe [Min] Typ] Max| ok Fins a ee ee CS Setup Time Referenced to CLK Falling [toss | - [oz] - | - [us| — CS Hold Time Referenced to CLK Rising | tosn | — [01] - | - | us| - Di Setup Time Referenced to CLK Rising | tos | - | o4] - | — | us| - DI Hold Time Referencedto CLK Rising | tom | - | o4| — | - [vs | — CLK Pub gh Tine bem |= ef = [= foe f= GiK Pe Low Ti bien |= [et = f= fm = Delay Time of DO Rising Referenced to ; CLK Rising Delay Time of DO Falling Referenced to j CLK Rising "Tine of Sue Poona ww) [ve | = |=} - oma = Note 1: Condition: C= 100pF and Voy/oH = 0.8/2.0 763
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Figure 1. Synchronous Data Timing Figure 2. READ
Figure 3. PROGRAM address are erased and the new data is written to the same address. duration of the automatic programming cycle as indicated by tp.
Figure 4. PEN (Program Enable) and PDS (Program Disable) Programming must be preceded once by a programming enable (PEN) instruction. Programming remains enabled until a programming disable (PDS) instruction is executed. READ instruction is independent of both PEN and PDS instructions.
Figure 5. ERAL (Erase Alll)(128 x 8) Entire chip erasing is implemented with the ERAL (erase all registers) instruction. All specifications and details published are subject to change without notice.
Figure 6. WRAL (Write All) (128 x 8) of the array are set to their proper values.