MSC7110-01

MSC7110-01 OKI | Alldatasheet

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MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 GENERAL DESCRIPTION The MSC7110-01/MSC7112-01 is a display controller to display the timer of video tape recorder, channel operation, and other infomaiton by a vaccum fluorescent display tube. Display data is input by serial transfer from microcontroller.

FEATURES

• Provides the interface with a microcontroller by three signal lines. : DATA IN, CLOCK, and LOAD
• Driver output can directly be connected to a vaccum fluorescent display tube without a pull-down resistor.
• Display is turned on by dynamic drive mode. The number of display digits are programmable in the range of : 1 to 12 digits (MSC7112-01) 1 to 16 digits (MSC7110-01)
• 12-segment driver output : 16 driver outputs (MSC7112-01) 12 driver outputs (MSC7110-01)
• The LED drivers can turn on 5 outputs statically.
• RAM data can directly be displayed.
• The brightness adjustment is programmable and brightness can be adjusted every 1/15 step.
• Built-in power-on-reset circuit
• The vacuum fluorescent display tube driver outputs high withstand voltage : VDD-VEE=45V (max).
• Logic supply voltage : V DD=5V ±10%
• Package options: 42-pin plastic SDIP (SDIP42-P-600-1.778) : (Product name : MSC7112-01SS) 44-pin plastic QFP (QFP44-P-910-0.80-2K) : (Product name : MSC7110-01GS-2K/MSC7112-01GS-2K) ¡ Semiconductor MSC7110-01/7112-01 12-Segment · 16-Digit or 16-Segment · 12-Digit Display Controller/Driver FEDL7110-03 This version: Sep. 2000 Previous version: Nov. 1997

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 BLOCK DIAGRAM MSC7110-01 SEG A SEG L D16 LED1 LED5 (b0) (b11)

• 12 (0)
• 16 (15)
• 5 SEG DRVLATCHLATCH SCLK DATA IN LOAD DIGIT TIME COUNTER DOWN COUNTER DUTY CYCLE COUNTER POR VEE (–20 to –40) VSS (0V) VDD (+5V) OSCI OSCO LOAD bit 0 POR POR OSC TIMING GENERATOR CONTROL TEST MODE D•C•R LOAD b15-17 COMMAND DECODER bit 18 S D•C•C L D•C•RL b0-3 POR18-bit LATCHL 18-bit S•RI D•T•C b0-16 W•A LOAD W•A•C COUNT b0-3 D•R LOAD fW RAM PC L 44 4 O D•R LATCH R•A•C COUNT ADDRESS COMP b0-4 W•A•C R•A•C ADDRESS SELECTORW/R 4 b0-3 17 17 16 12 L R L A=B A=B BA A=B A0-A3 L L DIGIT LOAD BLANK BLANK DUTY L•R LATCH LED DRV DIGIT DRVDECODER 16W · 17bits RAM RAM fR PC2PLA PC1 PLA fR L (ROM) PLA 32 · 16bits Address L•R LOAD Q OE O OE LATCH

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 MSC7112-01 SEG A SEG P D12 LED1 LED5 (b0) (b15)

• 16 (0)
• 12 (11)
• 5 SEG DRVLATCHLATCH SCLK DATA IN LOAD DIGIT TIME COUNTER DOWN COUNTER DUTY CYCLE COUNTER POR VEE (–20 to –40) VSS (0V) VDD (+5V) OSCI OSCO LOAD bit 0 POR POR OSC TIMING GENERATOR CONTROL TEST MODE D•C•R COAD b15-17 COMMAND DECODER bit 18 S D•C•C L D•C•RL b0-3 POR18-bit LATCHL 18-bit S•RI D•T•C b0-16 W•A•C LOAD W•A•C COUNT b0-3 D•R LOAD fW RAM PC L 44 4 O D•R LATCH R•A•C COUNT ADDRESS COMP b0-4 W•A•C R•A•C ADDRESS SELECTORW/R 4b 0-3 17 17 16 16 L R L A=B A=B BA A=B A0-A3 L L DIGIT LOAD BLANK BLANK DUTY L•R LATCH LED DRV DIGIT DRVDECODER 16W · 17bits RAM RAM fR PC2PLA PC1 PLA fR L (ROM) PLA 32 · 16bits L•R LOAD Q OE O OE LATCH R R

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 INPUT AND OUTPUT CONFIGURATION Input Pin Output Pin VDD LOAD DATA IN SCLK OSCI VDD POR VDD R OSCO SEGA-L SEGA-P VEE VDD D1-D12 D1-D16 VEE LED1- LED5 VDD VDD VDD *1 MSC7110-01 *2 MSC7112-01

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 PIN CONFIGURATION (TOP VIEW) MSC7110-01 /#03/#04 D12 V EE D10 D11 SEGD SEGE SEGF SEGG SEGH V EE SEGI SEGJ SEGK SEGL LED1 VDD POR OSCO OSCI LOAD DATA IN SCLK SEGA SEGB SEGC D13 D14 D15 D16 LED5 V SS VEE LED4 LED3 LED2 44-Pin Plastic QFP

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 MSC7112-01 D12 V EE D10 D11 SEGD SEGE SEGF SEGG SEGH V EE SEGI SEGJ SEGK SEGL SEGM VDD POR OSCO OSCI LOAD DATA IN SCLK SEGA SEGB SEGC LED1 LED2 LED3 LED4 LED5 V SS VEE SEGP SEGO SEGN /#06/#07 44-Pin Plastic QFP

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 OSCI 1 LOAD 42 OSCO 2 DATA IN 41 POR 3 SCLK 40 VDD 4 SEG A39 D1 5 SEG B 38 D2 6 SEG C 37 D3 7 SEG D 36 D4 8 SEG E 35 D5 9 SEG F 34 D6 10 SEG G 33 D7 11 SEG H 32 D8 12 SEG I 31 D9 13 SEG J 30 D10 14 SEG K 29 D11 15 SEG L 28 D12 16 SEG M 27 LED1 17 SEG N 26 LED2 18 SEG O 25 LED3 19 SEG P 24 LED4 20 V EE23 LED5 21 V SS22 MSC7112-01 42-PIN PLASTIC SDIP Note: The product name actually printed on the product is "C7112-01".

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 PIN DESCRIPTION Symbol VEE VDD VSS Number of Pins Type Connected to Power source

Description

VDD-VSS: Supply voltage for internal logic VDD-VEE: Supply voltage for VF display tube driving circuit logic DATA IN 1 I Input of display data of the shift register Input from the MSB (positive logic). SCLK 1 I Microcontroller Shift clock of the shift register. Data is shifted at the falling edge of SCLK. LOAD 1 I Latch clock input for display data. When this pin is at a "H" level, the data is not latched to pass through the latch circuit. When the pin is at a "L" level, the data when the pin is at the "H" level is latched. POR 1 I — Internal logic reset input upon power-on. During reset, the 18-bit internal latch, duty cycle register, digital register, LED register, and write/read address register are all reset, and the outputs of SEGA to SEGP(*a), D1 to D12 (*b), and LED1 to LED5 go off. Connecting of an external capacitor to the pin allows power- on reset. Schmitt with pull-up resistor using diode OSC I 1 I — Input for oscillation circuit When an external resistor and a capacitor are connected, an oscillation circuit is formed. C=100pF, R=47kW f OSC=235kHz±20% OSC O SEGA-L SEGA-P O Anode side of VF display tube Output for driving anode electrodes of VF display tube. The output is complementary. D1-D12 D1-D16 O Grid side of VF display tube Output for driving grid electrodes of VF display tube. The output is complementary. LED1-LED5 O LED LED driving output. The output is complementary.5 *a SEGA to SEGL in case of MSC7110-01 *b D1 to D16 in case of MSC7110-01 *1 In case of MSC7110-01 *2 In case of MSC7112-01

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 ABSOLUTE MAXIMUM RATINGS RECOMENDED OPERATING CONDITIONS Parameter Symbol Oscillation Frequency Operating Temperature Supply Voltage (1) Supply Voltage (2) kHz V V Condition Unit Range 200 to 500 –20 to +75 4.5 to 5.5 25 to 45 f OSC TOP VDD VDD-VEE

ELECTRICAL CHARACTERISTICS

V V Condition Unit V IH VIL Typ. Max. 0.3V DD High Level Input Current mAIIH —1 mAIIL2 –55 –110 VVOH1 VDD–1.5 — VDD=5.5V, VI=VDD VDD=5.5V, VI=0V VDD=4.5, IOH=–6mA Low Level Output Voltage (1) VVOL1 VEE+0.8 V EE+1.3VDD=4.5, IOL=0.2mA (VDD–VEE=45V, VDD=5V±10%, Ta=–20 to +75°C) Low Level Input Current (2) High Level Output Voltage (1) Min. 0.7VDD –27 V DD–2.2 High Level Output Voltage (2) VVDD=4.5, IOH=–30mAVOH2 VDD–2.3 — Low Level Output Voltage (2) VVOL2 VEE+0.8 V EE+1.3 VVOH3 —— VVOL3 — 0.5 mAIDD 8.5 15 VDD=4.5, IOL=0.2mA VDD=4.5, IOH=–10mA VDD=4.5, IOL=0.1mA VDD=5.5V, No load fOSC=245kHz High Level Output Voltage (3) Low Level Output Voltage (3) Current Consumption VDD–2.9 VDD–1.5 All input Applicable pin All input All input All SEG output POR All SEG output All DIGIT output All DIGIT output LED1-LED5 LED1-LED5 mAIIL1 —– 1VDD=5.5V, VI=0VLow Level Input Current (1) — All input except POR Parameter Symbol Input Voltage Power Dissipation Supply Voltage (1) Supply Voltage (2) V mW V V Condition Unit Range –0.3 to VDD+0.3 to 500 –0.3 to +6.5 0 to 50 Ta£25°C VI PD VDD VDD-VEE Output Current Storage Temperature mA mA mA –60 –20 –55 to +150 –10 All DIGIT output LED1-LED5 All SEG output I IO3 TSTG IO1

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 AC Characteristics Parameter Symbol SCLK Cycle Time SCLK, LOAD Pulse Width ms ms Condition Unit t CP tW Min. Max. Data Setup Time nstDSU 500 — nstDHD 500 — mstSL 2— mstLS 2— LOAD Cycle Time 1* mst LCYC1 205 —fOSC=245kHz (VDD=5V±10%, Ta=–20 to +75°C) Data Hold Time SCLK-LOAD Time LOAD-SCLK Time mst LCYC2 200 —fOSC=245kHzLOAD Cycle Time 2 Typ. *t LCYC1>16/fOSC must be satisfied. tLCYC1 tLCYC2 tCP tW tDSU tDHD tSL tW tLS SCLK DATA IN LOAD 0.7VDD 0.7VDD 0.7VDD 0.3VDD 0.3VDD0.3VDD 0.7VDD 0.7VDD 0.7VDD 0.7VDD 0.3VDD Oscillation Characteristics Parameter Symbol Oscillation Frequency kHz Condition Unit C=100pF, R=47kW/CRfOSC Typ. 235 Max. 282 (VDD=5V, VDD–VEE=25V to 45V, Ta=–20 to +75°C) Min. 188 Applicable pin OSCI, OSCO

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 TIMING DIAGRAM 16-digit display SEGn t1= 64 · 16 = 1024T D16 VDD VEE D15 D14 D13 D12 D11 D10 VDD VEEt2 60T t1=Frame cycle f OSC=245kHz t2=Display timing t 1=4.096ms t3=Blank timing t 2=240ms t3=16ms T=1/fOSC

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 FUNCTION DESCRIPTION Command Description The RAM data is output directly to the SEGA to SEGP pins (Positive logic) The write address is set in the write address counter. (The write position is set.) Display data is set in the LED register and output to the LED1 to LED5 pins (Positive logic) The number of digits is set in the digit register. DATA DISPLAY L.R LOAD D.R LOAD W.A.C LOAD b SEGA LED1 Input data The TEST mode is set. The duty value is set in the duty cycle register. D.C.R LOAD TEST MODE ·/CR LOAD SEGB LED2

• /CR SEGC LED3
• /CR SEGD LED4
• /CR SEGE
• /CR LED5
• /CR
• /CR
• /CR SEGF
• /CR
• /CR
• /CR
• /CR
• /CR SEGG
• /CR
• /CR
• /CR
• /CR
• /CR SEGH
• /CR
• /CR
• /CR
• /CR
• /CR SEGI
• /CR
• /CR
• /CR
• /CR
• /CR SEGJ
• /CR
• /CR
• /CR
• /CR
• /CR b10 SEGK
• /CR
• /CR
• /CR
• /CR
• /CR b11 SEGL
• /CR
• /CR
• /CR
• /CR
• /CR b12 SEGM
• /CR
• /CR
• /CR
• /CR
• /CR b13 SEGN
• /CR
• /CR
• /CR
• /CR
• /CR b14 SEGO
• /CR
• /CR
• /CR b15 SEGP b16 b17 Function LSBMSB
• : Don't Care *1*1*1*1 Command *1: Ignored in the case of MSC7110-01.

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 Relation between write address and digit output Corresponding digit output F D16 E D15 D D14 C D13 B D12 A D11 D10 Write address count *1*1*1*1 *1: Ignored in the case of MSC7112-01 Inputting Display Data LED display Display data is output to the LED1 to LED5 pins in correspondence with each bit by executing the L. RLOAD command. Input data uses positive logic. When the data is 1, the LED lights. When the data is 0, the LED goes off. VF display (RAM direct display) Set optional data in the digit register and the duty register, and execute the W.A.C LOAD command to set the display digit position. Execute the DATA DISPLAY command to write the b0 to b15 (*1) display data in the RAM. The write address counter is incremented by one. The the digit register. *1 : b 0 to b11 display data in the case of MSC7110-01. Brightness Adjustment The brightness can be adjusted by using the values of the duty cycle register (D.C.R) and the digit register (D.R). The value of the duty cycle register changes the pulse width (B) at the D1 to D16 output pins, and the value of the digit register changes the cycle (A). The table below gives the relation between the value of the duty cycle register and the duty. When all the values of the duty cycle register are 0 (in the case of 16-digit display), the display is blank. Dn B A VDD VEE A=64 · n=64 · 16=1024 n : Number of display digits D.C.R b b B/A DUTY b b b B/A DUTY b b b B/A DUTY b b b B/A

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 Number of Display Digits The number of display digits is set by the digit register. The number of display digits ranges from 1 to 16 (*1). The value of the digit register and the number of digits are as follows: *1 1 to 12 digits in the case of the MSC7112-01 *2 Ignored in the case of the MSC7112-01 D.R b b digit D1-D16 D1-D1 D1-D2 D1-D3 Control b b b digit D1-D4 D1-D5 D1-D6 D1-D7 Control b b b digit D1-D8 D1-D9 D1-D10 D1-D11 Control b b b digit D1-D12 D1-D13 D1-D14 D1-D15 ControlD.R D.R D.R

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 APPLICATION CIRCUIT MSC7110-01 VF display tube Heater transformer GRID (DIGIT) Microcont- roller MSC7110-01+5V DATA IN SCLK LOAD –25 to –40V ZD C R VDD VSS VDD VSS VEE R2 LED D1-D16SEG A-SEG L OSCOOSCIPOR LED1 LED5 Output port ANODE (SEGMENT)

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Package weight (g)Oki Electric Industry Co., Ltd. Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (‡5 mm) 4.52 TYP. 2/Dec. 11, 1996 SDIP42-P-600-1.778

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Package weight (g)Oki Electric Industry Co., Ltd. Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (‡5 mm) 0.41 TYP. 4/ Nov. 28, 1996 Mirror finish QFP44-P-910-0.80-2K

MSC7110-01/7112-01¡ Semiconductor FEDL7110-03 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 2000 Oki Electric Industry Co., Ltd. Printed in Japan