MSC5301B-01 OKI | Alldatasheet

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MSC5301B-01¡ Semiconductor GENERAL DESCRIPTION The MSC5301B-01 is an LCD driver LSI with built-in RAM. The device’s bit mapping method offers greater flexibility because each bit of the RAM for display controls each section on the LCD panel. It can form a graphic display system of 64 x 16 dots in one chip. In addition, the display can be expanded by using additional LSIs.

FEATURES

  • LCD driving voltage range : 6 to 16V
  • Operating power supply voltage range : 5V ±10%
  • Display duty : 1/16 (1/5 bias)
  • Common output : 16 outputs
  • Segment output : 64 outputs
  • RAM capacity : 16 x 64 = 1024 bits
  • Serial transfer clock frequency (f SCK) : 500 kHz Max.
  • Multichip configuration available
  • Blanking available
  • Built-in RC oscillation circuit
  • Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name: MSC5301B-01GS-BK) ¡ Semiconductor MSC5301B-01 LCD COMMON/SEGMENT DRIVER WITH RAM E2B0017-27-Y2 This version: Nov. 1997 Previous version: Mar. 1996

MSC5301B-01¡ Semiconductor BLOCK DIAGRAM 16-DOT COM DRV (4-LEVEL DRV) 64-DOT SEG DRV (4-LEVEL DRV) 4-16 DECODER 64-BIT LATCH 4-BIT LATCH READ (4-BIT) ADDRESS COUNTER TIMING GENERATOR 64-BIT SHIFT REGISTER 64-BIT LATCH CHIP CTL 6-BIT LATCH 8-BIT SHIFT REGISTER FRAM IN/OUT BLK CTL POR CTL OSC INPUT CTL V4 V1 C0 C15 V DSP S63 S0 V 2 V3 VDSP GND VCC GND OS1 OS2 φ BLK POR FRAM V CC GND RAM RA3 RA2 RA1 RA0 WA3 WA2 WA1 WA0 WE φ 64x16 =1024 BITS LATCH A/D SI SCK CSO CS1

MSC5301B-01¡ Semiconductor PIN CONFIGURATION (TOP VIEW) S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 C10 C11 C12 C13 C14 C15 V CS0 V VDSP GND VCC φ OS2 OS1 FRAM BLK POR SCK SI A/D LATCH CS1 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 NC S45 S46 S47 S48 S49 S50 S51 S52 100 /#06 NC: No connection 100-Pin Plastic QFP

MSC5301B-01¡ Semiconductor ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Power Supply Voltage Input Voltage Input Voltage Power Dissipation Storage Temperature Symbol V CC VDSP VIN VINDP PD TSTG Condition Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C Ta = 85°C –55 to +125 Rating –0.3 to +6.5 –0.3 to +18.0 –0.3V£V IN£VCC+0.3 –0.3£VINDP£VDSP+0.3 275 Unit V V V V mW Condition GND = 0V GND = 0V Parameter Power Supply Voltage Power Supply Voltage Operating Temperature Shift Frequency Oscillation Frequency Frame Frequency Symbol V CC VDSP Top fSCK fφ fFR Range 4.5 to 5.5 6.0 to 16.0 –40 to +85 25 to 500 3.84 to 16.0 60 to 250 Unit V V kHz kHz Hz

MSC5301B-01¡ Semiconductor

ELECTRICAL CHARACTERISTICS

*1 Applicable to all input pins *2 Applicable to LATCH, A/ D, SI, SCK, BLK and POR pins *3 Applicable to CS0, CS1, OS1 and FRAM pins *4 Applicable to FRAM and f pins *5 Applicable to C0 - C15 pins *6 Applicable to S0 - S63 pins *7 f f = 6.4 kHz, f SCK = 200 kHz, no load, display pattern = checkers VDSP = 16V, Current flows into VCC pin *8 f f = 6.4 kHz, fSCK = 200 kHz, no load, display pattern = checkers VDSP = 16V, Current flows into VDSP pin *9 Applicable to OS1 pin Segment Driver Output Voltage VDSP = 10V VDSP = 10V (VCC = 5V, Ta=–40 to +85°C) Parameter "H" Input Voltage "L" Input Voltage Hysteresis Voltage 1 Hysteresis Voltage 2 Pull-up Resistance Pull-up Voltage "H" Input Current "L" Input Current "H" Output Voltage "L" Output Voltage Common Driver Output Voltage Supply Current 1 Supply Current 2 Symbol V IH VIL VHS1 VHS2 RPU VPH IIH IIL VOH VOL VDP VSS VDP VSS ICC IDSP Condition V I = 0V II < 1mA VCC = 5.5V, VIH = 5.5V VCC = 5.5V, VIL = 0V IO = –0.4mA IO = 1.6mA VCC = 5.0V VCC = 5.0V I = –10mA I = ±10mA I = ±10mA I = +10mA I = –10mA I = ±10mA I = ±10mA I = +10mA Min. 3.5 0.3 0.2 4.9 4.6 VDSP–0.4 V1–0.4 V4–0.4 VDSP–0.4 V2–0.4 V3–0.4 Typ. 0.8 0.4 Max. V CC 1.5 1.4 0.8 ±10 ±10 0.4 V 1+0.4 V4+0.4 0.4 V2+0.4 V3+0.4 0.4 6.0 0.5 Unit V V V V kW/CR V mA mA V V V V V V V V V V mA mA

MSC5301B-01¡ Semiconductor AC Characteristics *1 The dispersion of external resistors and capacitors is not included. RS = 1kΩ , RT = 16kΩ , CT = 4700pF, VCC = 4.5V to 5.5V (VCC = 5V, Ta = –40 to +85°C) Symbol Condition Min. Typ. Max. UnitParameter t1 —2 — — msSCK Clock Period t2 —1 — — msSI Data Setup Time t3 —1 — — msSI Data Hold Time t4 —1 — — msSCK-LATCH Time t5 — 1 5—— msLATCH Pulse Width t6 —1 — — msA/D Setup Time t7 —1 — — msA/D Hold Time t8 —1 — — msA/D-SCK Time t9 — ——2 0 msPOR, BLK Fall Time t10 CL = 50 pF — — 0.3 msf, FRAM Rise Time t11 CL = 50 pF — — 0.3 msf, FRAM Fall Time fFR *1 85 100 115 HzFrame Frequency SCK SI LATCH t5 t7 t8t6 A/D

MSC5301B-01¡ Semiconductor VCC POR, BLK 90% 10% GND VDSP f, FRAM 90% 10% t11 t10 GND GND 1/fFR Frame A Frame B 1/fFR VCC

MSC5301B-01¡ Semiconductor The relationship between the frame frequency fFR and internal clock frequency ff is expressed by the following equation: (RC oscillation frequency = internal clock frequency) ff = 4 x 16 x f FR In addition, the relationship between the frame frequence fFR and frame synchronizing signal frequency fFRAM is expressed by the following equation. fFRAM = fFR/2

  • CS0 (Pin 30), CS1 (Pin 31) Chip select input pins. Master or slave mode is selected by CS0 and CS1 as shown in the table below. A maximum of 4 chips can be connected in this manner. Use the master mode when using a single device. FUNCTIONAL DESCRIPTION Pin Functional Description
  • OS1 (Pin 39), OS2 (Pin 40), f (Pin 41) These are pins for the RC oscillation circuit. Connect external resistors and a capacitor as shown below. When inputting the external clock pulse, input it to OS1 pin. OS2 and f pins should be left open. OS1 OS2 f/CR CTRS RT CS0 CS1 Operation mode L L Master mode H L Slave mode L H Slave mode H H Slave mode H : VCC level L : GND level

MSC5301B-01¡ Semiconductor

  • FRAM (Pin 38) This is an input and output pin for the frame synchronizing signal to be used for master/slave configuration. This is used as an output pin in master mode and as an input pin in slave mode.
  • SI (Pin 34) This is a serial data input of address data (8 bits) and segment data (64 bits). A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained.
  • SCK (Pin 35) This is a shift clock input of address data (8 bits) and segment data (64 bits). The serial data is shifted at the rising edge of SCK pulse. A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained.
  • LATCH (Pin 32) This is a latch pulse input of address data (8 bits) and segment data (64 bits). The latch data comes through at "H" level of LATCH and the data just before "H" level is latched at "L" level. A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained.
  • A /D (Pin 33) This is a data select signal input of address data (8 bits) and segment data (64 bits). "H" level is set in the case of address 8-bit input and "L" level is set in the case of segment data 64-bit input. A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained. DSP (Pin 44), V1 (Pin 29), V2 (Pin 45), V3 (Pin 46), V4 (Pin 28), VCC (Pin 42), GND (Pin 43) These are power supply pins for this LSI and bias power supply pins for LCD driving. VCC, which is a power supply pin, is from 4.5V to 5.5V and GND, which is a ground pin, is 0V. VDSP, which is an LCD driving power supply pin, is usually used in the range between 6V and 16V. V1, V2, V3 and V4 are bias power supply pins for LCD driving and are usually used with the bias voltage supplied from an external source.

MSC5301B-01¡ Semiconductor

  • BLK (Pin 37) This is an input pin to control the LCD panel display. When a "H" level is input (or when this pin is open), the segment output pins S0 - S63 come to the levels V 2 - V3 and the LCD panel is turned off. In addition, during this period, reading of data from display RAM stops but writing into the display RAM of address and segment data input from the SI pin is enabled. When this pin is changed from "H" to "L" level, the frame synchronizing signal FRAM is output within 2 cycles of an internal clock ff, and multiple chips are synchronized. Then, the display RAM address is set to "0000". After 1/16 frame cycle from FRAM signal generation, the output is applied from the "0001" data of the display RAM address to the segment driver. When the power supply is turned on, keep this pin to "H" level (or leave open) until writing data to the RAM is completed, because the display RAM contents are undefined at power-on. A pull-up resistor (10 kW - 60 kW) and a Schmitt circuit are contained.
  • POR (Pin 36) This is a power-on-reset input pin. When a "H" level is input (or when this pin is open), the common and segment outputs come to the static display-off state regardless of the BLK pin and the segment output pins S0 - S63 become V 3 level and the common output pins C0 - C15 become V4 level. When this pin changes from "H" to "L" level, the frame synchronizing signal FRAM is output within 2 cycles of an internal clock ff, synchronized at multichip, and is moreover dynamic- operated from the frame B . The display RAM address is set to "0000." After 1/16 frame cycle from FRAM signal generation, the data at display RAM address "0001" is output to the segment driver. However, because the BLK pin is usually at "H" level when the power-on-reset is released, reading data from the display RAM stops and display-off segment data is forcibly transferred to the segment output. A pull-up resistor (10 kW - 60 kW) and a Schmitt are contained.
  • C0 (Pin 12) - C15 (Pin 27) These are 16-output pins of common driver which are used for LCD panel driving. The outputs have 4 levels. V DSP and GND levels are select levels. The V1 and V4 levels are non-select levels.
  • S0 (Pin 47) - S63 (Pin 11) These are 64-output pins of segment driver which are used for LCD panel driving. The outputs have 4 levels. VDSP and GND levels are used as display-on ones, which correspond to "1" of the display RAM data. V2 and V3 levels are used as display-off ones, which correspond to "0" of the display RAM data. NOTES ON USE Note the following when turning power on and off: The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to carry out the following power-on and power-off sequences: When turning power on: First turn V CC ON, next VDSP, V4, V3, V2, V1 ON. Or both ON at the same time. When turning power off: First turn V DSP, V4, V3, V2, V1 OFF, next VCC OFF. Or both OFF at the same time.

MSC5301B-01¡ Semiconductor Relationship Between LCD Screen Size and Display RAM This LCD driver has built-in RAM for the display of 16 x 64 = 1024 bits and each address corresponds to each 1/16 duty of the LCD. The data corresponds to the number of dots in the X direction. The relation between the LCD screen size and the display RAM is shown below. Relationship Between Frame Cycle and Display RAM Data The output of the display RAM data corresponds to the segment output. The relationship between the frame cycle and the display RAM data is as follows: S63 S0 C10 C11 C12 C13 C14 C15 1/16 duty Address Data Number of dots in X direction (64) Segment output (Contents of RAM) 1 frame cycle 0000 0001 0010 0011 1110 1111 0000 0001 First line address

MSC5301B-01¡ Semiconductor Multiple Configuration This LCD driver can form multiple configuration. It is possible to form a maximum of 4 devices (a panel of up to 256 · 16 dots in size can be formed) by using chip select signals CS0 and CS1. The devices in multiple configuration must be synchronized with one another. In this configuration, one device in the master mode and the other devices in the slave mode are used in combination. In the master mode, the original oscillation signal f and the synchronous signal FRAM are output; in the slave mode, the original oscillation signal f and the synchronous signal FRAM are input. Refer to items CS0 and CS1 of pin description on the mode setting method. The original oscillation signal output pin f of the master mode device is connected to the OS1 pin of the slave mode device and the synchronizing signal pin FRAM is also connected to the FRAM pin of the slave mode device. Connect SI, SCK, LATCH, A/D, POR and BLK of the master mode device to SI, SCK, LATCH, A/D, POR and BLK of each of the slave mode devices and connect them to CPU for control. In addition, connect the devices so that V DSP, V1, V2, V3, V4 and GND are shared between the devices, and connect them to each voltage level divided by external resistors. Address Data Configuration The lower address, which is the display RAM address, corresponds to the common sides C0 - C15 of the LCD panel. The upper address corresponds to the logical state of chip select pins CS0 and CS1 and the lower address is set to the device. For the device to output the common signal (f, FRAM), set both of the upper address 2 bits to "L". The 2 bits of dummy data can be set to either "L" or "H". DM DM CS1 CS0 Dummy data Upper address Lower address 2 bits 2 bits (MSB) (LSB) 4 bits

MSC5301B-01¡ Semiconductor Notes: 1. Make sure to set the address before writing the segment data to RAM. Then, write the segment data to RAM. 2. While the POR pin is "H" (upon power-on reset), neither the address data nor the segment data can be entered. Serial Signal to be Input From CPU The following signals are input from an external CPU to this LCD driver. - Serial transfer clock fi SCK - Serial transfer data fi SI - Serial transfer latch fi LATCH - Serial data select fi A/D The operations are shown in the following table. Timing Chart of Serial Signal Transferred From CPU Address data input mode Mode A/ D SCK LATCH SI H LSegment data input mode Shifts at the rising edge Shifts at the rising edge 8-bit address latch at falling edge (level sensitive) 64-bit segment data latch at falling edge (level sensitive) 8-bit address data Serial input from LSB side 64-bit segment data Serial input from S63 corresponding data "1" : Display-on data, "0" : Display-off data 1 234 5 6 78 12 3 6 3 6 4 A/D "H" at address data setting "L" at segment data setting SCK SI LATCH A0 A1 A2 A3 CS0 CS1 Dummy Dummy S63 S62 S61 S1 S0 Address data (8 bits) Segment data (64 bits) MSBLSB Address latch signal RAM write signal

MSC5301B-01¡ Semiconductor Operation upon Power ON (When Single Device Used) Dynamic operation (normal operation)Dynamic light-out state Frame B Frame B Frame A Frame A Frame BFrame BFrame A RAM address 0 - F Frame A 0 - F 0 - 0 0 - F 0 - F 0 - F 0 - F Segment signal output Common signal output FRAM f/CR (External R and C) BLK POR VCC

MSC5301B-01¡ Semiconductor (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFP100-P-1420-0.65-BK Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Mirror finish