MSC23236C OKI | Alldatasheet

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2,097,152-Word x 36-Bit DRAM MODULE : FAST PAGE MODE TYPE

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The OKI MSC23236C/CL-xxBS20/DS20 is a fully decoded 2,097,152-word x 36-bit CMOS Dynamic Random Access Memory Module composed of sixteen 4-Mb DRAMs (1M x 4) in SOJ packages and four 2-Mb DRAMs in SOJ (1M x 2) packages mounted with twenty decoupling capacitors on a 72-pin glass epoxy single-inline package. This module is generally used for memory expansion in parity applications such as workstations. The low-power version (CL) offers reduced power consumption for mobile computing applications like laptopsand palmtops. FEATURES i + 2-Meg x 36-bit organization | * 72-Pin Socket Insertable Module | MSC23236C/CL-xxBS20 : Gold tab | MSC23236C/CL-xxDS20: Solder tab | * Single 5 V supply +10% tolerance | * Access times : 60, 70, 80 ns | *Input : TTL compatible | * Output : TTL compatible, 3-state | « Refresh : 1024 cycles/16 ms (128 ms : L-version) * CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability * Multi-bit test mode capability j * Fast Page Mode capability | PRODUCT FAMILY 7 Access Time (Max.) Cycle Time Power Dissipation F: Ace amily trac | taa | teac | (Min.) _|Operating (Max)| Standby (Max.) : mscas2a6c/CL-e08s200s20 | eons | 30ns | 1Sns | t10ns | sss5mw | 110 mW/ scan. 7ossn0500 | 7One [Bn | 2008 | —He0ns | sone OTN wsceazs60% 8685000520 | 60ns | 40s | 20ns | 150as | aessmw _|'temW (“ves | 169

i MSC23236C/CL-xxBS20/0S20 0 IKE Semiconductor | PIN CONFIGURATION MSC23236C/CL-xxBS20/DS20 107.95 20.2 93 Max. | 3.38 20. 101.19 Typ. _ mae | | JAfAAAAAAAre 93.18 10.164 g 38 [\\t ooo pon, 72) 3.7 Min, : exer} 2720 6.35 1.04 Typ 1.27 Bb 95.25 | *1 The common size difference of the board width 12.5 mm of its height is Pin No. [Pin Name] Pin Name|| Pin No. |Pin Namel | Pin No. [Pin Name|| Pin No. [Pin Name 1 | Vs mio | as [| a | nc | ot | pov : 2 [poo || a7 [masa] 9 |r| we || ee | 0a 3 [oo |] ie | ae |] 33 | aa [faa | nc | pars 4 | par Pia [nc [sa | ase || 49 | 09 pasa 7 | poe [2 [00s [| 37 [vai || sa | page || 67 | Por a | pos |} 23 | ooa |] 38 | poss || “63 [bai [| 68 | Ppe 2 [ar |e [pas || 99 [ves [fs] 0008] 60 | Poa tf ne || 6 [oar a1] tase] a6 | paso |] 71 | | [ad || ar | aes [| «2 | cass |r| para [72 | vss CES AS | | Oc | DO M4 eee 1s | a3 [] 30} vec [fas Rast |] owe [fT Presence Detect Pins Pin No. MSC23236C/CL | MSC23236C/CL | MSC23236C/CL " -60BS20/0S20 | -70BS20/DS20 | -80BS20/DS20 _ j 87 es | NG 68 Po2 NC. 69 ee ee NC a a . 170

OKI Semiconductor MSC23236C/CL-xxBS20/DS20 BLOCK DIAGRAM ! ‘AO - AS — ‘ "ASO wt ft EE OO ad ag 90 |-000 {DO pp. ag 20 - 0018] DO pg. iH ie * ba pat | oa os H | LH ms 00 | po19—| 0a aed | TT] cas fom ms ETI TH as 00 f-daw—joo eT | til we ee 3 eo «Oe IT TTT we Be Daat Ee wilt Voc Vss Veo Vss Veo Vss Voc Vis [LY VT CTY Vy Ap-ag DO F-DO4— DO ag-ag ag 20 + 00224 DO pg. x | Fag 00 }-005—] 00 ARS ry a ms a |- 0023] 00 TS [| 7 we (F-00400 TT TT] aag 00 -0024-}00 ae Ho we eo ES we LL Ce ee owe Voc _Vss. Voc Ves Voc _Vss Voc Vs VV VV t-{ A009 007} Dos —/ 001 A089 }-4 f-{ 40-A9 001} oa2s—f 001 A0-19 +4 #1] BAS. 002 }-par7— Daz RAS tre P17] RAS Daz }- Da35—| Daz Ras A tH Bs Beth || Hee eine TT iwe oc we while « ue WE A0-Ag 0D F—DO9 — 00 Ag. ag ag-ag DO F027 00 gg. 4g Cl pas 00 }-d010- 00 “pag |] T |] pas 00 | -0026-] 00 ag [] TT | gag 20 | -bat1— Da tas gag (02 F-00200 eT TT ttl we | 3 paren) wet CO we we 0030 oe will Voc Ves b og Veo Vss Voc Veg b Sle _s [| [| LT [__ - DO + 0013 DO 7 -ag 00 |-DO31— DO go. baad ba bare Ba “ae us DQ f- 0032-4 DO amd 4 aS ust Tg (0 F-00338 D0 ae Tl we Be oat6: e wet [lie a asd oo wt | ely 9 7 | | EY vee i | [| tyes oo = Ver }j| i 171 | i

MSC23236C/CL-xxBS20/DS20 OKI Semiconductor r—rorewexseseo COT Semiconductor ELECTRICAL CHARACTERISTICS. Absolute Maximum Ratings Parameter Symbol | Unit Voltage on Any Pin Relative to Vss | Vin, Vour -1.0 107.0 Vv Voltage Vcc Supply Relative to Vss 10070 vo Short Circuit Output Current [tos 50 mA Power Dissipation [P| 20 w Operating Temperature *c Storage Temperature 40 to 125 °C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (Ta =0°C 10 70°C) Parameter _Symbol_ | Min, | Typ. | Unit Nec [45 | 50 v Power Supply Voita i eee a a Input High Voltage 24 | 65 |v input Low Voltage -10 | os Tv Capacitance (Ta = 25°C, f = 1 MHz) —_Feremtr Symbol [Wwe Max Unit input Capacitance (AO - AS) CCT Input Capacitance (WE) re | oF Input Capacitance (RASO-RASS) | Crs [| oF | Input Capactane (CRSO- CASS) [_Cwa| =a vo Capscines (000-0056) | ou | =| 20 or | Note: Capacitance measured with Boonton Meter. 172 \\

OKI Semiconductor MSC23236C/CL-xxBS20/DS20 Ee S80 23236C/CL-xxBS 20/0820 DC Characteristics Wor =5V £10%, Ta = 0°C to 70°C

4 IMSc2sz36c/cL|msc23238C/CLIMSC23236C/CL|

OVSViS65V; input Leakage Current tu | Al other pins not Dour disable Bulpu High Vonage iuie-50ma | 24 | Ve] 24] Wee] 24] Va | VI Output Low Voltage lot = 4.2 mA [o foal] o foal of oly __ Average Power Se een [l/l : tao = Min. (Operating) ce, (oe SSS cca . cen Gan Pucoow [=[ast— fact =a 15 Average Power RAS cycling, Supply Current TAS = Vin, 1010 1.2 (RAS-only Refresh) tac = Min. Average Power RAS cycling, Supply Current CAS before RAS, = | 1,2 _(CAS before RAS Refresh) tac = Min. Average Power RAS = Vit. Supply Current tcc7 | CAS cycling, 810 720 3 (Fast Page Mode) tec = Min. Supply Current TAS before - (Battery Backup) RAS cycling Notes: 1. Specified values are obtained with the output open. 2. Address can be changed once or less while RAS, iL 3. Address can be changed once or less while CAS=Vjji. 4. Vec-0.2 VS Vin S65V,-10V<SViL<02V. 5. L-version. | i 173

MSC23236C/CL-xxBS20/DS20 OKI Semiconductor AC Characteristics (1/2) (Voc = 5 V 210%, Ta = 0°C to 70°C) Note 1,2,3.9,10 Parameter bol| -608S20/DS20 | -70BS20/0820 | -80BS20/D820 | Unit| Note Random Read or Write Gycle Time [tac | 110 | — | 130 | — | 150 | — | as | Fast Page Mode Gycle Time {= | 4 | — | 80 | = [as] Access Time from BAS [ trac | | 60 | — | 70 | a 45.6 Access Time trom CAS Ftcac | — | 15 | — | 20 [20 | ns | as. Access Time from Column Address. [tm | — | 9 | — | 35 | — | 40 | ns | 4.6 Access Time trom CAS Precharge [tea | — | 35 | — [ 40 | — | a5 | os| a Output Low Impedance Time from CAS. Hef ofa fo tte 4 Output Butfer Turn-off Delay Time [ torr | o | 15 | 0 | 20 | 0 | 7 Transition Time | {3 [so [3 {so | 3 | 50 | as] 3 Retresh Period te Refresh Period (L-version) | tres [— [128 [ — [128 | — | 128 | ‘RAS Precharge Time | toe | 40 | — | so | — | 60 [— Ts] | AS Puise Width | tas | 60 [tox | 70 | 10K | 60 | 10K | ns | RAS Pulse Width (Fast Page Mode) —_—| trasp| 60 | 100K| 70 | 100K| 80 | ‘RAS Hold Time ere ta tate pete | CAS Precharge Time | toe | 10 | — | 10 | — | to | — [ns | TAS Puise Wiath [ tors | 15 [tox | 20 | 10K | 20 | tox | as | TAS Hold Time [tose [60 [| vo | = | 00 | — [ns | ‘CAS to RAS Precharge Time Hoe eat ete RAS to CAS Delay Time | too | 20 | 45 [20 | 50 | 20 | 5 FAS to Column Address Delay Time Hue 6 |e Le fete ei _ Row Address Set-up Time | wa] o | — [Vo [= | o | . | Row Address Hold Time Vtaan | 10 | [io [| — | to | — | ns] Column Address Set-up Time | tase | 0 | Hee _- Column Address Hold Time [ton | 15 | — [| 18 | — | ts [| — | : Column Address Hold Time fromPAS | tan | 50 | — | 85 | — | 60 | — | as Column Address to RAS Lead Time [tra | 30 | — | 35 | — | 40 | — | as | | 174 i

i OKI Semiconductor MSC23236C/CL-xxBS20/DS20 mcr MS 232360/CL-xxBS20/DS20 : AC Characteristics (2/2) (Voc =5V 210%, Ta= 0°C to 70°C) Note 1.2.39,10 Msc2s2sec/cL msezszsec/ct|Msczs236c/CL Parameter -608S20/D820 | -708S20/D820 | -s08S20/D$20 Note Read Command Set-up Time Het ea tet ; Read Command Hold Time [toon [ 0 | — [oo |—]of—] _ Read Command Hold Time referenced to RAS. [to [0 [= To | o [= fre | 8 | Write Command Set-up Time ee ett te et ta | Write Command Hold Time | twon | to | — | | — | Write Command Hold Time from RAS [ats Pett Tt _ ‘Write Command Pulse Wiath | twe [10 |=] 10 [= 10 [= Pas | Wete Command toRASteadTime | tam | 18 | — [20 | — | 20 | — | as | Write Command to CAS Lead Time T tow. | Se Data-in Set-up Time | ws | o | — fo f= fo] e+

1 Data-in Hold Time | tm | 1s | — [as |— | is | —]

Date-in Hold Time from RAS [tome [50 [—"]s8 [ = [eo [Tas | TAS Active Delay Time from RAS Precharge Se RAS to TAS Set-up Time (GAS betoreRAS)| tesa | 5 | — | 5 | — | 8 | FAS to CAS Hold Time (CAS betore FAS) | tom | 10 [ — | 10 | — | 10 | — [rs] CAS Precharge Time (Refresh Counter Test) Reet tte te WE to RAS Precharge Time (CAS betore RAS) [twee | 10 [ — | 10 [= [10 | — | WE Hold Time from RAS (CRS betore 2 RAS to WE Set-up Time (Test Mode) Twos | 10 [= [10 | —T 10 | [ ns | FAS toWEHold Time (Test Mode) | twm | 10 | — | 10 | — | 10 | — [rs | 175 |

MSC23236C/CL-»%B$20/D$20 OKI Semiconductor | i Notes: 1. A start-up delay of 200 is is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or TAS before Rae refresh) before proper device operation is achieved. ' When using the internal refresh counter, a minimum of eight CAS before RAS initialization cycles is required. | 2. AC mesurement assume ty = 5 ns. 3. Vip (Min.) and Vj, (Max.) are reference levels for measuring input timing signals. Transition times are measured between Vjy and ViL- 4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. | i 5. Operation within the tacp (Max.) limit ensures that trac (Max.) can be met. trcp (Max.) is specified as a reference point only. Iftacpis greater than the specified tpep (Max.) limit, access time is controlled by tcac. | 6. Operation within the trap (Max.) limit ensures that trac (Max.) can be met. trap 1 (Max.) is specified asa reference point only. If trap is greater than the specified trap (Max,) limit, access time is controlled by taa. ‘ 7. topr (Max.) defines the time at which the output achieves an open circuit condition and is not referenced to output voltage levels. 8. tach oF tar must be satisfied for a read cycle. 9, The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. Ina test mode CA0 is not used and each DQ pin now accesses 2 bit locations. Ina read cycle, if the 2 data bits are equal, the DQ pin will indicate a high level. If the 2 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 10. Ina test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values. See ADDENDUM E for AC Timing Waveforms 176