MSC23137D-XXBS9 OKI | Alldatasheet

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Technical content

1,048,576-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE This version: Feb. 23. 1999

DESCRIPTION

The MSC23137D-xxBS9/DS9 is a fully decoded, 1,048,576-word x 36-bit CMOS dynamic random access memory module composed of nine 4Mb DRAMs in SOJ packages mounted with nine decoupling capacitors on a 72-pin glass epoxy single-inline package. This module supports any application where high density and large capacity of storage memory are required.

FEATURES

  • 1,048,576-word x 36-bit organization
  • 72-pin socket insertable module MSC23137D-xxBS9 : Gold tab MSC23137D-xxDS9 : Solder tab
  • Single +5V supply ± 10% tolerance
  • Input : TTL compatible
  • Output : TTL compatible, 3-state
  • Refresh : 1024cycles/16ms
  • /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
  • Fast page mode capability
  • Multi-bit test mode capability PRODUCT FAMILY Access Time (Max.) Power Dissipation Family tRAC tAA tCAC tOEA Cycle Time (Min.) Operating(Max.) Standby(Max.) MSC23137D-60BS9/DS9 60ns 30ns 15ns 15ns 110ns 4455mW MSC23137D-70BS9/DS9 70ns 35ns 20ns 20ns 130ns 3960mW 49.5mW

R1.57 6.35 1.04Typ. 1.27±0.1 95.25 2.03Typ. 6.35Typ. Typ. 6.35 Typ. 10.16 ( 3.18 25.4±0.2 101.19Typ. 107.95±0.2*1 3.38Typ. 3.7Min. 5.28Max. +0.1 -0.08 1.27 (Unit : mm) MSC23137D-xxBS9/DS9 The common size difference of the board width 12.5mm of its height is specified as ±0.2. The value above 12.5mm is specified as ±0.5.

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name VSS /OE DQ19 DQ28 DQ0 DQ8 DQ20 DQ29 DQ1 DQ9 VSS DQ30 DQ2 DQ10 /CAS0 DQ31 DQ3 DQ11 NC VCC DQ4 DQ12 NC DQ32 DQ5 DQ13 NC DQ33 DQ6 DQ14 /RAS0 DQ34 DQ7 DQ15 NC DQ35 VCC DQ21 NC NC DQ16 /WE NC VCC VSS NC DQ22 PD1 DQ23 PD2 NC DQ24 PD3 NC DQ25 PD4 DQ17 DQ26 NC DQ18 DQ27 VSS Presence Detect Pins Pin No. Pin Name MSC23137D -60BS9/DS9 MSC23137D -70BS9/DS9 PD1 VSS VSS PD2 VSS VSS PD3 NC VSS PD4 NC NC

/WE /CAS0 /RAS0 A0-A9 DQ0 A0-A9 DQ DQ DQ DQ /OE VCC /RAS /CAS /WE VSS DQ1 DQ2 DQ3 DQ8 A0-A9 DQ DQ /OE VCC /RAS /CAS /WE VSS DQ9 VCC VSS C1-C9 A0-A9 DQ DQ DQ DQ /OE VCC /RAS /CAS /WE VSS DQ4 DQ5 DQ6 DQ7 A0-A9 DQ DQ DQ DQ /OE VCC /RAS /CAS /WE VSS DQ12 DQ13 DQ14 DQ15 A0-A9 DQ DQ DQ DQ /OE /RAS /CAS /WE DQ16 DQ17 DQ18 DQ19 DQ20 A0-A9 DQ DQ DQ DQ /OE /RAS /CAS /WE DQ21 DQ22 DQ23 VCC VSS VCC VSS DQ24 A0-A9 DQ DQ DQ DQ /OE /RAS /CAS /WE DQ25 DQ26 DQ27 VCC VSS DQ28 A0-A9 DQ DQ /OE VCC /RAS /CAS /WE VSS DQ29 DQ32 A0-A9 DQ DQ DQ DQ /OE /RAS /CAS /WE DQ33 DQ34 DQ35 VCC VSS /OE DQ DQ DQ10 DQ11 DQ DQ30 DQ DQ31

ELECTRICAL CHARACTERISTICS

( Ta = 25°C ) Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT -1.0 to +7.0 V Voltage on VCC Supply Relative to VSS VCC -1.0 to +7.0 V Short Circuit Output Current IOS mA Power Dissipation PD W Operating Temperature TOPR 0 to +70 Storage Temperature TSTG -40 to +125 Recommended Operating Conditions ( Ta = 0°C to +70°C ) Parameter Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V Power Supply Voltage VSS V Input High Voltage VIH 2.4 6.5 V Input Low Voltage VIL -1.0 0.8 V Capacitance ( VCC = 5V ± 10%, Ta = 25°C, f = 1 MHz ) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 - A9) CIN1 pF Input Capacitance (/RAS0, /CAS0, /WE, /OE) CIN2 pF I/O Capacitance (DQ0 - DQ35) CDQ pF Note: Capacitance measured with Boonton Meter.

(VCC = 5V ± 10%, Ta = 0°C to +70°C ) MSC23137D -60BS9/DS9 MSC23137D -70BS9/DS9 Parameter Symbo l Condition Min. Max. Min. Max. Unit Note Input Leakage Current ILI 0V ≤ VIN ≤ 6.5V: All other pins not under test = 0V -90 -90 µA Output Leakage Current ILO Data out is disable 0V ≤ VOUT ≤ 5.5V -10 -10 µA Output High Voltage VOH IOH = -5.0mA 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 4.2mA 0.4 0.4 V Average Power Supply Current (Operating) ICC1 /RAS cycling, /CAS cycling, tRC = min. 810 720 mA 1, 2 TTL mA Power Supply Current (Standby) ICC2 /RAS = VIH /CAS = VIH MOS mA Average Power Supply Current (/RAS only refresh) ICC3 /RAS cycling, /CAS = VIH, tRC = min. 810 720 mA 1, 2 Average Power Supply Current (/CAS before /RAS refresh) ICC6 tRC = min. 810 720 mA 1, 2 Average Power Supply Current (Fast Page Mode) ICC7 /RAS = VIL, /CAS cycling, tPC = min. 630 540 mA 1, 3 Notes: 1. ICC is dependent on output loading and cycles rates. Specified values are obtained with the output open. Address can be changed once or less while /RAS = VIL. Address can be changed once or less while /CAS = VIH.

AC Characteristics (1/2) MSC23137D -60BS9/DS9 MSC23137D -70BS9/DS9 Parameter Symbol Min. Max. Min. Max. Unit Note Random Read or Write Cycle Time tRC 110 130 ns Read Modify Write Cycle Time tRWC 150 180 ns Fast Page Mode Cycle Time tPC ns Fast Page Mode Read Modify Write Cycle Time tPRWC ns Access Time from /RAS tRAC ns 4, 5, 6 Access Time from /CAS tCAC ns 4, 5 Access Time from Column Address tAA ns 4, 6 Access Time from /CAS Precharge tCPA ns Access Time from /OE tOEA ns Output Low Impedance Time from /CAS tCLZ ns /CAS to Data Output Buffer Turn-off Delay Time tOFF ns /OE to Data Output Buffer Turn-off Delay Time tOEZ ns Transition Time tT ns Refresh Period tREF ms /RAS Precharge Time tRP ns /RAS Pulse Width tRAS 10K 10K ns /RAS Pulse Width (Fast Page Mode) tRASP 100K 100K ns /RAS Hold Time tRSH ns /RAS Hold Time referenced to /OE tROH ns /CAS Precharge Time (Fast Page Mode) tCP ns /CAS Pulse Width tCAS 10K 10K ns /CAS Hold Time tCSH ns /CAS to /RAS Precharge Time tCRP ns /RAS Hold Time from /CAS Precharge tRHCP ns /RAS to /CAS Delay Time tRCD ns /RAS to Column Address Delay Time tRAD ns Row Address Set-up Time tASR ns Row Address Hold Time tRAH ns Column Address Set-up Time tASC ns Column Address Hold Time tCAH ns Column Address Hold Time from /RAS tAR ns Column Address to /RAS Lead Time tRAL ns

AC Characteristics (2/2) MSC23137D -60BS9/DS9 MSC23137D -70BS9/DS9 Parameter Symbol Min. Max. Min. Max. Unit Note Read Command Set-up Time tRCS ns Read Command Hold Time tRCH ns Read Command Hold Time referenced to /RAS tRRH ns Write Command Set-up Time tWCS ns Write Command Hold Time tWCH ns Write Command Hold Time from /RAS tWCR ns Write Command Pulse Width tWP ns /OE Command Hold Time tOEH ns Write Command to /RAS Lead Time tRWL ns Write Command to /CAS Lead time tCWL ns Data-in Set-up Time tDS ns Data-in Hold Time tDH ns Data-in Hold Time from /RAS tDHR ns /OE to Data-in Delay Time tOED ns /CAS to /WE Delay Time tCWD ns Column Address to /WE Delay Time tAWD ns /RAS to /WE Delay Time tRWD ns /CAS Precharge /WE Delay Time tCPWD ns /CAS Active Delay Time from /RAS Precharge tRPC ns /RAS to /CAS Set-up Time (/CAS before /RAS) tCSR ns /RAS to /CAS Hold Time (/CAS before /RAS) tCHR ns /WE to /RAS Precharge Time (/CAS before /RAS) tWRP ns /WE Hold Time from /RAS (/CAS before /RAS) tWRH ns /RAS to /WE Set-up Time (Test Mode) tWTS ns /RAS to /WE Hold Time (Test Mode) tWTH ns

Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. The AC characteristics assumes tT = 5ns. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are measured between VIH and VIL. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. tOFF(Max.) and tOEZ(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. tRCH or tRRH must be satisfied for a read cycle. tWCS, tCWD, tRWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(Min.), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD(Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD(Min.) and tCPWD ≥ tCPWD(Min.), the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither or the above sets of conditions is satisfied, the conditions of the data out (at access time) is indeterminate. 10. These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading edge in an /OE control write cycle or a read modify write cycle. 11. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA0 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by a /RAS only refresh or /CAS before /RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.