MSC2313258D OKI | Alldatasheet

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Technical content

1,048,576-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO This version: Feb. 23. 199 9

DESCRIPTION

The MSC2313258D-xxBS2/DS2 is a fully decoded, 1,048,576-word x 32-bit CMOS dynamic random access memory module composed of two 16Mb DRAMs in SOJ packages mounted with four decoupling capacitors on a 72-pin glass epoxy single-inline package. This module supports any application where high density and large capacity of storage memory are required.

FEATURES

  • 1,048,576-word x 32-bit organization
  • 72-pin socket insertable module MSC2313258D-xxBS2 : Gold tab MSC2313258D-xxDS2 : Solder tab
  • Single +5V supply ± 10% tolerance
  • Input : TTL compatible
  • Output : TTL compatible, 3-state
  • Refresh : 1024cycles/16ms
  • /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
  • Fast page mode capability PRODUCT FAMILY Access Time (Max.) Power Dissipation Family tRAC tAA tCAC Cycle Time (Min.) Operating(Max.) Standby(Max.) MSC2313258D-60BS2/DS2 60ns 30ns 15ns 104ns 1375mW MSC2313258D-70BS2/DS2 70ns 35ns 20ns 124ns 1265mW 11mW

R1.57 95.25 2.03Typ. 6.35Typ. Typ. 6.35 Typ. 10.16 /G28 3.18 19.0±0.2 101.19Typ. 107.95±0.2*1 3.38Typ. 6.0Min. 5.28Max. +0.1 -0.081.27 (Unit : mm)MSC2313258D-xxBS2/DS2 *1 The common size difference of the board width 12.5mm of its height is specified as ±0.2. The value above 12.5mm is specified as ±0.5.

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1V SS 19 NC 37 NC 55 DQ11

2 DQ0 20 DQ4 38 NC 56 DQ27

3 DQ16 21 DQ20 39 V SS 57 DQ12

4 DQ1 22 DQ5 40 /CAS0 58 DQ28

5 DQ17 23 DQ21 41 /CAS2 59 V CC

6 DQ2 24 DQ6 42 /CAS3 60 DQ29

7 DQ18 25 DQ22 43 /CAS1 61 DQ13

8 DQ3 26 DQ7 44 /RAS0 62 DQ30

9 DQ19 27 DQ23 45 NC 63 DQ14

10 V CC 28 A7 46 NC 64 DQ31

11 NC 29 NC 47 /WE 65 DQ15

12 A0 30 V CC 48 NC 66 NC

13 A1 31 A8 49 DQ8 67 PD1

14 A2 32 A9 50 DQ24 68 PD2

15 A3 33 NC 51 DQ9 69 PD3

16 A4 34 /RAS2 52 DQ25 70 PD4

17 A5 35 NC 53 DQ10 71 NC

18 A6 36 NC 54 DQ26 72 V SS

Pin No. Pin Name MSC2313258D -60BS2/DS2 MSC2313258D -70BS2/DS2

67 PD1 V SS VSS

68 PD2 V SS VSS

69 PD3 NC V SS

70 PD4 NC NC

/WE /CAS1 /CAS0 A0-A9 /CAS3 /CAS2 DQ0A0-A9 DQ1 DQ3 DQ2 DQ4 DQ5 /RAS /LCAS /UCAS DQ6 DQ1 DQ2 DQ3 VCC VSS C1-C4 DQ8 VSS /WE /OE VCC DQ4 DQ5 DQ6 DQ7 DQ7 DQ8DQ9 DQ11 DQ10 DQ12 DQ13 DQ14 DQ9 DQ10 DQ11 DQ16 DQ12 DQ13 DQ14 DQ15 DQ15 /RAS0 /RAS2 DQ16A0-A9 DQ1 DQ3 DQ2 DQ4 DQ5 /RAS /LCAS /UCAS DQ6 DQ17 DQ18 DQ19 DQ8 VSS /WE /OE VCC DQ20 DQ21 DQ22 DQ23 DQ7 DQ24DQ9 DQ11 DQ10 DQ12 DQ13 DQ14 DQ25 DQ26 DQ27 DQ16 DQ28 DQ29 DQ30 DQ31 DQ15

ELECTRICAL CHARACTERISTICS

( Ta = 25°C ) Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT -1.0 to +7.0 V Voltage on VCC Supply Relative to VSS VCC -1.0 to +7.0 V Short Circuit Output Current I OS 50 mA Power Dissipation P D 2W Operating Temperature T OPR 0 to +70 °C Storage Temperature T STG -40 to +125 °C Recommended Operat ing Conditions ( Ta = 0°C to +70°C ) Parameter Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V Power Supply Voltage VSS 000V Input High Voltage V IH 2.4 - 6.5 V Input Low Voltage V IL -1.0 - 0.8 V Capacitance ( VCC = 5V ± 10%, Ta = 25°C, f = 1 MHz ) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 - A9) C IN1 -2 1 p F Input Capacitance (/WE) C IN2 -2 0 p F Input Capacitance (/RAS0, /RAS2) C IN3 -1 3 p F Input Capacitance (/CAS0- /CAS3) C IN4 -1 3 p F I/O Capacitance (DQ0 - DQ31) C DQ -1 8 p F Note: Capacitance measured with Boonton Meter.

(VCC = 5V ± 10%, Ta = 0°C to +70°C ) MSC2313258D -60BS2/DS2 MSC2313258D -70BS2/DS2Parameter Symbo l Condition Min. Max. Min. Max. Unit Note Input Leakage Current I LI 0V ≤ VIN ≤ 6.5V: All other pins not under test = 0V -20 20 -20 20 µA Output Leakage Current I LO Data out is disable 0V ≤ VOUT ≤ 5.5V -10 10 -10 10 µA Output High Voltage V OH IOH = -5.0mA 2.4 V CC 2.4 V CC V Output Low Voltage V OL IOL = 4.2mA 0 0.4 0 0.4 V Average Power Supply Current (Operating) ICC1 /RAS cycling, /CAS cycling, t RC = min. - 250 - 230 mA 1, 2 T T L -4-4 m A 1Power supply current (Standby) ICC2 /RAS = VIH /CAS = VIH MOS - 2 - 2 mA 1 Average Power Supply Current (/RAS only refresh) ICC3 /RAS cycling, /CAS = VIH, tRC = min. - 250 - 230 mA 1, 2 Average Power Supply Current (/CAS before /RAS refresh) ICC6 tRC = min. - 250 - 230 mA 1, 2 Average Power Supply Current (Fast Page Mode) ICC7 /RAS = VIL, /CAS cycling, t PC = min. - 250 - 230 mA 1, 3 Notes: 1. ICC is dependent on output loading and cycles rates. Specified values are obtained with the output open. 2. Address can be changed once or less while /RAS = VIL. 3. Address can be changed once or less while /CAS = VIH.

AC Characteristics (1/2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Note: 1, 2, 3 MSC2313258D -60BS2/DS2 MSC2313258D -70BS2/DS2Parameter Symbol Min. Max. Min. Max. Unit Note Random Read or Write Cycle Time t RC 104 - 124 - ns Fast Page Mode Cycle Time t HPC 25 - 30 - ns Access Time from /RAS t RAC - 60 - 70 ns 4, 5, 6 Access Time from /CAS t CAC - 15 - 20 ns 4, 5 Access Time from Column Address t AA - 30 - 35 ns 4, 6 Access Time from /CAS Precharge t CPA - 35 - 40 ns 4 Output Low Impedance Time from /CAS t CLZ 0-0- n s 4 Data Output Hold After /CAS Low t DOH 5-5- n s /CAS to Data Output Buffer Turn-off Delay Time tCEZ 0 15 0 20 ns 7, 8 /RAS to Data Output Buffer Turn-off Delay Time tREZ 0 15 0 20 ns 7, 8 /WE to Data Output Buffer Turn-off Delay Time tWEZ 0 15 0 20 ns 7 Transition Time t T 1 50 1 50 ns 3 Refresh Period t REF -1 6-1 6 m s /RAS Precharge Time t RP 40 - 50 - ns /RAS Pulse Width t RAS 60 10K 70 10K ns /RAS Pulse Width (Fast Page Mode with EDO) t RASP 60 100K 70 100K ns /RAS Hold Time t RSH 10 - 13 - ns /CAS Precharge Time (Fast Page Mode with EDO) tCP 10 - 10 - ns /CAS Pulse Width t CAS 10 10K 13 10K ns /CAS Hold Time t CSH 40 - 45 - ns /CAS to /RAS Precharge Time t CRP 5-5- n s /RAS Hold Time from /CAS Precharge t RHCP 35 - 40 - ns /RAS to /CAS Delay Time t RCD 14 45 14 50 ns 5 /RAS to Column Address Delay Time t RAD 12 30 12 35 ns 6 Row Address Set-up Time t ASR 0-0- n s Row Address Hold Time t RAH 10 - 10 - ns Column Address Set-up Time t ASC 0-0- n s Column Address Hold Time t CAH 10 - 13 - ns Column Address to /RAS Lead Time t RAL 30 - 35 - ns Read Command Set-up Time t RCS 0-0- n s Read Command Hold Time t RCH 0-0- n s 9 Read Command Hold Time referenced to /RAS t RRH 0-0- n s 9

AC Characteristics (2/2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Note: 1, 2, 3 MSC2313258D -60BS2/DS2 MSC2313258D -70BS2/DS2Parameter Symbol Min. Max. Min. Max. Unit Note Write Command Set-up Time t WCS 0-0- n s Write Command Hold Time t WCH 10 - 13 - ns Write Command Pulse Width t WP 10 - 10 - ns /WE Pulse Width (DQ Disable) t WPE 10 - 10 - ns Write Command to /RAS Lead Time t RWL 10 - 13 - ns Write Command to /CAS Lead Time t CWL 10 - 13 - ns Data-in Set-up Time t DS 0-0- n s Data-in Hold Time t DH 10 - 13 - ns /CAS Active Delay Time from /RAS Precharge t RPC 5-5- n s /RAS to /CAS Set-up Time (/CAS before /RAS) tCSR 5-5- n s /RAS to /CAS Hold Time (/CAS before /RAS) tCHR 10 - 10 - ns

Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assumes tT = 2ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF. 5. Operation within the t RCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC . 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA . 7. tCEZ (Max.), tREZ (Max.) and tWEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle.