MSC23108C

MSC23108C OKI | Alldatasheet

Document overview

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Technical content

1,048,576-Word x 8-Bit DRAM MODULE : FAST PAGE MODE TYPE CC

DESCRIPTION

The OKI MSC23108C/CL-xxD82 is a fully decoded 1,048,576-word x 8-bit CMOS Dynamic Random Access Memory Module composed of two 4-Mb DRAMs (1M x 4) in SOJ packages mounted with two decoupling capacitors on a 30-pin glass epoxy single-inline package. This | module is generally used for non-parity memory expansion applications such as fax machines, printers and personal computers. The low-power version (CL) offers reduced power consumption | for mobile computing applications like laptops and palmtops.

FEATURES

° 1-Meg x 8-bit organization | + 30-Pin Socket Insertable Module MSC23108C/CL-xxDS2_: Solder tab 1 * Single 5 V supply 10% tolerance + Access times : 60, 70, 80 ns «Input : TTL compatible - * Output : TTL compatible, 3-state * Refresh ; 1024 cycles/16 ms (128 ms : L-version) * CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability * Multi-bit test mode capability + Fast Page Mode capability PRODUCT FAMILY : Cycle Ti Power Dissipation Famil ycle Time fon fm | trac | tea | toac | (Min) [Operating (Max)] Standby (Max) S208 60052 | Ons | Ons | 15s | 110s 14 mW/ wiscasrceGe.70082 | 70m | 36s | 200s | ro01s | 990 mW | ; }2.2 mW (L-version) | wiscasiaace-200s2 | ane | 40s | 2005 | 180s | 680 mW : 19 i

MSC23108C/CL-xxDS2 OXI Semiconductor MMSGOSOBC (Cb exxDS200 COKE Semiconductor PIN CONFIGURATION | MSC23108C/CL-xxDS2 | "4 5.28 Max. 88.9 0.2 | ty (IC ° | HW) 1 MOOOKONOA OOO MMOONANONAANONONNnAM 30 | [24 min. 73.66 “1 The common size difference of the board width 12.5 mm of its height is Pino. | PinName [| PinNo. | PinName || PinNo. | PinName 1 | | 2 pase as ess 3 oa | ee | ee 3 4 al | i 5 0 |< 4 eT | | eS | | | 7 RAS. ES | |) NC ES |S |< a | | 20 | I

| OKI Semiconductor MSG23108C/CL-xxDS2 QKESemiconductor MS 23108C/CL-xxDS2 BLOCK DIAGRAM AQ- AQ I AOQ-Ad Lie} a0 FAS RAS ba j|— oar = Lt le 8 [ee CAS CAS LOS fom We WE E | Vss v A0- Ad DQ ba4 cH ca |— par We oE Veo Vss | V Veo ct c2 i

MSC23108C/CL-xDS2 OKI Semiconductor OK Semiconductor | ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Rating Unit Voltage on Any Pin Relative to Vss 1.010 7.0 Vv | Voltage Voc Supply Relative to Ves ~1.0107.0 _ vo Short Circuit Output Current | los | 50 mA _Power Dissipation [Pp | 2 Ww Operating Temperature ___ 01070 c Storage Temperature [Toe | 40 to 125 °C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. | Recommended Operating Conditions (Ta=0°Cto 70°C) Parameter ee Unit [Veo | Power Supply Vonage Veo [45 [50 | vo [| vs [oo fo vo | input High Voltage Vi 65 Vv | Input Low Voltage Vie 08 Vv I Capacitance (Ta = 25°C, f= 1 MHz) | Parameter Symbol Typ. Unit | Input Capacitance (AO - AS) Cins - Fo j 'nput Capacitance (RAS, CAS, WE) = 20 oF i VO Capacitance (D00-007) | Coa__—| = 13 r | Note: Capacitance measured with Boonton Meter. | 2 |

OKI Semiconductor MSC23108C/CL-xxDS2 ——ueaaea M8 23108C/CL-xxDS2 DG Characteristics oc = 5 V 210%, Ta = 0°C 10 70°C) 1SC25106C/CL|MSC23108C/CLIMsc231080/CL] Parameter 60082 +70DS2 80082 Note OVsViS65V; Input Leakage Current | i: | All other pins not under test = 0V _ Dour disable Output Leakage Current} {Lo OV<Vos55V 10 10 | vA Guput gn Vorage | Vou lion=-50mi | 24 | Ver | 24] Veo | 24] Ye V Outbut Low Vonage iaed2ma | 0 [04 | 0] 04 yf 0 | 04] VI Average Power . Supply Current ie CHS cyl 12 (Operating) ___ : Power Supply [RAS CaS vin [| — [4 | — [a | — [a [malt | current (standby) magcas | — | 2 [2 | =e [ml Average Power BAS cycling, Supply Current CAS= Vin, 180 1,2 (RAS-only Refresh) tac = Min. ' Average Power RAS cycling, | Supply Current CHS before RAS, 180 160 1,2 (CAS betore RAS Refresh) tac = Min. Average Power RAS = Vit, Supply Current lec7 | TAS cycling, 13 ' (Fast Page Mode) tec = Min. j Average Power tac = 125 ys, 12 Supply Current TAS before - 600 ‘ 5 i (Battery Backup) BAS cycling . i Notes: 1. Specified values are obtained with the output open. i 2. Address can be changed once or less while RAS=Vj,. ' 3. Address can be changed once or less while CAS=Vjy. i 4. Voc-0.2VSVipS65V,-10VSVi_s02V. 5. L-version. | 23 :

MSC23108C/CL-xxDS2 OKI Semiconductor STOR SSTOBC ICE KDS2 KE Semiconductor AC Characteristics (1/2) (Voc =5 V 210%, Ta = 0°C to 70°C) Note 1,2,39,10 IMSC23108¢/CL|msc2s108c/cL[MSC23109C/CL| Parameter von on -70DS2 -80DS2 Note Random Read or Write Cycle Time [ tac [110 | = [130 — [150 | — | ns Fast Page Mode Cycle Time Rete Access Time from RAS: { trac | — | eo | — [ 7 | — | [ ns | 45,6 Access Time trom CAS | tea | — [is [= [20 | = | 20 [ns as Access Time from Column Address eS 4.6 Access Time from CAS Precharge [tera | — | 35 | — | ao | — | as | 4 Qutput Low Impedance Time trom CAS ee 4 Output Buffer Turn-ott Delay Time [torr [ 0 | 18 [0 | 20 | | 20 | ms | 7 Transition Time Re ms {3 Refresh Period | tar | — | te | — Pte | — | ms Refresh Period (L-version) a RAS Precharge Time [ tae [40 [| — | so [ — | 60 | _ | ns | — RAS Pulse Width [wes | 60_[ "10x [70 [10K [00 | fox [ns | FAS Pulse Width (Fast Page Mode) ee __ GAS Precharge Time ee TAS Pulse Width | 1s [tox [20 [tox | 20 | tox | CAS Hold Time [ tosn | 60 [ — | 70 | +2} =+ =] TAS to RAS Precharge Time Het Steet eT [ as | FIRS to GAS Delay Time | taco | 20 [ 45 [20 | 50 | 20 | 60 | ns] 5 RAS to Column Address Delay Time Hae ee es fe Pe Tos] 6 Row Address Set-up Time [sal 0 | —[o [—| 0 | Hey | Row Address Hold Time [tw | 30 | — [0 | = | to | — | Column Address Set-up Time [use| o | — | o [—|o | He \\ Column Address Hold Time [team | 15 | — | 1s | — [165 | Column Address Hold Time from RAS [wa | so | — [55 | — | 60 | [ ns | Column Address to RAS Lead Time [tem [90 | = [35 [| — | ao [ — [ne] _ i i i i 24 1

OKI Semiconductor MSC23108C/CL-xxDS2 OKI Semiconductor M2 3108C/CL-xxDS:2 AC Characteristics (2/2) (Vor = 5 V 10%, Ta = 0°C to 70°C) Note 1,2,3.9,10 ae awe ame Parameter -60DS2 -70DS2 -80DS2 Note Read Command Set-up Time [tas { o | —[ o{[—]|o]|—| i Read Command Hold Time pam f of =o ff oo f= fa 8 Read Command Hold Time referenced to RAS| tann | | —| o |—Tfo[—Tn| se Write Command Set-up Time fas} ofa fo tateta fe Write Command Hold Time | twow | 10 | — [io | — [to | = [as | Write Command Hold Time tromRAS | twoa | 45 | — | 50 | — | 60] — | ne | Write Command Pulse Width [wwe | to | — | 10 | — | 1 | — [as] ‘Write Command to RAS Lead Time [tam | 15 | — | 20 | — | 20 | — | ns Write CommandtoCASLeadTime | tom | 15 | — | 20 | — | 2{— [ns] Data-in Set-up Time [ ts | o | —[ oo | —T o [ — [rs Data-in Hold Time | tow | 6 | — Tos | [ts | = Ts | Data-in Hold Time from FAS [town | 50 | — | 55 | — | 60 | — | ns | ‘GAS Active Delay Time from RAS Precharge| tapc | 5 | — | 5 | — | 5 | — | ns| RAS to CAS Set-up Time (CAS before RAS)| tesa | 5 | — | 5 | — | 5 | — | 1s | FAS to GAS Hold Time (CAS betore RAS) Hoe of = fa [=o fo GAS Precharge Time (Refresh Counter Test) | teor |" 30 | — | +e t= ‘WE to RAS Precharge Time (CAS betoreFAS)| wap | 10 | — | 10 | — | 0] — | WE Hold Time from RAS (CAS beforeRAS) twa | 10 [| — | 10 | — | 10 | — | rs | RAS to WE Set-up Time (Test Mode! vw of — fof te tat ‘AS to WE Hold Time (Test Mode) | twm | 10 | — | 10 | — | 10 | — |

: MSC23108C/CL-»xxDS2 OKI Semiconductor ——EEemmmees COKE Semiconductor Notes: 1. A start-up delay of 200 us is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh or TAS before refresh) before Proper device operation is achieved. When using the internal refresh counter, a minimum of eight CAS before RAS initialization cycles is required. 2. AC mesurement assume tr = 5 ns. 3. Vin (Min.) and Vj_ (Max.) are reference levels for measuring input timing signals. Transition times are measured between Vip and Vj. 4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tacp (Max.) limit ensures that trac (Max.) can be met. tpcp (Max.) is specified asa reference point only. If tacpis greater than the specified tpcp (Max.) limit, access time is controlled by tcac. 6. Operation within the trap (Max.) limit ensures that trac (Max.) can be met. trap (Max.) is specified as a reference point only. If trap is greater than the specified trap (Max.) limit, access time is controlled by taa. 7. torr (Max.) defines the time at which the output achieves an open circuit condition and is not referenced to output voltage levels, 8. trcy or trry must be satisfied for a read cycle. 9. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. * This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CAO is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 10. Ina test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values. | See ADDENDUM E for AC Timing Waveforms