MSC1162A OKI | Alldatasheet

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¡ Semiconductor MSC1162A ¡ Semiconductor MSC1162A 40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver GENERAL DESCRIPTION The MSC1162A is a monolithic IC designed for directly driving the grid and anode of the vacuum fluorescent display tube. The device contains a 40-bit bidirectional shift register, a 40-bit latch circuit, and 40-output circuit on a single chip. Display data is serially stored in the shift register at the rising edge of a clock pulse. Setting the CL pin low allows all the driver outputs to be driven low, which makes it possible to set the display blanking. Also, setting both of the CL and CHG pins high allows all the driver outputs to be driven high, which provides the easy testing of all lights after final assembly of a VFD tube panel. The MSC1162A is compatible with the MSC1162.

FEATURES

  • Logic Supply Voltage (V CC): 5 V
  • Driver Supply Voltage (V HV): 65V
  • Driver Output Current IOHVH1 (Only one driver output : "H") : –40mA IOHVH2 (All the driver outputs : "H") : –2mA IOHVL:1mA
  • Directly connected to VFD tube without pull-down resistors
  • Data Transfer Speed: 4MHz
  • Package : 60-pin plastic SSOP (SSOP60-P-700-0.65-BK) (Product name : MSC1162AGS-BK) E2C0034-27-Y5 This version: Nov. 1997 Previous version: Jul. 1996

¡ Semiconductor MSC1162A BLOCK DIAGRAM VHV VCC CL VCC CHG LS DIN CLK GND1 GND2 HVO1 CS I PO1 PO2 O-1 O-2 I-1 I-2 PO40 O-40 I-40 SO HVO2 HVO40 DOUT 40-Bit Bi- directional Shift Register 40-Bit Latch

¡ Semiconductor MSC1162A INPUT AND OUTPUT CONFIGURATION Schematic Diagrams of Logic portion Input/Output Circuits and Driver Output Circuits Input Pin Output Pin VCC VCC INPUT GND1 GND2 VCC VCC DOUT GND2 GND1

¡ Semiconductor MSC1162A Driver Output Circuit GND 1 GND 1 Output VHV VHV

¡ Semiconductor MSC1162A PIN CONFIGURATION (TOP VIEW) HVO 1 HVO 2 HVO 3 HVO 4 HVO 5 HVO 6 HVO 7 HVO 8 HVO 9 HVO 10 HVO 11 HVO 12 HVO 13 HVO 14 HVO 15 HVO 16 HVO 40 HVO 39 HVO 38 HVO 37 HVO 36 HVO 35 HVO 34 HVO 33 HVO 32 HVO 31 HVO 30 HVO 29 HVO 28 HVO 27 HVO 26 HVO 25 HVO 17 HVO 18 HVO 19 HVO 20 HVO 24 HVO 23 HVO 22 HVO 21 V HV GND 1 GND 2 CL NC LS VHV GND 1 GND 2 NC CHG NC NC R/L DIN V CC CLK NC DOUT VCC /,/#01/#03/#04 NC : No-connection pin 60-Pin Plastic SSOP

¡ Semiconductor MSC1162A PIN DESCRIPTION Symbol Description CLK Shift register clock input pin. Shift register reads data through DIN while the CLK pin is low state and the data in the shift register is shifted from one stage to the next stage at the rising edge of the clock. Type I Serial data input pin of the shift register. Display data (positive logic) is input in through the DIN pin synchronization with clock.DIN I Serial data output pin of the shift register. Data is output through the DOUT pin in synchronization with the CLK signal. When R/L = High, the data of PO40 in the shift register is output through the DOUT pin. When R/L = Low, the data of PO1 pin in the shift register is output through the DOUT pin. DOUT O Latch strobe input pin When LS is high, the parallel output data (PO1-40) of the shift register read out. When LS goes from high to low, the parallel output data (PO1-40) of the shift register is held. LS I Clear input pin with a built-in pull-up resistor The CL pin is normally being set high. If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in phase with the corresponding latch outputs (O1 to O40). If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high irrespective of the states of the latch outputs. If the CL pin is set low, the driver outputs are driven low irrespective of the states of the CHG pin and latch outputs. This allows display blanking to be set. CL I Input for testing (with a pull-down resistor) The CL pin is normally being set low. If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV40) are in phase with the corresponding latch outputs (O1 to O40). If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV40) are low irrespective of the states of the latch outputs. If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the latch outputs. This provides the easy testing of all lights after final assembly. CHG I High voltage driver outputs for driving VFD tube The driver outputs are in phase with the corresponding latch outputs (O1 to O40). The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors. VHO1-40 O Power supply pin for driver circuits of VFD tubeVHV Power supply pin for logicVCC GND pin for driver circuits of a VFD tube. (D-GND) Since the GND1 is not be connected to L-GND, connect this pin to the external L-GND.GND1 GND pin for the logic circuits. (L-GND) Since the GND2 pin is not be connected to D-GND, connect this pin to the external D-GND.GND2

¡ Semiconductor MSC1162A ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Applicable to logic supply pinLogic Supply Voltage V CC –0.3 to +6.5 V Applicable to driver supply pinDriver Supply Voltage V HV –0.3 to +70 V Applicable to all input pinsInput Voltage V IN –0.3 to VCC +0.3 V Applicable to data output pinOutput Voltage V O –0.3 to VCC +0.3 V Driver Driving Frequency f DRV 0 to 15 kHzApplicable to driver output pin 860Power Dissipation P D mWTa £ 25°C Package Thermal Resistance Rj-a 145 °C/WTa > 25°C Storage Temperature T STG –55 to +150 °C— *1, *2 Withstand Output Voltage *1, *2 VHVO –0.3 to VHV +0.3 VApplicable to driver output pin Notes: *1 Maximum Supply Voltage with respect to L-GND and D-GND *2 Permanent damage may be caused if the voltage is supplied over the rating value. *3 Package Thermal Resistance (between junction and ambient) The junction temperature (Tj) expressed by the equation indicated below should not exceed 150°C. T j=P · Rj–a+Ta (P: Maximum power consumption)

¡ Semiconductor MSC1162A RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Max. Unit Applicable to logic supply voltage pinLogic Supply Voltage V CC 5.5 V Min. 4.5 —V3.6 Applicable to driver supply voltage pinDriver Supply Voltage V HV 65 V10 1.1 V— High Level Input Voltage V IH Low Level Input Voltage V IL High Level Driver Output Current Only one output is highIOHVH1 –40 mA— IOHVH2 –2 mA— CLK Frequency f CLK 4 MHz— CLK Pulse Width tw (CLK) —n s75 Data Setup Time t SU(D-CLK) —n s80 Data Hold Time th (CLK-D) —n s50 CLK-LS tsu (CLK-LS) —n s50 LS-CLK tsu (LS-CLK) —n s0 LS-CHG tsu (LS-CHG) — ms0 LS-CL tsu(LS-CL) — ms0 Pulse Width tw(CHG) — ms2 —tw(CL) — ms2 —Operating Temperature T op 85 °C–40 Low Level Driver Output Current Applicable to all driver output pinsIOHVL 1m A— Applicable to all input pins Applicable to all input pins All outputs are high Applicable to driver output pin Data Pulse Width tw (D) 140 —n s Latch Probe Pulse Width tw (LS) 80 —n s Setup Time See timing diagram CHG CL

¡ Semiconductor MSC1162A

ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition Max. Unit All input: Low Logic Supply Current ICC1 6.65 mA Typ. 4.3 All input: High, Ta=25°CICC2 Min. No load VCC=5.5V 1.00.5— All input: Low Driver Supply Current IHV1 1.0 mA All input: High Ta=25°CIHV2 No load VCC=5.5V 3.82.45 mA VCC=5.5V, VIN=5.5V Inputs excluding CHG 1—–1 mA High Level Input Current IIH Ta=25°CInput Capacitance C I —p F15— VCC=4.5V — —3.5 V VCC=5.5V — —4.5 V High Level Data Output Voltage VODH VCC=4.5V 1.1 —— V VCC=5.5V 1.1 —— V Low Level Data Output Voltage VODL IOH=–0.1mA IOL=0.1mA High Level Driver Output Voltage IOH=–40mAVOHVH1 —V—VHV–4 Low Level Driver Output Voltage IOL=1mAVOHVL 3.0 V—— (VCC=4.5 to 5.5V, VHV=10 to 65V, Ta=–40 to +85°C) VCC=5.5V, VIN=5.5V CHG input 80—5 mA VCC=5.5V, VIN=0V Inputs excluding CL 1—–1 mA Low Level Input Current IIL VCC=5.5V, VIN=0V CL input –80—–5 mA IOH=–2mA —V—VHV–4VOHVH2 AC Characteristics Parameter Symbol Condition Max. Unit Typ.Min. —CLK-DOUT Delay Time t PD 300 ns—— —Delay Time Low to High t DLH 1.0 ms0.3— (VCC=5V, VHV=65V, Ta=25°C) —Transit Time Low to High t TLH 5.0 ms2.0— —Delay Time High to Low t DHL 1.0 ms0.3— —Transit Time High to Low t THL 5.0 ms2.0—

¡ Semiconductor MSC1162A TIMING DIAGRAM 1/fCLK CLK DIN LS HVO (OTHERS) CL HVO (1, 2, 39, 40) CHG DOUT T1/2 T3/4 T39/40 T1/2 T3/4 tw(CLK)th(CLK-D)tsu(D-CLK) tw(D) tPD tPD tsu(CLK-LS) tw(LS) tsu(LS-CHG) tsu(LS-CL) tw(CL) tw(CL) tDLH tDLH tTLH tsu(LS-CLK) tw(CHG) tw(CHG) tDHL tDHL tTLH tTHL tTHL

¡ Semiconductor MSC1162A FUNCTIONAL DESCRIPTION Function Table Shift register Input Shift Register Parallel Out Output CLK R/L DIN PO1 PO39 PO2 PO40 DOUT X X Not changed H L L PO38n PO1n PO39n PO40 H H H PO38n PO1n PO39n PO40 L L PO2n PO40n PO3n L PO1 L H PO2n PO40n PO3n H PO1 Not changed X: Don't Care PO1n to PO40n : PO1 to PO40 data just before CLOCK rises. Latch Input Shift Register Parallel Out Latch Output LS POm Om I X Not changed HL L HH H X: Don't Care, m: 1 to 40 Driver output Input Driver Output CL Om HVOm LX L HX H HL L X: Don't Care, m: 1 to 40 HH H Latch Output CHG X H L L

¡ Semiconductor MSC1162A NOTES ON USE 1. Connect GND1 to GND2 externally to be an equal potential voltage. 2. The contents of the shift register are undefined when the power is applied. Therefore, unnecessary driver outputs may be driven high just after power-on, and the VFD tube may flicker. To avoid this, follow the procedures: 1) Apply the driver power supply after applying the logic power supply, with the CL pin remained low. 2) Start displaying by setting the CL pin high after in putting display data the shift register through the DIN pin.

¡ Semiconductor MSC1162A Test circuit 65V 5.0V DIN DOUT 30pF CLK LS R/L CHG GND1, 2 CL HVO40 HVO1 HVO2 20pF 1.5kW VCC VHV

¡ Semiconductor MSC1162A (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). SSOP60-P-700-0.65-BK Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.21 TYP. Mirror finish