MS82V16520

MS82V16520 OKI | Alldatasheet

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¡ Semiconductor MS82V16520

DESCRIPTION

The MS82V16520 is a synchronous graphics random access memory organized as 256 K words ´ 32 bits ´ 2 banks. This device can operate up to 143 MHz by using synchronous interface. In addition, it has 8-column Block Write function and Write per bit function which improves performance in graphics systems.

FEATURES

262,144 words ´ 32 bits ´ 2 banks memory
Single 3.3 V –0.3 V power supply
LVTTL compatible inputs and outputs
All input signals are latched at rising edge of system clock
Auto precharge and controlled precharge
Internal pipelined operation: column address can be changed every clock cycle
Dual internal banks controlled by A10 (Bank Address: BA)
Independent byte operation via DQM0 to DQM3
8-column Block Write function
Persistent write per bit function
Programmable burst sequence (Sequential/Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable CAS latency (2, 3)
Burst stop function (full-page burst)
Power Down operation and Clock Suspend operation
Auto refresh and self refresh capability
2,048 refresh cycles/32 ms
Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (Product : MS82V16520-xGA) x indicates speed rank. PRODUCT FAMILY ¡ Semiconductor MS82V16520 262,144-Word ´ 32-Bit ´ 2-Bank Synchronous Graphics RAM Family 100-pin Plastic QFP (14 ´ 20 mm) Clock Frequency MHz (Max.) Package MS82V16520-8 125 MS82V16520-7 143 E2L1056-39-72 This version: Jul. 1999 Previous version: Sep. 1998

¡ Semiconductor MS82V16520 PIN CONFIGURATION (TOP VIEW) DQ3 100-Pin Plastic QFP VCCQ 2 DQ4 3 DQ5 4 VSSQ 5 DQ6 6 DQ7 7 VCCQ 8 DQ16 9 DQ17 10 VSSQ 11 DQ18 12 DQ19 13 VCCQ 14 VCC 15 VSS 16 DQ20 17 DQ21 18 VSSQ 19 DQ22 20 DQ23 21 VCCQ 22 DQM0 23 DQM2 24 WE 25 CAS 26 RAS 27 CS 28 BA (A10) 29 A8 30 DQ28 VCCQ DQ27 DQ26 V SSQ DQ25 DQ24 V CCQ DQ15 DQ14 VSSQ DQ13 DQ12 V CCQ VSS VCC DQ11 DQ10 V SSQ DQ9 DQ8 VCCQ NC DQM3 DQM1 CLK CKE DSF NC A9 (AP) A0 31 A1 32 A2 33 A3 34 VCC 35 NC 36 NC 37 NC 38 NC 39 NC 40 NC 41 NC 42 NC 43 NC 44 NC 45 VSS 46 A4 47 A5 48 A6 49 A7 50 DQ2 V SSQ DQ1 DQ0 V CC NC NC NC NC NC NC NC NC NC NC V SS DQ31 DQ30 V SSQ DQ29 100 /#01/#02/#04/#05 Pin Name Function Pin Name Function A0 - A10 Address Inputs DQM0 - DQM3 DQ Mask Enable A0 - A9 Row Address Inputs DSF Special Function Enable A0 - A7 Column Address Inputs CKE Clock Enable BA (A10) Bank Address CLK System Clock Input DQ0 - DQ31 Data Inputs/Outputs VCC Supply Voltage CS Chip Select VSS Ground RAS Row Address Strobe VCCQ Supply Voltage for DQ CAS Column Address Strobe VSSQ Ground for DQ WE Write Enable NC No Connection Note: The same power supply voltage must be provided to every V CC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin.

¡ Semiconductor MS82V16520 BLOCK DIAGRAM DQ0 to 31 DQM0 to 332 A10 Address Buffers Column Decoders Sense Amplifiers 8Mb Memory Cells Bank - A Row Decoders Column Decoders Sense Amplifiers 8Mb Memory Cells Bank - B Refresh Counter I/O Buffers Color Register (32 bits) Mask Register (32 bits) Row Decoders CLK CKE CS RAS CAS WE DSF VCC/VCCQ VSS/VSSQ Timing Generator

¡ Semiconductor MS82V16520 PIN DESCRIPTION *Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0, DQM1, DQM2, and DQM3 are invalid. 2. When issuing an active, read or write command, the bank is selected by BA (A10). 3. The auto precharge function is enabled or disabled by the A9 input when the read or write command is issued. BA (A10) Active, read or write Bank A Bank B Operation After the end of burst, bank A holds the active status. BA 0 After the end of burst, bank B holds the active status.1 After the end of burst, bank A is precharged automatically. After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A9 and BA (A10) inputs. BA X Operation Bank A is precharged. Bank B is precharged. Both banks A and B are precharged. CLK Fetches all inputs at the "H" edge. CKE Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Row & column multiplexed. Row address: RA0 – RA9 Column address: CA0 – CA7 RAS CAS WE Functionality depends on the combination. For details, see the function truth table. DQM0 - DQM3 Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal. Address DQi Data inputs/outputs are multiplexed on the same pin. CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0, DQM1, DQM2 and DQM3. Selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. BA = "L" : Bank A, BA = "H" : Bank B BA (A10) DSF DSF is part of the inputs of graphics command of the MS82V16520. If DSF is inactive (Low level), MS82V16520 operates just like SDRAM.

¡ Semiconductor MS82V16520 COMMAND OPERATION Mode Register Set Command (CS, RAS, CAS, WE, DSF = "Low") The MS82V16520 has the mode register that defines the operation mode " CAS Latency, Burst Length, Burst Sequence". The mode register is composed of eleven bits of memories corresponding to address inputs A0 - A9 and BA. The Mode Register Set command should be executed just after the M S82V16520 is powered on. Before entering this command, all banks must be precharged. Next command can be issued after t RSC. Special Mode Register Set Command ( CS, RAS, CAS, WE = "Low", DSF = "High") The MS82V16520 has the 32-bit color register for block write operation and the 32-bit mask register for write per bit operation. The Special Mode Register Set command performs loading mask register or color register. When A5 is "high", The mask data presented on the DQ0 - DQ31 is latched into the mask register. When A6 is "high", The color data presented on the DQ0 - DQ31 is latched into the color register. The Special Mode Register Set command must be executed before Masked Block Write and Write Per Bit operations. Next command can be issued after t RSC. Auto Refresh Command (CS, RAS, CAS, DSF = "Low", WE, CKE = "High") The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be performed 2048 times within 32 ms and the next command can be issued after t RC from last Auto Refresh command. Before entering this command, all banks must be precharged. Self Refresh Entry/Exit Command ( CS, RAS, CAS, DSF, CKE = "Low", WE = "High") The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left "low". This operation terminates by making CKE level "high". The self refresh operation is performed automatically by the internal address counter on the MS82V16520 chip. In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be precharged. Next command can be issued after t RC. Single Bank Precharge Command ( CS, RAS, WE, DSF, A9 = "Low", CAS = "High") The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA. All Banks Precharge Command (CS, RAS, WE, DSF = "Low", CAS, A9 = "High") The All Bank Precharge command triggers precharge of both bank A and bank B.

¡ Semiconductor MS82V16520 Bank Active and Masked Write Disable Command ( CS, RAS, DSF = "Low", CAS, WE = "High") The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A9 and BA" are strobed. After this command, the write command and block write command for that bank works as the no write per bit operation. Bank Active and Masked Write Enable Command ( CS, RAS = "Low", CAS, WE, DSF = "High") The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A9 and BA" are strobed. After this command, the write command and block write command for that bank works as the write per bit operation. Write Command (CS, CAS, WE, DSF, A9 = "Low", RAS = "High") The Write command is required to begin burst write operation. Then burst access initial bit column address is strobed. Write with Auto Precharge Command ( CS, CAS, WE, DSF = "Low", RAS, A9 = "High") The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after the burst write. Any command that interrupts this operation cannot be issued. Masked Block Write Command ( CS, CAS, WE, A9 = "Low", RAS, DSF = "High") The Masked Block Write command is required to begin block write operation with column mask. The masked block write operation performs writing in the 8 memory cells selected by column addresses "A3 - A7". In this operation, data in color register is written to memory cells with the column mask functions. At the same time, this command can perform write per bit operation. The block write operation is not bursted.

¡ Semiconductor MS82V16520 1DQ0

8 Column ´ 8 DQ

Note : Location "*" can not be loaded. Color Register I/O Mask Column Mask 11001110 11111010 10010011 Column 7 Column 6 Column 5 Column 4 Column 3 Column 2 Column 1 Column 0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Remark: 1. This diagram shows only for DQ0 - 7. The other DQ is similar as this. Column Mask DQ0 - 7 : Column Mask for DQ0 - 7 DQ8 - 15 : Column Mask for DQ8 - 15 DQ16 - 23: Column Mask for DQ16 - 23 DQ24 - 31: Column Mask for DQ24 - 31 Write per Bit Mask data = Mask Register + DQMi DQMi is prior to data of Mask Register. Block Write Function

¡ Semiconductor MS82V16520 Masked Block Write with Auto Precharge Command ( CS, CAS, WE = "Low", RAS, DSF, A9 = "High") The Masked Block Write with Auto Precharge command performs precharging at the bank selected by BA automatically after Masked Block Write. Read Command (CS, CAS, DSF, A9 = "Low", RAS, WE = "High") The Read command is required to begin burst read operation. Then burst access initial bit column address is strobed. Read with Auto Prechaege Command ( CS, CAS, DSF = "Low", RAS, WE, A9 = "High") The Read with Auto Precharge command is required to begin burst read operation with auto precharge after the burst read. Any command that interrupts this operation cannot be issued. No Operation Command (CS = "Low", RAS, CAS, WE = "High") The No Operation command does not trigger any operation. Device Deselect Command (CS = "High") The Device Deselect command disables the RAS, CAS, WE, DSF and Address input. This command does not trigger any operation. Data Write/Output Enable Command (DQMi = "Low") The Data Write/Output Enable command enables DQ0 - DQ31 in read or write. The each DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31 respectively. Data Mask/Output Disable Command (DQMi = "High") The Data Mask/Output Disable command disables DQ0 - DQ31. In read cycle output buffers are disabled after 2 clocks . In write cycle input buffers are disabled at the same clock. The each DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31 respectively. Burst Stop Command (CS, WE, DSF = "Low", RAS, CAS = "High") The Burst Stop command stops burst access when the access is in full page. After the Burst Stop command is entered, the output buffer goes into high impedance state.

¡ Semiconductor MS82V16520 TRUTH TABLE Command Truth Table DQM Truth Table Function DQMi Data Write/Output Enable L Data Mask/Output Disable H Function CS RAS CAS WE DSF Address A10 A9 A7 - A0 No Operation L H H H ´´´´ Burst Stop in Full Page L H H L L ´´´ Read L H L H L BA L CA Read with Auto Precharge L H L H L BA H CA Write L H L L L BA L CA Write with Auto Precharge L H L L L BA H CA Masked Block Write L H L L H BA L CA Masked Block Write with Auto Precharge LHLLH B A H C A Bank Activate L L H H L BA RA (A8 - A0) Bank Activate with WPB Enable L L H H H BA RA (A8 - A0) Precharge Select Bank L L H L L BA L ´ Precharge All Banks L L H L L ´ H ´ Mode Register Set L L L L L OP. CODE Special Register Set L L L L H OP. CODE

¡ Semiconductor MS82V16520 Function Truth Table (1/5) Current State CS RAS CAS WE DSF Address Note Action Idle H ´´´´ ´ NOP or Power Down LHHH ´´ NOP or Power Down LHHLH ´ ILLEGAL LHHLL ´ 2ILLEGAL LHLHH ´ ILLEGAL L H L H L BA, CA, AP 2 ILLEGAL L H L L H BA, CA, AP 2 ILLEGAL L H L L L BA, CA, AP 2 ILLEGAL L L H H H BA, RA Row Active with WPB L L H H L BA, RA Row Active LLHLH ´ ILLEGAL L L H L L BA, AP 3 NOP LLLHH ´ ILLEGAL LLLHL ´ 4Auto Refresh/Self refresh L L L L H Op-Code Special Register Write LLLLL Op-Code Mode Register Write Row Active (ACT) LHHH ´´ NOP LHHLH ´ ILLEGAL LHHLL ´ 2ILLEGAL LHLHH ´ ILLEGAL L H L H L BA, CA, AP Read L H L L H BA, CA, AP Block Write L H L L L BA, CA, AP Write L L H H H BA, RA 2 ILLEGAL L L H H L BA, RA 2 ILLEGAL LLHLH ´ ILLEGAL L L H L L BA, AP Precharge LLLHH ´ ILLEGAL LLLHL ´ ILLEGAL L L L L H Op-Code Special Register Write LLLLL Op-Code ILLEGAL Note 1

¡ Semiconductor MS82V16520 Current State CS RAS CAS WE DSF Address Note Action Read (RD) H ´´´´ ´ NOP (Continue Row Active after Burst ends) LHHH ´´ NOP (Continue Row Active after Burst ends) LHHLH ´ ILLEGAL LHHLL ´ 1, 2, 4, 8 Burst Length; ILLEGAL Full Page Burst; Burst Stop ® Bank Active LHLHH ´ ILLEGAL L H L H L BA, CA, AP Term Burst, new Read L H L L H BA, CA, AP Term Burst, start Block Write L H L L L BA, CA, AP Term Burst, start Write L L H H H BA, RA ILLEGAL L L H H L BA, RA ILLEGAL LLHLH ´ ILLEGAL L L H L L BA, AP Term Burst, execute Row Precharge LLLHH ´ ILLEGAL LLLHL ´ ILLEGAL L L L L H Op-Code ILLEGAL L L L L L Op-Code ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) ILLEGAL 1, 2, 4, 8 Burst Length; ILLEGAL Full Page Burst; Burst Stop ® Row Active ILLEGAL Term Burst, start Read Term Burst, new Block Write Term Burst, new Write ILLEGAL ILLEGAL ILLEGAL Term Burst, execute Row Precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL Write/Block Write (WT/BW) LHHH ´´ LHHLH ´ LHHLL ´ LHLHH ´ L H L H L BA, CA, AP L H L L H BA, CA, AP L H L L L BA, CA, AP L L H H H BA, RA 2 L L H H L BA, RA 2 LLHLH ´ L L H L L BA, AP LLLHH ´ LLLHL ´ L L L L H Op-Code L L L L L Op-Code Note 1 Function Truth Table (2/5)

¡ Semiconductor MS82V16520 Current State CS RAS CAS WE DSF Address Note Action Read with Auto Precharge (RAP) LHHH ´´ LHHLH ´ LHHLL ´ LHLHH ´ L H L H L BA, CA, AP L H L L H BA, CA, AP L H L L L BA, CA, AP L L H H H BA, RA 2 L L H H L BA, RA 2 LLHLH ´ L L H L L BA, AP 2 LLLHH ´ LLLHL ´ L L L L H Op- Code L L L L L Op- Code Note 1 NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Write/Block Write with Auto Precharge (WAP/BWAP) LHHH ´´ LHHLH ´ LHHLL ´ LHLHH ´ L H L H L BA, CA, AP L H L L H BA, CA, AP L H L L L BA, CA, AP L L H H H BA, RA 2 L L H H L BA, RA 2 LLHLH ´ L L H L L BA, AP 2 LLLHH ´ LLLHL ´ L L L L H Op- Code L L L L L Op- Code NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Function Truth Table (3/5)

¡ Semiconductor MS82V16520 Current State CS RAS CAS WE DSF Address Note Action Precharging (PRE) NOP ® Idle after t RP LHHH ´´ NOP ® Idle after tRP LHHLH ´ ILLEGAL LHHLL ´ ILLEGAL LHLHH ´ ILLEGAL L H L H L BA, CA, AP ILLEGAL L H L L H BA, CA, AP ILLEGAL L H L L L BA, CA, AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP ® Idle after t RP ILLEGAL ILLEGAL Special Register Write ILLEGAL L L H H H BA, RA L L H H L BA, RA LLHLH ´ L L H L L BA, AP LLLHH ´ LLLHL ´ L L L L H Op-Code L L L L L Op-Code Note 1 Refreshing (REF) LHHH ´´ NOP ® Idle after tRC LHHLH ´ ILLEGAL LHHLL ´ ILLEGAL LHLHH ´ ILLEGAL ILLEGAL ILLEGAL ILLEGAL L H L H L BA, CA, AP L H L L H BA, CA, AP L H L L L BA, CA, AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL L L H H H BA, RA L L H H L BA, RA LLHLH ´ L L H L L BA, AP LLLHH ´ LLLHL ´ L L L L H Op-Code LLLLL Op-Code Function Truth Table (4/5)

¡ Semiconductor MS82V16520 Current State CS RAS CAS WE DSF Address Note Action NOP NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Mode Register Access (MRA) LHHH ´´ LHHLH ´ LHHLL ´ LHLHH ´ L H L H L BA, CA, AP L H L L H BA, CA, AP L H L L L BA, CA, AP L L H H H BA, RA L L H H L BA, RA LLHLH ´ L L H L L BA, AP LLLHH ´ LLLHL ´ L L L L H Op-Code L L L L L Op-Code Note 1 Special Mode Register Access (SMRA) LHHH ´´ NOP LHHLH ´ ILLEGAL LHHLL ´ ILLEGAL LHLHH ´ ILLEGAL ILLEGAL ILLEGAL ILLEGAL L H L H L BA, CA, AP L H L L H BA, CA, AP L H L L L BA, CA, AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL L L H H H BA, RA L L H H L BA, RA LLHLH ´ L L H L L BA, AP LLLHH ´ LLLHL ´ L L L L H Op-Code L L L L L Op-Code Function Truth Table (5/5) Notes: 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. NOP to bank precharging or in idle state. Precharges activated bank by BA or AP. 4. Illegal if any bank is not idle. ABBREVIATIONS RA = Row Address BA = Bank Address NOP = No OPeration command CA = Column Address AP = Auto Precharge ´ = High or Low level (Don't care)

¡ Semiconductor MS82V16520 Function Truth Table for CKE Current State (n) CKEn-1 Address LH ´´´ ´ L LHHH ´ LL H H L ´ LL H L ´´ LL L ´´ ´ LH ´´´ ´ L LHHH ´ LL H H L ´ LL H L ´´ LL L ´´ ´ HH ´´´ ´ H LHHH ´ HL H H L ´ HL H L ´´ HL L H L ´ HL L L H ´ L Self Refresh (SREF) Power Down (PD) All Banks Idle Any State Other Action INVALID Exit Self Refresh ® ABI Exit Self Refresh ® ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down ® ABI Exit Power Down ® ABI ILLEGAL ILLEGAL ILLEGAL NOP (Continue power down mode) Refer to Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh Refer to Operations in Table Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension CKEn H H H H H L H H H H H L H L L L L L L H L H L (ABI) than Listed Above H LLLL ´ ILLEGALL L Note CS RAS CAS WE DSF Notes: 5. If the minimum set-up time t PDE is satisfied when CKE transitions from "L" to "H", CKE operates asynchronously so that a command can be input in the same internal clock cycle. 6. Power-down and self refresh can be entered only when all the banks are in an idle state.

¡ Semiconductor MS82V16520 Mode Set Address Keys Special Mode Set Address Keys Note : If LC and LM are both high (1), data of Mask and Color register will be unknown. POWER ON SEQUENCE 1. With CKE = "H", DQM = "H" and the other inputs in NOP state, turn on the power supply and start the system clock. 2. After the V CC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply an Auto-refresh 2 or more times. 5. Enter the mode register setting command. LC LM Load Color (LC) Function A5 Load Mask (LM) Function Disable Disable Enable Enable A10 ´ : Don't care A6 A5 A4 CL A3 BT A2 A1 A0 BT = 0 BT = 1 CAS Latency (CL) Burst Type (BT) Burst Length (BL) TMA7A8 Mode Setting00 Vender10 Use01 Burst0 Single Bit1 LengthA9 Operation Code Write Burst Length

000 Reserved 0 Sequential 000 1 Reserved

001 1 Interleave 001 2 Reserved 010 010 4 4 011 011 8 8

100 Reserved 100 Reserved Reserved

101 Reserved 101 Reserved Reserved

110 Reserved 110 Reserved Reserved

111 Reserved 111 Full Page Reserved

¡ Semiconductor MS82V16520 Burst Length and Sequence BL = 2 Starting Address Sequential Type Interleave Type(column address A0, binary) 0 0, 1 Not supported 1 1, 0 Not supported BL = 4 Starting Address Sequential Type Interleave Type(column address A1 - A0, binary) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 BL = 8 Starting Address Sequential Type Interleave Type(column address A2 - A0, binary) BL = Full : Sequential only

¡ Semiconductor MS82V16520 PRECHARGE Read Interrupted by Precharge Number of valid data after precharge : 1, 2 for CL = 2, 3 respectively. 012345678 BL = 4 (tRAS is satisfied) CLK Hi-ZDQ CL = 2 RD PRE DQ CL = 3 RD PRE Hi-Z Q2 Q3 Q4Q1 Q2 Q3 Q4Q1

¡ Semiconductor MS82V16520 AUTO PRECHARGE Read with Auto Precharge 012345678 BL = 4 (tRAS is satisfied) CLK Hi-ZDQ CL = 2 RAP DQ CL = 3 RAP Hi-Z Auto precharge starts Auto precharge starts Q2 Q3 Q4Q1 Q2 Q3 Q4Q1

¡ Semiconductor MS82V16520 Write with Auto Precharge 012345678 BL = 4 (tRAS is satisfied) CLK Hi-ZDQ CL = 2 WAP DQ CL = 3 WAP Hi-Z Auto precharge starts Auto precharge starts D2 D3 D4D1 D2 D3 D4D1 Block Write with Auto Precharge 012345 (tRAS is satisfied) CLK Hi-ZDQ CL = 2 DB BWAP DQ CL = 3 BWAP Hi-Z Auto precharge starts Auto precharge starts tBWC DB

¡ Semiconductor MS82V16520 READ/WRITE COMMAND INTERVAL Read to Read Command Interval 012345678 BL = 4, CL = 2 Hi-Z CLK DQ QB1 QB2 QB3 QB4 RD-A RD-B QA1 1 cycle Write to Write Command Interval 012345678 BL = 4, CL = 2 Hi-Z CLK DQ DB1 DB2 DB3 DB4 WT-A WT-B DA1 1 cycle

¡ Semiconductor MS82V16520 Write to Read Command Interval 012345678 BL = 4 CLK DQ CL = 2 DQ CL = 3 1 cycle Hi-Z QB2 QB3 QB4 WT-A RD-B QB1DA1 Hi-Z QB2 QB3 QB4 WT-A RD-B QB1DA1

¡ Semiconductor MS82V16520 Block Write to Write/Block Write Command Interval Block Write to Read Command Interval 012345678 Hi-Z CLK DQ BW-A DBDA BW-B CL = 2 tBWC DQ BW-A DB1 DB2 DB3 DB4DA WT-B BL = 4, CL = 2 tBWC 012345678 CLK DQ CL = 2 DQ CL = 3 Hi-Z BW-A QB2 QB3 QB4QB1DA RD-B tBWC Hi-Z BW-A QB2 QB3 QB4QB1DA RD-B tBWC

¡ Semiconductor MS82V16520 Read to Write/Block Write Command Interval 012345678 CL = 2, 3 Hi-Z CLK DQM RD-A WT-B DQ DB2 DB3 DB4DB1 1 cycle BL = 8, CL = 2 012345678 9 CLK DQM CL = 2 RD-A WT-B DQ QA1 QA2 QA3 DB2 DB3DB1 Hi-Z is necessary

¡ Semiconductor MS82V16520 012345678 ex.) CL = 3, BL = 4 CLK DQM RD-A WT-B DQ QA1 DB2 DB3DB1 Hi-Z is necessary

¡ Semiconductor MS82V16520 BURST TERMINATION Burst Stop Command in Full Page 012345678 BL = Full Page, CL = 2, 3 Hi-Z CLK D2 D3 D4 WT BST CL = 2, 3 DQ D1 01234 5 678 BL = Full Page, CL = 2, 3 CLK Hi-ZQ2 Q3CL = 2 DQ Q1 Hi-ZQ2 Q3CL = 3 DQ Q1 BSTRD

¡ Semiconductor MS82V16520 Precharge Termination in READ Cycle 012345678 BL = X, CL = 2 CLK RD PRE ACT DQ Q1 Q3 Q4Q2 Hi-Z tRP 012345678 BL = X, CL = 3 CLK RD PRE ACT DQ Q1 Q3Q2 Hi-Z tRP

¡ Semiconductor MS82V16520 Precharge Termination in WRITE Cycle 012345678 BL = X, CL = 2 CLK WT PRE ACT DQ D3D2D1 D4 Hi-Z tRP Note : D5 data will not be written 012345678 BL = X, CL = 3 CLK WT PRE ACT DQ D3D2D1 Hi-Z tRP D4 D5 Note : D5 data will not be written

¡ Semiconductor MS82V16520

ELECTRICAL CHARACTERISTICS

Note : All voltages are referenced to V SS. Absolute Maximum Ratings Parameter UnitSymbol Voltage on Power Supply Pin Relative to GND VCC, VCCQV Voltage on Input Pin Relative to GND VT V Short Circuit Output Current I OS mA Power Dissipation P D W Storage Temperature T stg °C Condition Ta = 25°C Rating –1.0 to 4.6 Operating Temperature T opr °C— 0 to 70 –55 to 150 Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Min. Symbol Power Supply Voltage V CC 3.0 Input High Voltage V IH 2.0 Input Low Voltage V IL –0.3 Typ. 3.3 Max. 3.6 VCC + 0.3 0.8 Unit V V V (Ta = 0°C to 70°C) Capacitance Parameter Min. Symbol Input Capacitance (CLK, CKE, CS, RAS, CAS, WE, DSF, DQM) CI1 — CI2 — Input/Output Capacitance (DQ0 - DQ31) CI/O — Max. Unit pF pF pF (VCC = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz) Input Capacitance (A0 - A10) DC Characteristics 1 Parameter Symbol Test Condition IOH = –2 mAOutput High Voltage V OH Unit V Max. Min. 2.4 IOL = 2 mAOutput Low Voltage V OL V0.4— 0 V £ VI £ 3.6 V; All other pins not under test = 0 VInput Leakage Current ILI mA10–10 DOUT is disabled, 0 V £ VO £ 3.6 VOutput Leakage Current I LO mA10–10

¡ Semiconductor MS82V16520 DC Characteristics 2 Notes 1. I CC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during t CK (MIN.). 2. I CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during t CK (MIN.). 3. I CC5 is measured on condition that addresses are changed only one time during tCK (MIN.). Parameter Symbol Test Condition Burst length = 1, tRAS ³ tRAS (MIN.), tRP ³ tRP (MIN.), IO = 0 mAOperating Current I CC1 Unit Note mA 1 CKE £ VIL (MAX.), tCK = 15 nsPrecharge Standby Current ICC2P mACKE £ VIL (MAX.), tCK = ¥in Power Down Mode ICC2PS CKE ³ VIH (MIN.), tCK = 15 ns, Precharge Standby Current CS ³ VIH (MIN.), in Non Power Down Mode ICC2N Input signals are changed one time during 30 ns. mA CKE ³ VIH (MIN.), tCK = ¥,ICC2NS Input signals are stable. CKE £ VIL (MAX.), tCK = 15 nsActive Standby Current I CC3P mACKE £ VIL (MAX.), tCK = ¥in Power Down Mode I CC3PS CKE ³ VIH (MIN.), tCK = 15 ns, Active Standby Current CS ³ VIH (MIN.), in Non Power Down Mode ICC3N Input signals are changed one time during 30 ns. mA CKE ³ VIH (MIN.), tCK = ¥, ICC3NS Input signals are stable. tCK ³ tCK (MIN.),Operating Current ICC4 IO = 0 mA(Burst Mode) mA 2 tRC ³ tRC (MIN.)Refresh Current I CC5 CKE £ 0.2 VSelf Refresh Current I CC6 mA tCK ³ tCK (MIN.), IO = 0 mA,Operating Current tBWC (MIN.)(Block Write Mode) ICC7 mA CAS Latency = 2 CAS Latency = 3 Max. 180 180 200 200 140 mA 3 Max. 190 200 240 220 150

¡ Semiconductor MS82V16520 AC Characteristics Test conditions

AC measurements assume t T = 1 ns.
Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL.
If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX).
An access time is measured at 1.4 V.
Input levels at the AC testing are 2.4 V/0.4 V. 2.4 V tCK

1.4 VCLK

0.4 V 2.4 V

1.4 VInput

0.4 V tCH tCL tSetup tHold Output 1.4 V 1.4 V /,/#02/#03/#05 tOH tAC

¡ Semiconductor MS82V16520 Synchronous Characteristics Parameter Unit Note CAS Latency = 3 t CK3 ns Symbol Clock Cycle Time CAS Latency = 2 t CK2 ns CAS Latency = 3 t AC3 ns 1Access Time from CLK CAS Latency = 2 t AC2 ns 1 CLK High Level Width t CH ns CLK Low Level Width t CL ns Data-out Hold Time t OH ns Data-out Low-impedance Time t LZ ns Data-out CAS Latency = 3 t HZ3 ns High-impedance Time CAS Latency = 2 t HZ2 ns Data-in Setup Time t DS ns Data-in Hold Time t DH ns Address Setup Time t AS ns Address Hold Time t AH ns CKE Setup Time t CKS ns CKE Hold Time t CKH ns tCMS nsCommand (CS, RAS, CAS, WE, DSF, DQM) Setup Time tCMH nsCommand (CS, RAS, CAS, WE, DSF, DQM) Hold Time MS82V16520-8 Min. Max. (125 MHz) 12 (83 MHz) — 6.5 — 6.5 2.5 — 2.5 — 2.5 — 2.5 — MS82V16520-7 Min. Max. (143 MHz) 10 (100 MHz) 2.5 — 2.5 — 2.5 — Note 1. Output load. Output Z = 50 W 30 pF 50 W 1.4 V

¡ Semiconductor MS82V16520 Asynchronous Characteristics Parameter Unit Note tRC ns Symbol REF to REF/ACT Command Period tRAS nsACT to PRE Command Period tRP nsPRE to ACT Command Period tRCD nsDelay Time ACT to READ/WRITE Command tRRD nsACT (0) to ACT (1) Command Period CAS Latency = 3 t DPL3 nsData-in to PRE CAS Latency = 2 t DPL2 nsCommand Period tBWC nsBlock Write Cycle Time CAS Latency = 3 t BPL3 nsBlock Write Data-in CAS Latency = 2 t BPL2 ns to PRE Command Period CAS Latency = 3 t BAL3 CLKBlock Write Data-in Active (REF) Command Period (Auto Precharge) CAS Latency = 2 t BAL2 CLK tRSC nsMode Register Set Cycle Time tT nsTransition Time tREF msRefresh Time MS82V16520-8 Min. Max. 13 0 —3 2 120 k MS82V16520-7 Min. Max. 13 0 —3 2 120 k

¡ Semiconductor MS82V16520 TIMING WAVEFORM AC Parameters for Read Timing (BL = 2, CL = 2) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ /#01z /,/#02 /#03/#05/#06/#08 y/#7B /|/~/#7F/#81 /,/#02 y/#7B Hi-Z tCKH tCMS tCMH tCK tCH tCKS tCMS tCMH tCL /#01 /#07 z /#80 /#01 /#04/#07 z /#7D/#80 /#01 /#07 z /#80 /#01 /#04/#07 z /#7D/#80 /,y /#03/| /#06 y /#7F /#03/#06 y /|/#7F/, /#06 y /#05/~ /#02 /#05/#08 /#7B /#05/#08/~/#81 /#02 /#08 /#7B /#01/#02 /#04/#05/#07/#08 z/#7B /#04/#05/#07/#08 z/#7B /#03/#06y y /|/#7F /#01 /#01 /#04 /#04 /#07 /#07 /#07 z z /#7D /#7D /#80 /#80 /#80 /#06/#7F /,y /#06/#7F /#03/|/#03/|/,y tAS tAH DSF /,/#02 /#06/#08 y/#7B /#7F/#81 /,/#02 /#03/#05/#06/#08 y/#7B /|/~/#7F/#81 tRC tRAS tRRD tRP tRCD tLZ tOH tOH tAC tAC tHZ 123456789 1 0 1 1 1 2 1 3 Auto Precharge Start for Bank B ACT-A RD-A ACT-B RAP-B PRE-A ACT-A

¡ Semiconductor MS82V16520 AC Parameters for Write Timing (BL = 4, CL = 2) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ Hi-Z DSF t CMS tCMHtAS tAH tCMStCMH tDS tDH tRCD tRRD tDAL tDPL tRP tRC tCKH /#01/#02 /#07/#08 z/#7B /#80/#81 /#04/#05/#7D/~ /,/#02 /#06/#08 y/#7B /#7F/#81 /,/#02 /#06/#08 y/#7B /#7F/#81 /#06/#08 /#7F/#81 /#02 /#08 /#7B /#81 /#02 /#08 /#7B /#81 /,/#02 /#06/#08 y/#7B /#7F/#81 /,/#01 /#06/#07 yz /#7F/#80/#01/#02 /#07/#08 z/#7B /#80/#81 /#07/#08 z/#7B /#80/#81/,/#01 /#06/#07 yz /#7F/#80 /#01 /#01 /#04 /#04 /#07 /#07 /#07 z z /#7D /#7D /#80 /#80 /#80 /#07/#08 z/#7B /#80/#81/#01 /#07 z /#80 /#04/#7D /#01/#04z/#7D/#01 /#07 z /#80/, /#06 y /#7F /#03/| /#03/#06/|/#7F /,y/#06/#7F/#03/| /#06 y /#7F /#03/| /#04/#05/#7D/~ 123456789 2 1 2019181716151413121110 tCKS Auto Precharge Start for Bank B Auto Precharge Start for Bank A ACT-A ACT-BWAP-A ACT-A WAP-B WT-A PRE-A ACT-A

¡ Semiconductor MS82V16520 Relationship between Frequency and Latency Rate Clock Cycle Time [ns] Frequency [MHz] CAS Latency [tRCD] RAS Latency (CAS Latency + [tRCD]) [tRC] [tRAS] [tRRD] [tRP] [tDPL] MS82V16520-8 128 83125 MS82V16520-7 107 100143

¡ Semiconductor MS82V16520 Power on Sequence and Auto Refresh (Initialization) 02 35 68 9 1 0 1 1 1 3 1 5 1 7 1 8 2 0 2 1 CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF PRE (All Banks) REF REF Hi-Z tRC tRC MRA /#02 /#02 /#05 /#05 /#08 /#08/#7B /#7B /#81 /#81/#01 /#01 /#04 /#04 /#07 /#07z z /#7D /#7D /#80 /#80 /#02/#05/#7B/~ /#07/#08/#80/#81 /#01/#02/#04/#05 /#07 /#07 /#08 /#08z/#7B/#7D/~ /#80 /#80 /#81 /#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /,/#02/#03/#05 /#06 /#06 /#08 /#08 y/#7B/|/~ /#7F /#7F /#81 /#81 /,/#02 /#06/#08 y/#7B /#7F/#81 /#01 /#01 /#02 /#02 /#04/#05 /#07 /#07 /#08 /#08z z /#7B /#7B /#7D/~ /#80 /#80 /#81 /#81 /#07/#80 /#01/#04 /#07 /#07z/#7D /#80 /#80 /#01 /#07 z /#80 /#01/#04z/#7D /,/#03 /#06 /#06y/| /#7F /#7F /#06 y /#7F /,/#03y/| /#03/#06/|/#7F /#06/#7F 1 4 7 12 14 16 19 ADDRESS KEY High level is necessary 2 refresh cycles are necessaryHigh level is necessary

¡ Semiconductor MS82V16520 Mode Register Set (BL = 4, CL = 2) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ 0 2 3 4 5 6 9 1 11 2 1 41 5 1 71 8 2 02 1 DSF PRE (All Banks) MRA ACT tRP Hi-Z H /#01 /#04 /#04 /#07 /#07z /#7D /#7D /#80 /#80 /#03/|/#02 /#02 /#05 /#05 /#08 /#08 /#7B /#7B /#81 /#81 /, /#03 /#03 /#06 /#06y /#7F /#7F /,/#01 /#03 /#03 /#04 /#04 /#06 /#06 /#07 /#07yz /#7D /#7D /#7F /#7F /#80 /#80 /#01/#02 /#04 /#04 /#05 /#05 /#07 /#07 /#08 /#08z/#7B /#7D /#7D /#80 /#80 /#81 /#81 /,/#01 /#03 /#03 /#04 /#04 /#06 /#06 /#07 /#07yz /#7D /#7D /#7F /#7F /#80 /#80 /#03/#04/|/#7D /,y /#03 /#03 /#06 /#06y /#7F /#7F /#02 /#05 /#05 /#08 /#08/#7B /#81 /#81 /#02/#7B 1 7 8 1 01 31 61 9 tRSC ADDRESS KEY

¡ Semiconductor MS82V16520 Auto Refresh (CL = 2) CLK CKE H CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF PRE REF REF ACT RD tRP tRC tRC /#01/#04 /#07 z/#7D /#80/#01 /#07 z /#80 /#06 y/| /#7F/#02/#7B /#05/~ /#02/#05 /#08 /#7B/~ /#81/#02 /#08 /#7B /#81 /,/#03/#06y/|/#7F /,y/, /#06 y /#7F /#01 /#07 z /#80 /,/#02/#03/#05 /#06/#08 y/#7B/|/~ /#06/#08 y/#7B /#7F/#81 /#04/#05/#7D/~ /#01 /#01 /#02 /#02 /#04 /#04 /#05 /#05 /#07/#08z z /#7B /#7B /#7D /#7D /#80/#81 /#07/#08/#80/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /#04/#7D /#01 /#01 /#04 /#04 /#07z z /#7D /#7D /#80 /#01 /#01 /#03 /#03 /#04 /#04 /#06 /#06 /#07 /#07y y z z /#7D /#7D /#7F /#7F /#80 /#80 L 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 1

¡ Semiconductor MS82V16520 Self Refresh (Entry and Exit) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF PRE SREF entry SREF Exit SREF entry or (ACT) SREF Exit Next clock enable Next clock enable ACT tRP tRC tRC 0123 789 1 0 1 1 1 7 1 8 1 9 2 0 2 141 2 L /,y /#07/#80 /#01/#04 /#07 z/#7D /#80 /#01 /#04/#07 z /#7D/#80 /#04/#07/#7D/#80 /#03/#04/#06/#07 yz /|/#7D/#7F/#80 /#06/#08 /#7F/#81 /,/#02/#03/#05 /#06/#08 y/#7B/|/~ /#7F/#81 /,/#02 /#03/#05/#06/#08 y/#7B /|/~/#7F/#81 /,/#01/#03/#04 /#06/#07 yz/|/#7D /#7F/#80 /,/#03y/| /,/#03 /#06 y/| /#7F /#03/#06 y /|/#7F /#06/#7F /#02 /#08 /#7B /#81 /#02 /#05/#08 /#7B /~/#81 /#03/#06/|/#7F /#02 /#02 /#05 /#08 /#08/#7B /#7B /#81 /#81 /#02/#05/#7B/~ /#05/#08/~/#81 /#01 /#01 /#04 /#07 /#07z z /#7D /#80 /#80 /#01 /#01 /#04 /#04 /#07 /#07z z /#7D /#7D /#80 /#80

¡ Semiconductor MS82V16520 Auto Precharge after Read Burst (BL = 4, CL = 3) CLK CKE H CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF ACT-A ACT-B RD-A RAP-B ACT-B RAP-A L Hi-Z AP-B AP-A RAP-B /#01 /#04/#07 z /#7D/#80/#01/#02 /#07/#08 z/#7B /#80/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /,/#02 /#06/#08 y/#7B /#7F/#81/, /#03 /#03 /#03 /#06 /#06y y /#7F /#7F /#04/#07/#7D/#80 /#03/#05 /|/~ /#02/#05/#7B/~ /#02 /#08 /#7B /#01 /#07 z /#80 /#01/#04z/#7D /#04/#05/#7D/~ /#07 z /,/#03y/| /#03/#06/|/#7F /,y/#03/#06/|/#7F /#03/| /#06 y /#7F /,/#03y/| 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 QBb2QBb1QAb4QAb3QAb2QAb1QBa4QBa3QBa2QBa1QAa4QAa3QAa2QAa1 CBbRBbCAa CBaRBa CAbRAa RAa RBb RBa

¡ Semiconductor MS82V16520 Auto Precharge after Write Burst (BL = 4, CL = 3) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF H ACT-A ACT-B WT-A WAP-B WAP-A WAP-B L Hi-Z AP-B ACT-B AP-A /,/#03 /#06 y/| /#7F/,/#03y/| /,/#03y/| /#02 /#02 /#05 /#05 /#08 /#08 /#08 /#7B /#7B /#81 /#81 /#81 /,/#02 /#06/#08 y/#7B /#7F/#81 /,/#02 /#06/#08 y/#7B /#7F/#81 /#07 z /#01/#04z/#7D /#01/#04z/#7D/#01 /#07 z /#80 /#06 y /#06 y /#7F /#06/#7F /#06 y /#7F /#08 /#7B /#81 /#02/#05/#7B/~ /#02 /#08 /#7B /#81 /#08/#81 /#07/#08 z/#7B /#80/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /#07/#08/#80/#81 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 DBb4DBb3DBb2DBb1DAb4DAb3DAb2DAb1DBa4DBa3DBa2DBa1DAa4DAa3DAa2DAa1 CBbRBbCAa CBaRBa CAbRAa RAa RBb RBa

¡ Semiconductor MS82V16520 Full Page READ Cycle (CL = 3) CLK CKE H CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF ACT-A RD-A ACT-B RD-B Burst cannot end in Full Page mode PRE-B ACT-B L Hi-Z Burst stop Command tRP /,y /#06 y /#7F/, /#06 y /#07 z /#80 /#01/#04z/#7D /#01z /#01 /#07 z /#80 /#03/| /,/#03y/| /,/#03y/| /,/#01 /#06/#07 yz /#7F/#80/,/#01 /#06/#07 yz /#7F/#80 /#02 /#02 /#02 /#03 /#03 /#05 /#05 /#06 /#06 /#08 /#08 y y y /#7B /#7B /#7B /#7F /#7F /#81 /#81 /,/#01yz /#06 y /#7F /#03 /#03 /#06y y /#7F /,/#02 y/#7B /,/#02 /#06/#08 y/#7B /#7F/#81 /,/#02 /#06/#08 y/#7B /#7F/#81 /#06/#08 /#7F/#81 /#02/#05/#7B/~ /#02/#7B /#02 /#08 /#7B /#81 /#02/#05/#7B/~ /#02 /#08 /#7B /#81/#05/~ 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 QBa+3 QBa+4 QBa+5QBa+2QBa+1QBaQAa+1QAaQAa–1QAa–2QAa+1QAa RBbRBa CBa RBa RBb QAa–3 CAaRAa RAa

¡ Semiconductor MS82V16520 Full Page WRITE Cycle (CL = 3) CLK CKE H CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF ACT-A WT-A ACT-B Burst cannot end in Full Page mode WT-B PRE-B ACT-B L Hi-Z Burst stop Command tRP /#07/#08/#80/#81 /#06/#08 y/#7B /#7F/#81 /#02 /#08 /#7B /#81 /,/#02 /#06/#08 y/#7B /#7F/#81 /#06/#08 /#7F/#81 /#01/#02z/#7B /#01/#02 /#07/#08 z/#7B /#80/#81/#01/#02 /#07/#08 z/#7B /#80/#81 /#05/#08/~/#81 /#02/#05/#7B/~ /#02 /#08 /#7B /#81/#01 /#01 /#04 /#04 /#07 /#07 /#07 z z /#7D /#7D /#80 /#80 /#80 /#08/#81 /#01 /#01 /#02 /#02 /#04/#05 /#07 /#07 /#08 /#08z z /#7B /#7B /#7D/~ /#80 /#80 /#81 /#81 /#07/#80 /#04/#07/#7D/#80 /#01/#04z/#7D /#01/#04z/#7D /#01z/#02/#7B /,/#03y/|/#01 /#07 z /#80/#01 /#07 z /#80 /#06 y /#7F /#06/#7F /,y/, /#06 y /#7F /#03/#06/|/#7F /,/#03y/| 03 25 47 69 81 1 10 13 12 15 14 17 16 19 18 21 20 RBb RBb CBaCAaRAa RAa RBa RBa DBa+3 DBa+4DBa+2DBa+1DBaDAa+1DAaDAa–1DAa+3DAa+2DAa+1DAa

¡ Semiconductor MS82V16520 PRE (Precharge) Termination of Burst (BL = 4, 8, Full, CL = 3) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF DQM 0 - 3 ACT-A WT-A RD-A ACT-APRE-A PRE Command Termination L Hi-Z H PRE-A ACT-A PRE Command Termination tDPL tRP tRPtRAStRCD /#02 /#02 /#05 /#05 /#05 /#08 /#08/#7B /#7B /#81 /#81 /,/#01 /#06/#07 yz /#7F/#80 /#06 y /#7F /#01 /#07 z /,/#01 /#06/#07 yz /#03/#06/|/#7F /#06 y /#7F/,y/#03/| /,/#03y/| /#03/| /#02/#05/#7B/~ /#02 /#08 /#7B /#81 /#05/~ /#02 /#08 /#7B /#81/#08/#81 /#02/#05/#7B/~ /#01/#02 /#07/#08 z/#7B /#80/#81 /#04/#05/#7D/~ /#01/#02 /#07/#08 z/#7B /#04/#7D /#04/#7D/#07/#80 /#04/#07/#7D/#80 /#01 /#07 z /#80 /#05/~ /#02/#05 /#08 /#7B/~ /#08 /#7B /#81 /#04/#07/#7D/#80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 QAb3QAb2QAb1DAa1 RAcCAa RAb CAbRAa RAa RAb RAc DAa2 QAb4

¡ Semiconductor MS82V16520 Clock Suspension during Burst Read (using CKE Function) (BL = 4, CL = 3) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF DQM 0 - 3 ACT-A RD-A 1-CLOCK SUSPENDED 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED Hi-Z (turn off) at end of burst L /#04/#7D /#01 /#01 /#04 /#04 /#07 /#07z z /#7D /#7D /#80 /#80 /#03/#04/|/#7D /#01 /#01 /#03 /#03 /#04 /#04 /#06 /#06 /#07 /#07y y z z /#7D /#7D /#7F /#7F /#80 /#80 /#03/| /#03 /#03 /#06 /#06y y /#7F /#7F /#05/~ /#02 /#02 /#05 /#05 /#08 /#08/#7B /#7B /#81 /#81/#01 /#01 /#04 /#04 /#07 /#07z z /#7D /#7D /#80 /#80 /#01 /#01 /#03 /#03 /#04 /#04 /#06 /#06 /#07 /#07y y z z /#7D /#7D /#7F /#7F /#80 /#80 /#02 /#02 /#05 /#05 /#08 /#08/#7B /#7B /#81 /#81 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 1 QAa2 QAa3 QAa4 CAaRAa RAa QAa1

¡ Semiconductor MS82V16520 Clock Suspension during Burst Write (using CKE Function) (BL = 4, CL = 3) /#07/#08/#80/#81 /#01 /#01 /#02 /#02 /#04 /#04 /#05 /#05 /#07 /#07 /#08 /#08 z z /#7B /#7B /#7D /#7D /#80 /#80 /#81 /#81 /#07/#80 /#01 /#01 /#04 /#04 /#07 /#07 z z /#7D /#7D /#80 /#80 /#06/#7F /#03 /#03 /#06 /#06 y y /#7F /#7F /#01 /#01 /#02 /#02 /#04 /#04 /#05 /#05 /#07 /#07 /#08 /#08 z z /#7B /#7B /#7D /#7D /#80 /#80 /#81 /#81 /#01z/#01/#02z/#7B /#01 /#01 /#04 /#04 /#07 /#07 z z /#7D /#7D /#80 /#80 /#01/#02z/#7B/#01z /#06/#07/#7F/#80 /#01 /#01 /#03 /#03 /#04 /#04 /#06 /#06 /#07 /#07 y y z z /#7D /#7D /#7F /#7F /#80 /#80 /,/#01yz/,y /#08/#81 /#02 /#02 /#05 /#05 /#08 /#08 /#7B /#7B /#81 /#81 CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF DQM 0 - 3 L CAaRAa RAa ACT-A 1-CLOCK SUSPENDED 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED WT-A DAa4DAa3DAa2DAa1 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1

¡ Semiconductor MS82V16520 Power Down Mode and Clock Suspension (BL = 4, CL = 2) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF DQM 0 - 3 L VALID ACT-A RD-A ACTIVE STANDBY PRECHARGE STANDBY PRE-A PDPD Entry PD Exit Clock Mask Start Clock Mask End PD tCKS tCKS /,/#02 y/#7B /#02 /#05 /#05 /#08 /#08/#7B /#81 /#81 /#03 /#03 /#05 /#05 /#06/#08 y/#7B /#7F/#81 /#04 /#04 /#05 /#05 /#07/#08 z/#7B /#7D /#7D /#80/#81/#02/#7B /#05/#08/~/#81 /#02/#05/#7B/~ /#02 /#05 /#05 /#08 /#7B /#81/#01/#04z/#7D /#01 /#04 /#04 /#07 z /#7D /#7D /#80/,y /#03/#06/|/#7F /,/#03y/| /#03 /#03 /#06 y /#7F /#03 /#03 /#05 /#05 /#06/#08 y/#7B /#06 y /#7F 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 CAaRAa RAa QAa4QAa3QAa2QAa1

¡ Semiconductor MS82V16520 CLOCK Suspend Exit & Power Down Exit /,/#01/#02 CLK 2) Power Down (= Precharge Power Down) Exit CKE Internal CLK Command NOP ACT Note 2 < tCKS Note 3 /,/#01/#01/#02 CLK 1) Clock Suspend (= Active Power Down) Exit CKE Internal CLK Command Note 1 RD tCKS Notes: 1. Active power down: one or both bank active state. 2. Precharge power down: both bank precharge state. 3. NOP should be issued. And new command can be issued after 1 Clock.

¡ Semiconductor MS82V16520 Byte Read/Write Operation (by DQM) (BL = 4, CL = 2) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM DQM1 DSF DQM0 H ACT-B RD-B Byte of DQ8 - 15 not Read Byte of DQ0 - 7 not Read Byte of DQ0 - 7 not Write WT-B Byte of DQ8 - 15 not Write Byte of DQ0 - 7 not Read Byte of DQ0 - 7 not Read Byte of DQ0 - 7 not Write DQ 0 - 7 DQ 8 - 15 /,/#02 y/#7B /#01/#02 /#07/#08 z/#7B /#80/#81 /#01 /#07 z /,/#02 /#06/#08 y/#7B /#08/#81 /#02/#7B /#02 /#08 /#7B /#81 /#07/#08/#80/#81 /#06/#7F /,/#03/#06y/|/#7F /#06 y /#7F/,/#02 /#06/#08 y/#7B /#7F/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /#04/#07/#7D/#80 /#07 z /#80 /,/#02 /#06/#08 y/#7B /#7F/#81 /#02 /#02 /#05 /#05 /#08 /#08/#7B /#7B /#81 /#81 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 1 QBa4QBa3QBa2 DBb2 DBb1 DBb4 QBc2 QBc1 QBc3 QBc4 QBa1 QBa3QBa2 DBb2 DBb3 QBc2 QBc3 RBa RBa CBa CBb CBc RD-B

¡ Semiconductor MS82V16520 Burst Read and Single Write (BL = 4, CL = 2) CLK CKE CS RAS CAS WE A10 (BA) ADD DQM1 DQ 0 - 7 DQ 8 - 15 DSF DQM0 ACT-B RD-B Single WT Single WT RD Single WT H Write Masking /#01 /#01 /#04 /#04 /#04 /#07 /#07z z /#7D /#7D /#7D /#80 /#80 /#06/#7F /#01 /#07 z /#80 /#06 y /#7F /#02 /#08 /#7B /#81 /#01/#04 /#07 z/#7D /#80 /,/#03 /#06 y/| /#7F /#01z /#02/#05 /#08 /#7B/~ /,/#01 /#06/#07 yz /#06/#07 yz/|/#7D /#7F/#80/#07/#80 /#08/#81 /#02 /#08 /#7B /#81 /,/#02 /#06/#08 y/#7B /#7F/#81 /#02/#05 /#08 /#7B/~ /#81 /,/#02/#03/#05 /#06/#08 y/#7B/|/~ /#7F/#81 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 QBa1 QBa2 QBa3 QBa4 DBb DBc CBb CBc CBd CBe DBe QBd1 CBa RBa RBa

¡ Semiconductor MS82V16520 Special Mode Register Set (BL = 4, CL = 2) /#01 /#07 z /#80 /,/#02 /#06/#08 y/#7B /#7F/#81 /#01z /#01/#02 /#04/#05/#07/#08 z/#7B /#06 y /#7F /#01 /#07 z /#80 /#08 /#7B /#81 /#01 /#01 /#04 /#04 /#07z z /#7D /#7D /#80/#02 /#02 /#05 /#05 /#08/#7B /#7B /#81 /, /#03 /#03 /#06y y /#7F/, /#02 /#02 /#03 /#03 /#05 /#05 /#06/#08 y y /#7B /#7B /#01 /#02 /#02 /#04 /#04 /#05 /#05 /#07/#08z z /#7B /#7B /#7D /#7D /#80/#81/#01z/#01 /#01 /#04 /#04 /#07z z /#7D /#7D /#80/,/#01yz/, /#01 /#01 /#03 /#03 /#04 /#04 /#06/#07y y z z /#7D /#7D /#7F/#80/,/#01 /#03/#04/#06/#07 yz /|/#7D/#7F/#80 /#03 /#03 /#06y y /#7F/, /#03/#06 y /|/#7F CLK CKE CS RAS CAS WE A10 (BA) ADD DQM 0 - 3 DQ DSF SMRAPRE (All Banks) Remark Special Register Set command can be input at any state. ACT is valid H Hi-Z tRP 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 1 tRSC ADDRESS KEY Color or Mask data

¡ Semiconductor MS82V16520 Random Row Write with WPB (BL = 8, CL = 3) /#08 /#7B /#81 /#02/#05/#7B/~ /#08/#81 /#02/#7B /#07/#08/#80/#81 /#07/#80 /#01/#04z/#7D /#01 /#07 z /#80 /#04/#07/#7D/#80 /#01/#04z/#7D /#06 y /#7F /,/#02 /#06/#08 y/#7B /#7F/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /#01 /#07 z /#04/#7D /#01z /#04/#7D /,/#03y/| /#06 y /#7F /#03/| /,y CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-A with WPB WT-A WPB is enabled. ACT-B WT-B WPB is disabled. WT-A WPB is disabled. PRE-A PRE-BACT-A H L tRCD tDPL tRP tDPL DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2 DAb3 RAa RAa CAa RBa RBa CBa RAb RAb CAb 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1

¡ Semiconductor MS82V16520 Block Write (Page at Same Bank) (CL = 3) CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-B BW-B BW-B BW-B BW-B BW-B WPB is enabled. PRE-B ACT-B with WPB H tRCD tRCDtRPtBPLtBWCtBWC /#01/#02 /#07/#08 z/#7B /#80/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /,/#02 /#06/#08 y/#7B /#7F/#81 /#06 y /#7F /,/#02 /#06/#08 y/#7B /#07 z /#80 /#08 /#7B /#81 /#05/#08/~/#81 /#02 /#08 /#7B /#81 /#01 /#07 z /#80 /#07/#08 z/#7B /#80/#81/#01/#02 /#07/#08 z/#7B /#80/#81 /#04/#7D /#04/#07/#7D/#80 /#03/#06 y /|/#7F /#01 /#07 z /#80 /#01/#04z/#7D/#01 /#04/#07 z /#03 /#03 /#06 y /#7F /#03/| /#06 y /#7F 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 RBa RBa CBa CM CBb CBc CBd CM CM CM CM I/O Mask I/O Mask I/O Mask I/O Mask L = No I/O Mask RBb CBc RBb I/O Mask tBWC

¡ Semiconductor MS82V16520 Block Write (Page at Same Bank) Changing Color and Mask Data (CL = 3) /,/#03y/|/,/#01 /#06/#07 yz /#7F/#80/#01z /#06/#07/#7F/#80 /#06 y /#01 /#07 z /#80 /#04/#7D /#01 /#07 z /#80 /,/#02 /#06/#08 y/#7B /#7F/#81 /#02 /#08 /#7B /#81 /#07/#80 /,/#01/#03/#04 /#06/#07 yz/|/#7D /,/#02/#03/#05 /#06/#08 y/#7B/|/~ /#7F/#81 CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-B with WPB BW-B SMRA (Mask data) BW-B SMRA (Color data) PRE-B ACT-BBW-B BW-B H tRCDtBPLtBWCtRSC tBWCtRSCtBWCtRCD CM RBa RBa CBa 20h CBb 40h CBc CBd RBb RBb Mask CM Color CMCM I/O Mask I/O Mask I/O Mask I/O Mask 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9

¡ Semiconductor MS82V16520 Interleaved Block Write (CL = 3) CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-A BW-A BW-B BW-BBW-A ACT-B PRE-B H L tRPtBPLtBWCtBWCtRCDtRCD Column Mask /#06/#7F /#04/#05/#7D/~ /#02 /#08 /#7B /#81 /#02/#7B/#03/| /#01 /#07 z /#07/#08/#80/#81 /#04/#7D/#07/#80 /#01z /#02/#05/#7B/~ /#01/#02 /#07/#08 z/#7B /#80/#81 /#08 /#7B /#81 /#08/#81 /#02/#7B /#02 /#08 /#7B /#81/,/#01 /#06/#07 yz /#7F/#80 /,/#01/#03/#04 /#06/#07 yz/|/#7D /#7F/#80 /,/#01 /#06/#07 yz /#7F/#80 /#06 y 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 ACT-B CM RAa RAa CAa RBa CBa CAb CBb RBa CM CM CM RBb RBb

¡ Semiconductor MS82V16520 Random Column Read (Page with Same Bank) (BL = 4, CL = 3) /,/#02 /#06/#08 y/#7B /,/#02 /#06/#08 y/#7B /#7F/#81 /,/#02 y/#7B /#01/#02z/#7B /#01/#02 /#07/#08 z/#7B /#80/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /#01/#02z/#7B /#04/#07/#7D/#80 /#01/#04z/#7D /#04/#7D /#01 /#07 z /#80 /#04/#07/#7D/#80 /#01 /#07 z /#80 /#01z /#01z /#03/#06/|/#7F /,/#03y/| /#03/| /#06 y /#7F /#03/#06/|/#7F /#06 y /#7F /,y /,y /#05/#08/~/#81 /#02 /#08 /#7B /#81/#02/#7B /#02/#05/#7B/~ /#05/~ /#02 /#08 /#7B /#81 /#02/#7B /#05/#08/~/#81 CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-A RD-A RD-A PRE-A ACT-A RD-ARD-A H L tRP /#02 /#02 /#02 /#05 /#05 /#08 /#08 /#7B /#7B /#7B /#81 /#81 RAa CAa CAb CAc RAa CAa /#03/#05 /|/~ /,/#02 /#06/#08 y/#7B /#7F/#81 /#06/#08 y/#7B /#7F/#81 /,/#02 y/#7B RAa RAa QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1

¡ Semiconductor MS82V16520 Random Column Write (Page with Same Bank) (BL = 4, CL = 3) CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-B WT-B WT-B WT-B WT-BACT-BPRE-B H L tRP DBb2 DBc1 DBc2 DBc3 DBc4 DBd1DBa2DBa1 DBa3 DBa4 DBb1 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 /#07/#80 /#01 /#07 z /#07 z /#80 /#01z /#01z /,/#03y/| /#06/#7F/,/#03y/| /#03/#06/|/#7F /#06 y /#7F /,y /#06 y /#7F /,y /#02 /#08 /#7B /#81 /#02/#05/#7B/~ /#05/#08/~/#81 /#02/#7B/#08/#81 /#02 /#08 /#7B /#81 /#02/#05/#7B/~ /#02/#7B /,/#01 /#06/#07 yz /#7F/#80 /,/#01yz /,/#01 /#06/#07 yz /#7F/#80 /,/#01yz /#06/#07/#7F/#80 /#01 /#01 /#01 /#03 /#03 /#04 /#04 /#06 /#06 /#07 /#07 y y y z z z /#7D /#7D /#7F /#7F /#80 /#80 RBa CBa CBb CBc RBd CBd /#07/#80 /#04/#07/#7D/#80 /#01 /#07 z /#80 /#01/#04z/#7D /#01 /#07 z /#80 /#01/#04z/#7D/#01z /#01z RBa RBd /#01/#02 /#07/#08 z/#7B /#80/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /#01/#02z/#7B

¡ Semiconductor MS82V16520 Random Row Read (BL = 8, CL = 3) /#01 /#01 /#03 /#03 /#04 /#04 /#06 /#06 /#06 /#07 /#07 /#07 y y z z /#7D /#7D /#7F /#7F /#7F /#80 /#80 /#80 /#02 /#08 /#7B /#81 /#08/#81/#07/#80 /#04/#7D/#05/~ /#02/#05/#7B/~ /#01z /#07/#08/#80/#81 /,y /#03/#04/|/#7D /#01 /#07 z /#80 /#04/#07/#7D/#80 /#06/#7F /#03/| /,/#01 /#06/#07 yz /#7F/#80 /#06 y /#7F /#01/#02 /#07/#08 z/#7B /#80/#81 /#03/#06/|/#7F /,/#03y/| /,/#03y/| /#01/#04z/#7D /#01z /#01 /#07 z /#80 /#04/#07/#7D/#80 /#01/#04z/#7D /#07/#80 CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-B ACT-BACT-ARD-B RD-BRD-A PRE-B PRE-A H L tRPtRCD CL RBa RBa RAa RBb CBa RAa CAa RBb CBb QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7QBa2QBa1 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa8 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1

¡ Semiconductor MS82V16520 Random Row Write (BL = 8, CL = 3) /,/#01yz/,y /,/#01 /#06/#07 yz /#7F/#80 /#01/#04z/#7D /#08/#81/#06/#7F /#01/#02 /#07/#08 z/#7B /#80/#81 /#05/#08/~/#81 /#02/#05/#7B/~ /#02/#7B /#07 z /#80 /#06 y /#7F /#07/#80 /#04/#07/#7D/#80 /#04/#7D /#01/#02z/#7B/#01z /#02 /#08 /#7B /#81 /#08/#81/#02 /#08 /#7B /#05/~ /#02/#7B /#05/#08/~/#81 /#02/#7B /#02 /#08 /#7B /#81 /#05/~ /#05/~ /#02/#05/#7B/~ CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-A ACT-APRE-A PRE-BWT-A WT-B WT-A H L tDPLtRCD tRPtDPL DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2 DAb3DAa2DAa1 RAa CBa RAb RAb CAb DAa3 DAa4 DAa5 DAa7 DAa8 RAa CAa 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 1 ACT-B RBa RBa DAa6

¡ Semiconductor MS82V16520 READ and WRITE (BL = 4, CL = 3) /,/#03 /#06 y/| /#7F /#02/#05 /#08 /#7B/~ /#81 /#03/#06/|/#7F /#03/#06/|/#7F /,/#03 /#06 y/| /#7F /#06 y /#7F /#02 /#08 /#7B /#81 /#03/#06/|/#7F /#01/#04 /#07 z/#7D /#80 /#04/#07/#7D/#80 /#01 /#07 z /#80 /#06 y /#7F /#06/#07 yz/|/#7D /,/#01 /#06/#07 yz /#07/#08 z/#7B/#7D/~ /#80/#81 /#01/#04 /#07 z/#7D /#80 /#01/#02 /#07/#08 z/#7B /#01 /#07 z /#80 CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-A RD-A WT-A RD-A Hi-Z at the end of Burst function 0-clock latency 2-clock latency Hi-Z H RAa CAa CAb CAc DAb1 DAb2 DAb4 QAc1 QAc2QAa1 RAa QAa2 QAa3 QAa4 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 Write latency = 0 Write Masking

¡ Semiconductor MS82V16520 Interleaved Column READ Cycle (BL = 4, CL = 3) /#02 /#02 /#02 /#05 /#05 /#08 /#08 /#7B /#7B /#7B /#81 /#07 z /#80 /#01z /,/#02 /#06/#08 y/#7B /#7F/#81 /#05/#08/~/#81 /#08 /#7B /#03/|/#06/#7F /,/#02 y/#7B /#01z/#01z/,y /,/#02 y/#7B /#01z/#01 /#07 z /#01/#04z/#7D/,y/, /#06 y /#7F /#02/#7B /,/#02 /#06/#08 y/#7B /#7F/#81 CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-A RD-A RD-B RD-B RD-B RD-A PRE-B PRE-A ACT-B H L tRCD tRRD CL RAa CAa RBa CBa CBb CBc CAb RAa QBc1 QBc2 QAb1 QAb2 QAb3 QAb4QAa2QAa1 QAa3 QAa4 QBa1 QBa2 QBb1 QBb2 RBa 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1

¡ Semiconductor MS82V16520 Interleaved Column WRITE Cycle (BL = 4, CL = 3) /#01 /#01 /#04 /#04 /#07 /#07 /#07 z z /#7D /#7D /#80 /#80 /#80 /#01 /#07 z /#80 /#01z /#06 y /#7F /,y /,/#02 /#06/#08 y/#7B /#7F/#81 /#04/#05/#7D/~ /#05/#08/~/#81 /#01/#02z/#7B /#02/#7B /#02 /#08 /#7B /#81 /#07/#08/#80/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /#01/#02 /#07/#08 z/#7B /#80/#81 /#01/#02z/#7B /#07/#08/#80/#81 /#04/#05/#7D/~ CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-A WT-A WT-B WT-B WT-B WT-A WT-B PRE-B ACT-B PRE-A H L tRCD tRRD tDPL tDPL RAa CAa RBa CBa CBb CBc CAb CBd RAa DBc1 DBc2 DAb1 DAb2 DBd1 DBd2 DBd3 DBd4DAa2DAa1 DAa3 DAa4 DBa1 DBa2 DBb1 DBb2 RBa 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1

¡ Semiconductor MS82V16520 Full Page Random Column Read (BL = Full Page, CL = 2) /#03 /#03 /#06 /#06 /#06 y y /#7F /#7F /#7F /#03/|/,/#01 /#06/#07 yz /#7F/#80 /#02 /#08 /#7B /#81 /#02 /#08 /#7B /#81 /#06 y /#7F/#01 /#07 z /#80 /#04/#7D/#07/#80 /,/#01 /#06/#07 yz /#02 /#08 /#7B /,/#01 /#06/#07 yz /#7F/#80 /#06 y /#7F /#02 /#08 /#7B /#81 /#01 /#07 z /#80 /,/#01 /#06/#07 yz CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-A ACT-B RD-B RD-A RD-A RD-ARD-B RD-B PRE-B (PRE Termination) H L tRCD tRRD tRCD RAa RBa CAa CBa CAb CBb CAc CBc QAc3 QBc1 QBc2 QBc3 Hi-Z QBa1QAa1 QAb1 QAb2 QBb1 QBb2 QAc1 QAc2 RBaRAa 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1

¡ Semiconductor MS82V16520 Full Page Random Column Write (BL = Full Page, CL = 2) /#01 /#01 /#04 /#04 /#04 /#07 /#07z z /#7D /#7D /#7D /#80 /,/#02 /#06/#08 y/#7B /#7F/#81 /,/#01 /#06/#07 yz /#7F/#80 /#08/#81 /#01 /#07 z /#80/#05/~ /#01/#04z/#7D /#06 y /#7F /#01 /#07 z /#80 /#01/#04z/#7D /#02 /#08 /#7B /#81 /,/#01yz CLK CKE CS RAS CAS WE A10 (BA) ADD DQ DSF DQM 0 - 3 ACT-A ACT-B WT-B WT-B WT-B PRE-B (PRE Termination) WT-A WT-A WT-A H L tRCD tRRD tRCD RAa RBa CAa CBa CAb CBb CAc CBc DAc3 DBc1 DBc2 DBc3DBa1DAa1 DAb1 DAb2 DBb1 DBb2 DAc1 DAc2 RBaRAa 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1

¡ Semiconductor MS82V16520 (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFP100-P-1420-0.65-BK4 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.54 TYP. Mirror finish

The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan E2Y0002-29-62

Summary

262,144-Word x 32-Bit x 2-Bank Synchronous Graphics RAM

Description