MS81V04166A-XXTB

MS81V04160A OKI | Alldatasheet

Document overview

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Technical content

This version: Nov.,21, 2002 MS81V04160A Dual FIFO (262,214 Words × 8 Bits) × 2 GENERAL DESCRIPTION The MS81V04160A is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO (First-In First-Out) memories which were designed for 262,214 x 8-bit high-speed asynchronous read/write operation. The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in common. The MS81V04160A, functionally compatible with Oki's 2Mb FIFO memory (MSM51V8222A), can be used as a x16 configuration FIFO. The MS81V04160A is a field memory for wide or low end use in general commodity TVs and VTRs exclusively and is not designed for high end use in professional graphics systems, which require long term picture storage, data storage, medical use and other storage systems. The MS81V04160A provides independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The MS81V04160A provides high speed FIFO (First-in First-out) operation without external refreshing: MS81V04160A refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MS81V04160A’s function is simple, and similar to a digital delay device whose delay-bit- length is easily set by reset timing. The delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 71 x 16-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. Additionally, the MS81V04160A has a write mask function or input enable function (IE), and read- data skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to MS81V04160A. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in picture” on a TV screen.

FEATURES

• 262,214 words × 8 bits × 2
• Fast FIFO (First-In First-Out) Operation: 25 ns cycle time
• Self refresh (No refresh control is required)
• High speed asynchronous serial access Read/Write Cycle Time 20 ns/25 ns Access Time 18 ns/23 ns
• Variable length delay bit (150 to 262214)
• Write mask function (Output enable control)
• Cascading capability by mode setting
• Single power supply: 3.3 V ± 0.3V
• Package: 100-Pin plastic TQFP (TQFP 100-P-1414-0.50-k) (Product: MS81V04160A-xxTB) xx indicates speed rank. MS81V04160A-xxTB Parameter Symbol –20 –25 Access Time tAC 18 ns 23 ns Read/Write Cycle Time tSWC tSRC 20 ns 25 ns Operation current ICC1 80 mA 80 mA Standby current ICC2 3 mA 3 mA

PIN CONFIGURATION (TOP VIEW) 100

100 PIN TQFP

MODE1,2 Mode Input NC No Connection VCC Power Supply (3.3 V) VSS Ground (0 V) Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.

256k (×8) Memory Array Serial Read Register (×8) Serial Write Register (×8) Serial Read Controller RE2 RSTR2 SRCK WE2 RSTW2 SWCK

71 Word

Sub-Register (×8) Data-In Buffer (×8) Data-Out Buffer (×8) DO (×8) DI (×8) Read/Write and Refresh Controller IE2 Sub-Register (×8) Controller Serial Write Decoder OE2 Clock Oscillator VBB Generator MODE1,2 256k (×8) Memory Array Serial Read Controller RE1 RSTR1 SRCK WE1 RSTW1 SWCK Sub-Register (×8) Data-In Buffer (×8) Data-Out Buffer (×8) DO (×8) DI (×8) Read/Write and Refresh Controller IE1 Sub-Register (×8) Decoder OE1 Serial Write Controller Serial Read Register (×8) Serial Read Register (×8)

Data Inputs: (DIN10 to 17) These pins are used for serial data inputs. Write Reset: RSTW1 The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW1 setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW1, the states of WE1 and IE1 are ignored in the write reset cycle. Before RSTW1 may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Write Enable: WE1 WE1 is used for data write enable/disable control. WE1 high level enables the input, and WE1 low level disables the input and holds the internal write address pointer. There are no WE1 disable time (low) and WE1 enable time (high) restrictions, because the MS81V04160A is in fully static operation as long as the power is on. Note that WE1 setup and hold times are referenced to the rising edge of SWCK. Input Enable: IE1 IE1 is used to enable/disable writing into memory. IE1 high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE1 level. Note that IE1 setup and hold times are referenced to the rising edge of SWCK. Data Out: (DOUT0 to 11) These pins are used for serial data outputs. Read Reset: RSTR1 The first positive transition of SRCK after RSTR1 becomes high resets the read address pointers to zero. RSTR1 setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states of RE1 and OE1 are ignored in the read reset cycle. Before RSTR may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles. Read Enable: RE1 The function of RE1 is to gate of the SRCK clock for incrementing the read pointer. When RE1 is high before the rising edge of SRCK, the read pointer is incremented. When RE1 is low, the read pointer is not incremented. RE1 setup times (tRENS and tRDSS) and RE1 hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. Output Enable: OE1 OE1 is used to enable/disable the outputs. OE1 high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE1 level. Note that OE1 setup and hold times are referenced to the rising edge of SRCK. Serial Write: Clock SWCK The SWCK latches the input data on chip when WE1,2 and IE1,2 are high, and also increments the internal write address pointer when WE1,2 is high. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Serial Read Clock: SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE1, 2 is high during a read operation. The SRCK input increments the internal read address pointer when RE1, 2 is high. The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK.

Data Input: (DIN20 to 27) These pins are used for serial data inputs. Write Reset: RSTW2 The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW2 setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW2, the states of WE2 and IE2 are ignored in the write reset cycle. Before RSTW2 may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Write Enable: WE2 WE is used for data write enable/disable control. WE2 high level enables the input, and WE2 low level disables the input and holds the internal write address pointer. There are no WE2 disable time (low) and WE2 enable time (high) restrictions, because the MS81V04160A is in fully static operation as long as the power is on. Note that WE2 setup and hold times are referenced to the rising edge of SWCK. Input Enable: IE2 IE2 is used to enable/disable writing into memory. IE2 high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE2 level. Note that IE2 setup and hold times are referenced to the rising edge of SWCK. Data Out: (DOUT20 to 27) These pins are used for serial data outputs. Read Reset: RSTR2 The first positive transition of SRCK after RSTR2 becomes high resets the read address pointers to zero. RSTR2 setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR2, the states of RE2 and OE2 are ignored in the read reset cycle. Before RSTR2 may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles. Output Enable: OE2 OE2 is used to enable/disable the outputs. OE2 high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE2 level. Note that OE2 setup and hold times are referenced to the rising edge of SRCK. Mode Setting1: MODE1 The Cascade/Non cascade select pin. Setting the MODE1 pin to the VCC level configures this memory device as cascade type and setting the pin to the VSS level configures this memory device as non cascade. During memory operation, the pin must be permanently connected to VCC or VSS. If a MODE1 level is changed during memory operation, memory data is not guaranteed. Mode Setting2: MODE2 MODE2 selects whether the control input signals are enabled at a high level or a low level. Setting MODE2 to the Vcc level enables the control input signals at a low level and setting MODE2 to the Vss level enables the control input signals at a high level. Note: Cascade/Non cascade When MODE1 is set to the VSS level, memory accessing starts in the cycle in which the control signals are input (Non cascade type). When MODE1 is set to the VCC level, memory accessing starts in the cycle subsequent to the cycle in which the control signals are input (Cascade type). This type is used for consecutive memory accessing.

ELECTRICAL CHARACTERISTICS

at Ta = 25°C, VSS –1.0 to +5.5 V Output Current IOS Ta = 25°C mA Power Dissipation PD Ta = 25°C W Operating Temperature TOPR 0 to 70 Storage Temperature TSTG –55 to +150 Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage VCC 3.0 3.3 3.6 V Power Supply Voltage VSS V Input High Voltage VIH 2.4 VCC 5.5 V Input Low Voltage VIL –0.3 +0.8 V DC Characteristics Parameter Symbol Condition Min. Max. Unit Input Leakage Current ILI 0<VI<VCC, Other input pins at V = 0 V –10 +10 µA Output Leakage Current ILO 0<VO<VCC –10 +10 µA Output “H” Level Voltage VOH IOH = –1 mA 2.4 V Output “L” Level Voltage VOL IOL = 2 mA 0.4 V Operating Current ICC1 Minimum Cycle Time, Output Open mA Standby Current ICC2 Input Pin = VIH/VIL mA Capacitance (Ta = 25°C, f = 1 MHz) Parameter Symbol Max. Unit Input Capacitance (DI, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE) CI pF Output Capacitance (DO) CO pF

(VCC = 3.3 V ±0.3 V, Ta = 0 to 70°C) MS81V04160A-20 MS81V04160A-25 Unit Parameter Symbol Min. Max. Min. Max. Access Time from SRCK tAC ns DOUT Hold Time from SRCK tDDCK ns DOUT Enable Time from SRCK tDECK ns SWCK “H” Pulse Width tWSWH ns SWCK “L” Pulse Width tWSWL ns Input Data Setup Time tDS ns Input Data Hold Time tDH ns WE Enable Setup Time tWENS ns WE Enable Hold Time tWENH ns WE Disable Setup Time tWDSS ns WE Disable Hold Time tWDSH ns IE Enable Setup Time tIENS ns IE Enable Hold Time tIENH ns IE Disable Setup Time tIDSS ns IE Disable Hold Time tIDSH ns WE “H” Pulse Width tWWEH ns WE “L” Pulse Width tWWEL ns IE “H” Pulse Width tWIEH ns IE “L” Pulse Width tWIEL ns RSTW Setup Time tRSTWS ns RSTW Hold Time tRSTWH ns SRCK “H” Pulse Width tWSRH ns SRCK “L” Pulse Width tWSRL ns RE Enable Setup Time tRENS ns RE Enable Hold Time tRENH ns RE Disable Setup Time tRDSS ns RE Disable Hold Time tRDSH ns OE Enable Setup Time tOENS ns OE Enable Hold Time tOENH ns OE Disable Setup Time tODSS ns OE Disable Hold Time tODSH ns RE “H” Pulse Width tWREH ns RE “L” Pulse Width tWREL ns OE “H” Pulse Width tWOEH ns OE “L” Pulse Width tWOEL ns RSTR Setup Time tRSTRS ns RSTR Hold Time tRSTRH ns SWCK Cycle Time tSWC ns SRCK Cycle Time tSRC ns Transition Time (Rise and Fall) tT ns

AC Characteristics Measuring Conditions Output Compare Level 1.5 V / 1.5 V Output Load

1 TTL + 30 pF

3.0 V / 0.0 V Input Signal Rise/Fall Time 3 ns Input Signal Measuring Reference Level 1.5 V 1. Input voltage levels for the AC characteristic measurement are VIH = 3.0 V and VIL= 0 V. The transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and VIL = 0 V. 2. AC measurements assume tT = 3 ns. 3. Read address must have more than a 150 address delay than write address in every cycle when asynchronous read/write is performed. 4. Read must have more than a 150 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called “new data read”. When read has less than a 20 address delay than write, the read data are the data written in a previous series of write cycles which had been written before at last write reset cycle: this is called “old data read”. 5. When the read address delay is between more than 21 and less than 149 or more than 262,214, read data will be undetermined. However, normal write is achieved in this address condition.

Write Operation Cycle (MODE2 = VSS) The write operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1, WE2 and IE1, IE2. Port1 write operation is accomplished by cycling SWCK, and holding WE1 and IE1 high after the write address pointer reset operation or RSTW1. RSTW1 must be preformed for internal circuit initialization before Write operation. Each write operation, which begins after RSTW1, must contain at least 140 active write cycles, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW1 operation is required after the last SWCK cycle. Note that every write timing of MS81V04160A is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Setting MODE1 to the VSS level starts write data accessing in the cycle in which RSTW1, WE1, and IE1 control signals are input. Setting MODE1 to the VCC level starts write data accessing in the cycle subsequent to the cycle in which RSTW1, WE1, and IE1 control signals are input. These operation are the same for Port1 and Port2. Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and Data input. WE1, 2 IE1, 2 Internal Write address pointer Data input H H Input H L Incremented L X Halted Not input X indicates “don’t care” Write Operation Cycle (MODE2=VCC) The write operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1, WE2, and IE1, IE2. Port1 write operation is accomplished by cycling SWCK and holding WE1 and IE1 low after the write address pointer reset operation or RSTW1. RSTW1 must be performed for internal circuit initialization before write operation. Each write operation, which begins after RSTW1, must contain at least 140 active write cycle, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW1 operation is required after the last SWCK cycle. Note that every write timing of MS8104160A is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Setting MODE1 to the VSS level starts write data accessing in the cycle in which RSTW1.WE1, and IE1 control signals are input. Setting MODE1 to the VCC level starts write data accessing in the cycle in which RSTW1, WE1, and IE1 control signals are input. Setting MODE1 to the VCC level starts write data accessing in the cycle subsequent to the cycle in which RSTW1, WE1, and IE1 control signals are input. These operations are the same for port1 and Port2.

Read Operation Cycle (MODE2=VSS) The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1, RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding RE1 and OE1 high after the read address pointer reset operation or RSTR1. Each read operation, which begins after RSTR1, must contain at least 140 active read cycles, i.e. SRCK cycles while RE1 and OE1 are high. These operations are the same for Port1 and Port2. Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data output. WE1, 2 IE1, 2 Internal Write address pointer Data output H H Output H L Incremented High impedance L X Output L L Halted High impedance Read Operation Cycle (MODE2=VCC) The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1, RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding RE1 and OE1 low after the read address pointer reset operation or RSTR1. Each read operation, which begins after RSTR1, must contain at least 140 active read cycles, i.e. SRCK cycles while RE1 and OE1 are low. These operations are the same for Port1 and Port2. Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data output. RE1,2 OE1,2 L L L H H L H H Halted Output High impedance Internal Write address pointer Data output Incremented Output High impedance

Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 µs after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 µs stabilization interval, the following initialization sequence must be performed. Because the read and write address pointers are undefined after power-up, a minimum of 80 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW1, 2 operation and an RSTR1, 2 operation, to properly initialize the write and the read address pointer. Dummy write cycles/RSTW1, 2 and dummy read cycles/RSTR1, 2 may occur simultaneously. If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is necessary to perform an RSTR1, 2 operation plus a minimum of 80 SRCK cycles plus another RSTR1, 2 operation, and an RSTW1, 2 operation plus a minimum of 80 SWCK cycles plus another RSTW1, 2 operation to properly initialize read and write address pointers. Old/New Data Access There must be a minimum delay of 150 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR1, 2 operation, before the start of writing the second field (before the next RSTW1, 2 operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 20 SWCK cycles. If the RSTR1, 2 operation for the first field read-out occurs less than 20 SWCK cycles after the RSTW1, 2 operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called “old data”. In order to read out “new data”, i.e., the second field written in, the delay between an RSTW1, 2 operation and an RSTR1, 2 operation must be at least 150 SRCK cycles. If the delay between RSTW1, 2 and RSTR1, 2 operations is more than 21 but less than 149 cycles, then the data read out will be undetermined. It may be “old data” or “new data”, or a combination of old and new data. Such a timing should be avoided.

Write Cycle Timing (Write Reset): MODE1 = VCC, MODE2 =VSS DI 10-17/20-27 n cycle 0 cycle 1 cycle 2 cycle tDS tDH tRSTWS tRSTWH tWSWH tWSWL tSWC n – 1 n SWCK WE1, 2 IE1, 2 RSTW1, 2 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Write Cycle Timing (Write Enable): MODE1 = VCC, MODE2 =VSS n cycle Disable cycle n + 1 cycle tWENH tWWEL tWENS Disable cycle tWDSH tWWEH tWDSS n – 1 n n + 1 DI 10-17/20-27 SWCK WE1, 2 IE1, 2 RSTW1, 2 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

Write Cycle Timing (Input Enable): MODE1 = VCC, MODE2 =VSS SWCK IE1, 2 DI 10-17/20-27 WE1, 2 RSTW1, 2 n cycle n + 1 cycle n + 3 cycle tIENH tWIEL tIENS n + 2 cycle tIDSH tWIEH tIDSS n – 1 n n + 3 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Write Cycle Timing (Write Reset): MODE1 = VCC, MODE2 =VCC DI 10-17/20-27 n cycle 0 cycle 1 cycle 2 cycle tDS tDH tRSTWS tRSTWH tWSWH tWSWL tSWC n – 1 n SWCK WE1, 2 IE1, 2 RSTW1, 2 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

Write Cycle Timing (Write Enable): MODE1 = VCC, MODE2 =VCC n cycle Disable cycle n + 1 cycle tWENH tWWEL tWENS Disable cycle tWDSH tWWEH tWDSS n – 1 n n + 1 DI 10-17/20-27 SWCK WE1, 2 IE1, 2 RSTW1, 2 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Write Cycle Timing (Input Enable): MODE1 = VCC, MODE2 =VCC SWCK IE1, 2 DI 10-17/20-27 WE1, 2 RSTW1, 2 n cycle n + 1 cycle n + 3 cycle tIENH tWIEL tIENS n + 2 cycle tIDSH tWIEH tIDSS n – 1 n n + 3 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

Write Cycle Timing (Write Reset): MODE1 = VSS, MODE2 =VSS SWCK RSTW1, 2 DI 10-17/20-27 WE1, 2 IE1, 2 n cycle 0 cycle 1 cycle 2 cycle tDS tDH n VIH VIL tRSTWS tRSTWH tWSWH tWSWL tSWC VIH VIL VIH VIL VIH VIL VIH VIL Write Cycle Timing (Write Enable): MODE1 = VSS, MODE2 =VSS SWCK WE1, 2 DI 10-17/20-27 IE1, 2 RSTW1, 2 n cycle Disable cycle n + 1 cycle tWENH tWWEL tWENS Disable cycle tWDSH tWWEH tWDS n n + 1 n VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

Write Cycle Timing (Input Enable): MODE1 = VSS, MODE2 =VSS SWCK IE1, 2 DI 10-17/20-27 WE1, 2 RSTW1, 2 n cycle n + 1 cycle n + 3 cycle tIENH tWIEL tIENS n + 2 cycle tIDSH tWIEH tIDSS n n n + 4 VIH VIL n + 3 VIH VIL VIH VIL VIH VIL VIH VIL Write Cycle Timing (Write Reset): MODE1 = VSS, MODE2 =VCC SWCK RSTW1, 2 DI 10-17/20-27 WE1, 2 IE1, 2 n cycle 0 cycle 1 cycle 2 cycle tDS tDH n VIH VIL tRSTWS tRSTWH tWSWH tWSWL tSWC VIH VIL VIH VIL VIH VIL VIH VIL

Write Cycle Timing (Write Enable): MODE1 = VSS, MODE2 =VCC SWCK WE1, 2 DI 10-17/20-27 IE1, 2 RSTW1, 2 n cycle Disable cycle n + 1 cycle tWENH tWWEL tWENS Disable cycle tWDSH tWWEH tWDS n n + 1 n VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Write Cycle Timing (Input Enable): MODE1 = VSS, MODE2 =VCC SWCK IE1, 2 DI 10-17/20-27 WE1, 2 RSTW1, 2 n cycle n + 1 cycle n + 3 cycle tIENH tWIEL tIENS n + 2 cycle tIDSH tWIEH tIDSS n n n + 4 VIH VIL n + 3 VIH VIL VIH VIL VIH VIL VIH VIL

Read Cycle Timing (Read Reset): MODE1 = VCC/VSS, MODE2 =VSS DO 10-17/20-27 SRCK RSTR1, 2 RE1, 2 OE1, 2 n cycle 0 cycle 1 cycle 2 cycle tAC tRSTRS tRSTRH tWSRH tWSRL tSRC VIH VIL n – 1 n tDDCK VIH VIL VIH VIL VIH VIL VIH VIL Read Cycle Timing (Read Enable): MODE1 = VCC/VSS, MODE2 =VSS SRCK RE1, 2 DO 10-17/20-27 OE1, 2 RSTR1, 2 n cycle Disable cycle n + 1 cycle tRENH tWREL tRENS VIH Disable cycle tRDSH tWREH tRDSS n – 1 n n + 1 VIL VIH VIL VIH VIL VIH VIL VIH VIL

Read Cycle Timing (Output Enable): MODE1 = VCC/VSS, MODE2 =VSS SRCK OE1, 2 DO 10-17/20-27 RE1, 2 RSTR1, 2 n cycle n + 1 cycle n + 3 cycle tOENH tWOEL tOENS VIH VIL n + 2 cycle tODSH tWOEH tODSS n – 1 n n + 3 Hi-Z tDECK VIH VIL VIH VIL VIH VIL VIH VIL Read Cycle Timing (Read Reset): MODE1 = VCC/VSS, MODE2 =VCC DO 10-17/20-27 SRCK RSTR1, 2 RE1, 2 OE1, 2 n cycle 0 cycle 1 cycle 2 cycle tAC tRSTRS tRSTRH tWSRH tWSRL tSRC VIH VIL n – 1 n tDDCK VIH VIL VIH VIL VIH VIL VIH VIL

Read Cycle Timing (Read Enable): MODE1 = VCC/VSS, MODE2 =VCC SRCK RE1, 2 DO 10-17/20-27 OE1, 2 RSTR1, 2 n cycle Disable cycle n + 1 cycle tREN tWREL tRENS VIH Disable cycle tRDSH tWREH tRDSS n – 1 n n + 1 VIL VIH VIL VIH VIL VIH VIL VIH VIL Read Cycle Timing (Output Enable): MODE1 = VCC/VSS, MODE2 =VCC SRCK OE1, 2 DO 10-17/20-27 RE1, 2 RSTR1, 2 n cycle n + 1 cycle n + 3 cycle tOENH tWOEL tOENS VIH VIL n + 2 cycle tODSH tWOEH tODSS n – 1 n n + 3 Hi-Z tDECK VIH VIL VIH VIL VIH VIL VIH VIL

Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). TQFP100-P-1414-0.50-K Mirror finish Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating (≥5µm) Package weight (g) 0.55 TYP. Rev. No./Last Revised 4/Oct. 28, 1996 (Unit: mm)

REVISION HISTORY

No. Date Previous Edition Current Edition

Description

Nov. 21, 2002 Final edition 1

The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.