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Issue Date: Jan 08, 2016 MR45V064B 64k(8,192-Word × 8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI GENERAL DESCRIPTION The MR45V064B is a nonvolatile 8,19 2-word x 8-bit ferroelectric ran dom access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology. The MR45V064B is accessed using Serial Peripheral Interface.Unlike SRAMs, this device, whose cells are no nvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cy cle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. The MR45V064B can be used in various applications, because the device is guaranteed for the write/read tolerance of 1012 cycles per bit and the rewrite count can be extended significantly.

FEATURES

  • 8,192-word × 8-bit configuration (Serial Peripheral Interface : SPI)
  • A single 1.8V to 3.6V （3.3 V typ） power supply
  • Operating frequency: 40MHz
  • Read/write tolerance 10 12 cycles/bit
  • Data retention 10 years
  • Guaranteed operating temperature range −40 to 85°C (Extended temperature version)
  • Package options: 8-pin plastic SOP (P-SOP8-200-1.27-T2K)

Note: Signal names that end with # indicate that the signals are negative-true logic. PIN DESCRIPTIONS Pin Name Description CS# Chip Select (input, negative logic) Latches an address by low input, activates the FeRAM, and enables a read or write operation. WP# Write Protect( input , negative logic ) Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should be fixed low or high in write-operations. HOLD# HOLD( input , negative logic ) Hold pin is used when the serial-communication suspended without disable the chip select. When HOLD# is low ,the seri al-output is in High-Z status and serial-input/serial-clock are “Donʟt Care” . CS# should be low in hold operation. SCK Serial Clock Serial Clock is the clock input pin for setti ng for serial data timing. Inputs are latched on the rising edge and output occur on the falling edge. SI Serial input SI pins are serial input pins for Operation-code , addresses ,and data-inputs . SO Serial output SO pins are serial output pins. VCC, VSS Power supply Apply the specified voltage to VCC. Connect VSS to ground. 8-pin plastic SOP CS# SO WP# VSS VCC HOLD# SCK SI 1 8 2 7 3 6 4 5 MR45V064B

SPI mode0ʢCPOL=0, CPHA=0ʣ SPI mode3ʢCPOL=1, CPHA=1ʣ STATUS REGISTER Name Function WIP Fixed to 0. WEL Write Enable Latch. This indicates internal WEL condition. BP0,BP1 Block Protect: These bits can be changed protect area. This is the software protect. SRWD Status Register Write Disable （SRWD ）: SRWD controls the effect of the hardware WP# pin. This device will be in hardware-protect by combination of SRWD and WP#. 0 Fixed to 0. SRWD 0 0 0 BP1 BP0 WEL WIP b7 b0 Status Register Write Disable Block Protect Bits Write Enable Latch Write In Progress (Always 0) CS# SCK SI LSB MSB CS# SCK SI LSB MSB

Operation codes are listed in the table below.If the device receives invalid operation code,the device will be diselected. Instruction Description Instruction format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010 FSTRD Fast Read from Memory Array 0000 1011 RDID Read device ID 1001 1111

WRENç (Write Enable) It is necessary to set Write Enable LatchʢWELʣbit before write-operation (WRITE and WRSR). WREN command sets WEL bit. WRDIç (Write Disable) WRDI command resets WEL bit. CS# SCK SI WP# Fixed “H” 0 1 2 3 4 5 6 7 SO High-Z CS# SCK SI WP# Fixed “H” 0 1 2 3 4 5 6 7 SO High-Z

RDSRç (READ Status Register) The RDSR command allows to read data of status register. WRSRç (WRITE Status Registerʣ WRSR command allows to write data to status register(SRWD,BP0,BP1). It is necessary to set Write Enable LatchʢWELʣbit by WREN command before executing WRSR. CS# SCK SI WP# Fixed “H” SO High-Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SRWD BP1 BP0 WEL WIP SRWD000 765432 1 07 CS# SCK SI SO High-Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BP0 X X 76543 2 1 0 BP1 XXXSRWD Note: WP#=Fix ”H”

READç (Read from Memory Array) READ command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial input”SI”. The inputted adresses are loaded to internal register,then the data from corresponded address is output at serial-output “SO”.If CS# will keep “L”,the internal adress will be incresed automatically after 8 clocks and will output the data from new-address.When it reaches the most significant adress,the adress counter rolls over tostarting adress,and reading cycle can be continued infinitely. FSTRDç (Fast Read from Memory Array) FSTRD command can be valid when CS# goes “L”, then the op-code and 16bit-adresses are inputted to serial input ”SI”. After 8bits for dummy byte, the data from corresponded address is output at serial-output “SO”. CS# SCK SI SO High-Z 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 A2 A1 A0 15 14 13 11 2 1 0 A11 XXX 16bit Address An A12 CS# SCK SI SO 25 26 27 28 29 30 31 32 33 34 35 38 39 m Data Out (An) Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Data Out (An+1) 36 37 Note : WP# = fixed ”H” CS# SCK SI SO High-Z 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 A2 A1 A0 15 14 13 11 2 1 0 A11 XXX 16bit Address An A12 CS# SCK SI SO 25 26 27 28 29 30 31 32 33 34 35 38 39 m Dummy Byte Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Data Out (An) 36 37 Note : WP# = fixed ”H”

WRITEç (Write to Memory Arrayʣ Write command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial input”SI”. Writing is terminated when CS# goes high af ter data-input. If CS# will keep “L”,the internal adress will be incresed automatically.When it reaches the most significant adress,the adress counter rolls over to starting adress 0000h,and writing cycle(overwriting) can be continued infinitely. WRITE (1Byte) WRITE (Page) CS# SCK SI 0 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 A2 A1 A0 15 14 13 11 2 1 0 A11 XXX 16bit Address An A12 CS# SCK SI Note : WP# = Fixed ”H” , SO=High-Z 24 25 26 27 28 29 30 31 Data Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 CS# SCK SI 0 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 A2 A1 A0 15 14 13 11 2 1 0 A11 XXX 16bit Address An A12 CS# SCK SI Note : WP# = Fixed ”H” , SO=High-Z 24 25 26 27 28 29 30 31 32 33 34 35 38 39 Data Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte 2 36 37 CS# SCK SI 40 41 42 43 44 45 46 47 Data Byte 3 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte N

Writing protection block is shown as follows: Protect Block size Block Protect BIT Protected Block Protected Address Area BP1 BP0 0 0 None None 0 1 Upper 1/4 block 1800h – 1FFFh 1 0 Upper 1/2 block 1000h – 1FFFh 1 1 All 0000h – 1FFFh Writing Protect WP# SRWD mode Writing protection status in status register Protection status in memory Protected blocks Unprotected blocks 1 0 Software protection (SPM) Status register is unprotected when WEL-bit is set by WREN command. BP0 and BP1 are unprotected. Protected Unprotected 0 0 1 1 0 1 Hardware protection (HPM) Status register is protected. BP0 and BP1 are protected. Protected Unprotected

Hold status is used for suspending serial comunication without disable the chip. SO becomes “High-Z” and SI is “Don’t care” during the hold status. It is necessary to keep CS#=L in hold status. RDID ( Read device ID) RDID command can be valid when CS# goes “L”,then th e op-code are inputted to serial input”SI”. Then 3bytes of device ID is output at serial-output “SO”. Manufacture id ( LAPIS ) device type ( MR45V064B ) 1st Byte 2 nd Byte 3 rd Byte AEh 83h 05h HOLD# SCK Hold status Hold status CS# SCK SI 0 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 1 st Byte CS# SCK SO Note : WP# = Fixed ”H” 24 25 26 27 28 29 30 31 32 33 34 35 38 39 2nd Byte 1 0 0 0 0 0 11000001 0 1 3rd Byte 36 37 SO 1 1 01 101 0 SI

ELECTRICAL CHARACTERISTICS

The application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. Therefore, do not allow actual characteristics to exceed any one parameter ratings PIN VOLTAGES Parameter Symbol Rating Unit Min. Max. Pin Voltage (Input Signal) VIN –0.5 VCC + 0.5 V Pin Voltage (Input/Output Voltage) VINQ, VOUTQ –0.5 VCC + 0.5 V Power Supply Voltage VCC –0.5 4.0 V TEMPERATURE RANGE Parameter Symbol Rating Unit Note Min. Max. Storage Temperature (Extended Temperature Version) Tstg –55 125 °C Operating Temperature (Extended Temperature Version) Topr –40 85 °C OTHERS Parameter Symbol Rating Note Power Dissipation PD 1,000mW Ta=25°C

RECOMMENDED OPERATING CONDITIONS POWER SUPPLY VOLTAGE [V] Parameter Symbol Min. Typ. Max. Note Power Supply Voltage VCC 1.8 3.3 3.6 Ground Voltage VSS 0 0 0 DC INPUT VOLTAGE [V] Parameter Symbol Min. Max. Note Input High Voltage VIH V CC x 0.7 VCC＋0.3 Input Low Voltage VIL –0.3 VCC x 0.3 OVERSHOOT/UNDERSHOOT TOLERANCE Parameter Symbol Pulse Width Peak “H” input VIH OVERSHOOT ≤ 20ns VCC+1.0V “L” input VIL UNDERSHOOT ≤ 20ns – 1.0V

DC INPUT/OUTPUT CHARACTERISTICS Parameter Symbol Condition Min. Max. Unit Note Output High Voltage VOH IOH =－2mA VCC×0.85 ― V VCCʾ2.0V VCC×0.80 ― V VCC<2.0V Output Low Voltage VOL I OL =2mA ― VCC×0.15 V Input Leakage Current ILI ― –10 10 µA Output Leakage Current ILO ― –10 10 µA POWER SUPPLY CURRENT VCC=Max.to Min, Ta=Topr Parameter Symbol Condition Max. Unit Note Power Supply Current (Standby) ICCS VIN=0.2V or VCC－0.2V 10 µA Power Supply Current (Operating) ICCA VIN=0.2V or VCC－0.2V, SCK=40MHz, IOUT=0mA 3 mA

AC CHARACTERISTICS (Read Cycle) VCC=Max. to Min., Ta=Topr. Parameter Symbol MR45V064B Unit Note Min. Max. Clock frequency fC D.C. 40 MHz CS# setup time tSLCH 10 ― ns CS# De-select time tSHSL 40 ― ns CS# hold time tCHSH 10 ― ns SCK High time tCH 11 ― ns 1 SCK Low time tCL 11 ― ns 1 Data Setup time tDVCH 5 ― ns Data Hold time tCHDX 5 ― ns SCK Low Hold time after HOLD# inactive tHHCH 10 ― ns SCK Low Hold time after HOLD# active tHLCH 10 ― ns SCK High Setup time before HOLD# active tCHHL 10 ― ns SCK High Setup time before HOLD# inactive tCHHH 10 ― ns Output disable time tSHQZ ― 12 ns 2 SCK Low to Output Valid time tCLQV ― 9 ns VCC≧2.7V ― 10 ns VCC<2.7V Output Hold time tCLQX 0 ― ns HOLD# High to Output Low impedance time tHHQX ― 20 ns 2 HOLD# High to Output High impedance time tHLQZ ― 20 ns 2 Note: 1. t CH＋tCL≧1/fC 2. sample value

CS# SCK SO SI HOLD# tCHHL tHLCH tHHCH tHHQX tCHHH tHLQZ CS# tCHSH SCK SI SO MSB IN LSB IN High Impedance tSLCH tDVCH tCHDX tSLCH tCHSH tSHSL CS# SCK SO SI Address, LSB IN tCH tCL tSHQZ tCLQV tCLQX tCLQX tCLQV LSB OUT

POWER-ON and POWER-OFF CHARACTERISTICS (Under recommended operating conditions) Parameter Symbol Min. Max. Unit Note Power-On CS# High Hold Time tVHEL 100 ⎯ ns 1, 2 Power-Off CS# High Hold Time tEHVL 0 ⎯ ns 1 Power-On Interval Time tVLVH 0 ⎯ μs 2 Power-On time tR 30 ⎯ μs/V Power-Off time tF 30 ⎯ μs/V Notes: 1. To prevent an erroneous operation, be sure to main tain CS#="H", and set the FeRAM in an inactive state (standby mode) before and after power-on and power-off. 2. Powering on at the intermediate voltage level will cau se an erroneous operation; thus, be sure to power up from 0 V. 3. Enter all signals at the same time as power-on or enter all signals after power-on. Power-On and Power-Off Sequences VIL Max. VCC Min. VCC VIH Min. CS# VIL Max. VCC Min. VCC VIH Min. CS# tVHEL tVLVH tEHVL tR tF

READ/WRITE CYCLES and DATA RETENTION (Under recommended operating conditions) Parameter Min. Max. Unit Note Read/Write Cycle 1012 ⎯ Cycle Data Retention 10 ⎯ Year CAPACITANCE Signal Symbol Min. Max. Unit Note Input Capacitance CIN ⎯ 10 pF 1 Input/Output Capacitance COUT ⎯ 10 pF 1 Note: Sampling value. Measurement conditions are V IN = VOUT = GND, f = 1MHz, and Ta = 25°C

Notes for Mounting the Surface Mount Type Package The surface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (Unit: mm)

Revision History

Document No. Date Page Description Previous Edition Current Edition FEDR45V064B-01 Jan. 08, 2016 – – Final edition 1

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