MR27V6452R

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Document overview

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Technical content

Issue Date: Aug, 21, 2012 MR27V6452R 4M-Word  16-Bit or 8M-Word  8-Bit Page mode P2ROM

FEATURES

• 4,194,304-word  16-bit/8,388,608-word  8-bit electrically switchable configuration
• Page size of 8-word x 16-Bit or 16-word x 8-Bit
• Access time 3.0 V to 3.6 V power supply 80ns MAX
• Input/Output TTL compatible
• Three-state output PACKAGES
• MR27V6452R-xxxTN 48-pin plastic TSOP (TSOP(1) 48-P-1220-0.50-1K)
• MR27V6452R-xxxTA 56-pin plastic TSOP (P-TSOP(1)I56-1420-0.50-K) P2ROM ADVANCED TECHNOLOGY P2ROM stands for Production Programmed ROM. This exclusive LAPIS Semiconductor’s technology utilizes factory test equipment for programming the customers code into the P2ROM prior to final production testing. Advancements in this technology allows production costs to be equivalent to MASKROM and has many advantages and added benefits over the other non-volatile technologies, which include the following;
• Short lead time , since the P2ROM is programmed at the final stage of the production process, a large P2ROM inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive lead-time and minimize liability as a custom product. A17 NC A18 NC A21 R ESET# NC A20 A19 A10 A11 A12 A13 A14 A15 CE VSS OE# D10 D11 V CC D12 D13 D14 D15/A–1 V SS BY TE# A16 1 56TSOP(Type-I) *:Different from FLASH products. NC NC A15 A14 A13 A12 A11 A10 A19 A20 NC RESET# A21 NC NC A18 A17 NC NC NC NC A16 BYTE# V SS D15/A-1 D14 D13 D12 V CC D11 D10 OE# V SS CE# NC NC* 48TSOP(Type-I) PIN CONFIGURATION (TOP VIEW) No mask charge , since P2ROMs do not utilize a custom mask for storing customer code, no mask charges apply.
• No additional programming charge, unlike Flash and OTP that require additional programming and handling costs, the P2ROM al ready has the code loaded at the factory with minimal effect on the production throughput. The cost is included in the unit price.
• Custom Marking is available at no additional charge. PDD C400807DC400758 1/11

CE# BYTE# RESET# CE RESET × 8/× 16 Switch D0 D2 D4 D6 D8 D10 D12 D14 D1 D3 D5 D7 D9 D11 D13 D15 Memory Cell Matrix 8M × 16-Bit or 16M × 8-Bit Multiplexer Output Buffer Row Decoder Column Decoder Address Buffer In 8-bit output mode, these pins are placed in a high-Z state and pin D15 functions as the A-1 address pin. A–1 OE# OE PIN DESCRIPTIONS Pin name Functions D15 / A–1 Data output / Address input A0 to A21 Address inputs D0 to D14 Data outputs CE# Chip enable input OE# Output enable input BYTE# Word / Byte select input RESET# Hardware Reset VCC Power supply voltage VSS Ground PDD C400807DC400758 2/11

Mode CE# OE# RESET# BYTE# VCC D0 to D7 D8 to D14 D15 /A–1 Read (16-Bit) L L H H D OUT Read (8-Bit) L L H L D OUT Hi–Z L/H H H Output disable L H H L Hi–Z H H Standby H  H L Hi–Z H Reset H H L L 3.0 V to 3.6 V Hi–Z : Don’t Care (H or L) ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Value Unit Operating temperature under bias Ta -40 to 85 °C Storage temperature Tstg –55 to 125 °C Input voltage VI –0.5 to VCC+0.5 V Output voltage VO –0.5 to VCC+0.5 V Power supply voltage VCC relative to VSS –0.5 to 5 V Power dissipation per package PD Ta = 25°C 1.0 W Output short circuit current IOS — 10 mA RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85°C) Parameter Symbol Conditio n Min. Typ. Max. Unit VCC power supply voltage VCC 3.0 — 3.6 V Input “H” level VIH 2.4 — VCC+0.5 V Input “L” level VIL VCC = 3.0 to 3.6 V –0.5 — 0.6 V Voltage is relative to VSS.  : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.  : -1.5V (Min.) when pulse width of undershoot is less than 10ns. PIN CAPACITANCE (VCC = 3.0 V, Ta = 25°C, f = 1 MHz) Parameter Symbol Conditio n Min. Typ. Max. Unit Input C IN1 — — 10 BYTE# C IN2 VI = 0 V — — 200 Output C OUT V O = 0 V — — 10 pF PDD C400807DC400758 3/11

ELECTRICAL CHARACTERISTICS

(VCC = 3.0 to 3.6 V, Ta = -40 to 85°C) Parameter Symbol Conditio n Min. Typ. Max. Unit Input leakage current ILI V I = 0 to VCC — — 10 A Output leakage current ILO V O = 0 to VCC — — 10 A ICCSC CE# = VCC — — 10 A VCC power supply current (Standby) ICCST CE# = VIH — — 1 mA VCC power supply current (Read) ICCA CE# = VIL, OE# = VIH f=5MHz — — 50 mA Input “H” level VIH — 2.4 — VCC+0.5 V Input “L” level VIL — –0.5 — 0.6 V Output “H” level VOH I OH = –1 mA 2.4 — — V Output “L” level VOL I OL = 2 mA — — 0.4 V Voltage is relative to VSS.  : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.  : -1.5V (Min.) when pulse width of undershoot is less than 10ns. PDD C400807DC400758 4/11

(VCC = 3.0 to 3.6 V, Ta = -40 to 85°C) Parameter Symbol Condit ion Min. Max. Unit Address cycle time tC — 80 — ns Address access time tACC CE# = OE# = VIL — 80 ns Page cycle time tPC — 25 — ns Page access time tPAC — — 25 ns CE# access time tCE OE# = VIL — 80 ns CE# high pulse width tCEH — 0 — ns OE# access time tOE CE# = VIL — 25 ns tCHZ OE# = VIL 0 20 ns Output disable time tOHZ CE# = VIL 0 20 ns Output hold time tOH CE# = OE# = VIL 0 — ns Note ： 1. Using continuous address/CE# input cycle less than t C(80ns), MR27V6452R may not work correctly. 2. t CEH is not restricted. Measurement conditions Output load Output 30 pF (Including scope and jig) >80ns address CE# >80nstCEH PDD C400807DC400758 5/11

TIMING CHART (READ CYCLE) RANDOM ACCESS MODE READ CYCLE CE# OE# D0 to D15(Word mode) tC tCE tOE tOH tCHZ tOHZ Valid Data Hi-Z Hi-Z tOH Valid Data tACC tACC A-1 to A21 (Byte mode) A0 to A21 (Word mode) D0 to D7(Byte mode) D8 to D15 : Hi-Z(Byte mode) PAGE ACCESS MODE READ CYCLE RESET# High A3 to A21 tC tCE tOE tACC tOH tCHZ tOHZ Hi-Z Hi-Z D0 to D7(Byte mode) A-1 to A2 (Byte mode) A0 to A2 (Word mode) CE# OE# D0 to D15(W ord mode) D8 to D15 : Hi-Z(Byte mode) tPAC Valid Data Valid Data Valid Data tPC tPC tPAC High RESET# PDD C400807DC400758 6/11

ymbol Condition Min. Max. Unit RESET# Pulse Width tRP — 100 — ns Reset# - CE# hold time tRCH — 100 — ns *During reset period CE# and OE# must be at logical high state. Parameter Symbol Conditio n Min. Max. Unit Vcc setup time tVCS — 35 — s Reset# - CE# setup time tRCS — 100 — ns Reset# - CE# hold time tRCH — 100 — ns *Max imum Vcc power up current is IccA (RESET#=VIL) Vcc CE# tRCH tVCS RESET# 2.7V tRCS Read mode RESETE# CE# OE# tRCHtRP HARDWARE RESET POWER-UP SEQUENCE PDD C400807DC400758 7/11

(Unit: mm) TSOP(1)48-P-1220-0.50-1K Mirror finish Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating (≥5μm) Package weight (g) 0.55 TYP.5 Rev. No./Last Revised 1/Dec. 2, 1999 Note s for Mounting the Surface Mount Type Package The surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform refl ow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (Unit: mm) PDD C400807DC400758 8/11

Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounti ng conditions (reflow me thod, temperature and times). PDD C400807DC400758 9/11

REVISION HISTORY

No. Date Previous Edition Current Edition

Description

FEDM27V6452R-002-01 Aug, 21, 2012 – – Final edition 1 PDD C400807DC400758 10/11

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