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Issue Date: Oct. 01, 2008 MR27V3252J 2M–Word × 16–Bit or 4M–Word × 8–Bit Page Mode P2ROM

FEATURES

48TSOP(Type-I) PIN CONFIGURATION (TOP VIEW) A CE# V SS OE# D10 D11 NC A A 44SOP A A16 BYT A VSS A D 15/A–1 A A D A A D A BYT D VSS D 15/A–1 VCC D D D D D VCC VSS CE# OE

  • 2,097,152-word × 16-bit / 4,194,304-word × 8-bit electrically switchable configuration
  • Page size of 8-word x 16-Bit or 16-word x 8-Bit
  • 3.0 V to 3.6 V power supply
  • Input/Output TTL compatible
  • Three-state output PACKAGES
  • MR27V3252J-xxxMA 44-pin plastic SOP (SOP44-P-600-1.27-K)
  • MR27V3252J-xxxTN 48-pin plastic TSOP (TSOP I 48-P-1220-0.50-1K) P2ROM ADVANCED TECHNOLOGY P2ROM stands for Production Programmed ROM. This exclusive LAPIS Semiconductor technology utilizes factory test equipment for programming the customers code into the P2ROM prior to final production testing. Advancements in this technology allows production costs to be equivalent to MASKROM and has many advantages and added benefits over the other non-volatile technologies, which include the following;
  • Short lead time , since the P2ROM is programmed at the final stage of the production process, a large P2ROM inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive lead-time and minimize liability as a custom product.
  • No mask charge , since P2ROMs do not utilize a custom mask for storing customer code, no mask charges apply.
  • No additional programming charge, unlike Flash and OTP that require additional programming and handling costs, the P2ROM already has the code loaded at the factory with minimal effect on the production throughput. The cost is included in the unit price.
  • Custom Marking is available at no additional charge.

CE# BYTE# OE# CE OE × 8/× 16 Switch D0 D2 D4 D6 D8 D10 D12 D14 D1 D3 D5 D7 D9 D11 D13 D15 Memory Cell Matrix 2M × 16-Bit or 4M × 8-Bit Multiplexer Output Buffer Row Decoder Column Decoder Address Buffer In 8-bit output mode, these pins are placed in a high-Z state and pin D15 functions as the A-1 address pin. A–1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 PIN DESCRIPTIONS Pin name Functions D15 / A–1 Data output / Address input A0 to A20 Address inputs D0 to D14 Data outputs CE# Chip enable input OE# Output enable input BYTE# Word / Byte select input VCC Power supply voltage VSS Ground NC No connect

Mode CE# OE# BYTE# VCC D0 to D7 D8 to D14 D15/A–1 Read (16-Bit) L L H DOUT Read (8-Bit) L L L DOUT Hi–Z L/H H Output disable L H L Hi–Z H Standby H ∗ L 3.3 V Hi–Z ∗: Don’t Care (H or L) ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Value Unit Operating temperature under bias Ta 0 to 70 °C Storage temperature Tstg –55 to 125 °C Input voltage VI –0.5 to VCC+0.5 V Output voltage VO –0.5 to VCC+0.5 V Power supply voltage VCC relative to VSS –0.5 to 5 V Power dissipation per package PD Ta = 25°C 1.0 W Output short circuit current IOS — 10 mA RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70°C) Parameter Symbol Condition Min. Typ. Max. Unit VCC power supply voltage VCC 3.0 — 3.6 V Input “H” level VIH 2.2 — VCC+0.5∗ V Input “L” level VIL VCC = 3.0 to 3.6 V –0.5∗∗ — 0.6 V Voltage is relative to VSS. ∗ : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns. ∗∗ : -1.5V (Min.) when pulse width of undershoot is less than 10ns. PIN CAPACITANCE (VCC = 3.3 V, Ta = 25°C, f = 1 MHz) Parameter Symbol Condition Min. Typ. Max. Unit Input C IN1 — — 8 BYTE# C IN2 VI = 0 V — — 200 Output C OUT V O = 0 V — — 10 pF

ELECTRICAL CHARACTERISTICS

(VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C) Parameter Symbol Condition Min. Typ. Max. Unit Input leakage current ILI V I = 0 to VCC — — 5 μA Output leakage current ILO V O = 0 to VCC — — 5 μA ICCSC CE# = VCC — — 10 μA VCC power supply current (Standby) ICCST CE# = VIH — — 1 mA VCC power supply current (Read) ICCA1 OE# = VIH, f = 10MHz — — 50 mA Input “H” level VIH — 2.2 — VCC+0.5∗ V Input “L” level VIL — –0.5∗∗ — 0.6 V Output “H” level VOH I OH = –1 mA 2.4 — — V Output “L” level VOL I OL = 2 mA — — 0.4 V Voltage is relative to VSS. ∗ : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns. ∗∗ : -1.5V (Min.) when pulse width of undershoot is less than 10ns. AC Characteristics (VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C) Parameter Symbol Condition Min. Max. Unit Address cycle time tC — 70 — ns Address access time tACC CE# = OE# = VIL — 70 ns Page cycle time tPC — 25 — ns Page access time tPAC — — 25 ns CE# access time tCE OE# = VIL — 70 ns OE# access time tOE CE# = VIL — 25 ns tCHZ OE# = VIL 0 20 ns Output disable time tOHZ CE# = VIL 0 20 ns Output hold time tOH CE# = OE# = VIL 0 — ns Measurement conditions Output load Output 50 pF (Including scope and jig)

TIMING CHART (READ CYCLE) RANDOM ACCESS MODE READ CYCLE Address CE# OE# Dout tC tCE tOE tOH Va ta tCHZ tOHZ lid Da Hi -Z Hi-Z tOH tACC Va talid Da tACC tC PAGE ACCESS MODE READ CYCLE A3 to A20 tC tCE tOE tACC tOH tCHZ tOHZ Hi-Z Hi-Z Dout tPAC A-1 to A2 (Byte mode) tPC tPC tPAC A0 to A2 (Word mode) CE# OE#

(Unit: mm) No tes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

(Unit: mm) No tes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

REVISION HISTORY

No. Date Previous Edition Current Edition

Description

FEDR27V3252J-02-01 Jun. 17, 2003 – – Final edition 1 FEDR27V3252J-02-02 Jul. 9, 2004 3 3 Add PD condition and IOS = 10mA FEDR27V3252J-002-02 Oct.1, 2008 – – Changed company logo and name to OKI SEMICONDUCTOR

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