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Issue Date: Oct. 23, 2013 MR45V032A 32k(4,096-Word 8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI GENERAL DESCRIPTION The MR45V032A is a nonvolatile 4,096-word x 8-bit ferroelectric random access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology. The MR 45V032A is accessed using Serial Peripheral Interface.Unlike SRAMs, this device, whose cells are no nvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cy cle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. The MR45V032A can be used in various applications, because the device is guaranteed for the write/read tolerance of 10 12 cycles per bit and the rewrite count can be extended significantly.
FEATURES
- 4,096-word 8-bit configuration (Serial Peripheral Interface : SPI)
- A single 2.7V～3.6V （3.3 V typ） p o w e r s u p p l y
- Operating frequency: 15MHz
- Read/write tolerance 10 12 cycles/bit
- Data retention 10 years
- Guaranteed operating temperature range 40 to 85C (Extended temperature version)
- Package options: 8-pin plastic SOP (P-SOP8-200-1.27-T2K)
Note: Signal names that end with # indicate that the signals are negative-true logic. 8-pin plastic SOP CS# SO WP# VSS VCC HOLD# SCK SI 1 8 2 7 3 6 4 5 MR45V032A
CS# Chip Select (input, negative logic) Latches an address by low input, activates the FeRAM, and enables a read or write operation. WP# Write Protect( input , negative logic ) Write Protect pin controls write-operation to the status-regist er(BP0,BP1). This pin should be fixed low or high in write-operations. HOLD# HOLD( input , negative logic ) Hold pin is used when the serial-communication suspended without disable the chip select. When HOLD# is low ,the seri al-output is in High-Z status and serial-input/serial-clock are “Don’t Care” . CS# should be low in hold operation. SCK Serial Clock Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on the rising edge and output occur on the falling edge. SI Serial input SI pins are serial input pins for Operation-code , addresses ,and data-inputs . SO Serial output SO pins are serial output pins. VCC, VSS Power supply Apply the specified voltage to VCC. Connect VSS to ground.
SPI mode0（CPOL=0, CPHA=0） SPI mode3（CPOL=1, CPHA=1） Status Register Status Register data are volatile. Set Status Register data by WRSR(Write status register) command, after power on. Name Function WIP Fixed to 0. WEL Write Enable Latch. This indicates internal WEL condition. BP0,BP1 Block Protect :These bits can be changed protect area . This is the software protect. SRWD Status Register Write Disable （SRWD ）: SRWD controls the effect of the hardware WP# pin. This device will be in hardware-protect by combination of SRWD and WP#. 0 Fixed to 0. SRWD 0 0 0 BP1 BP0 WEL WIP b7 b0 Status Register Write Disable Block Protect Bits Write Enable Latch Write In Progress (Always 0) CS# SCK SI LSBMSB CS# SCK SI LSB MSB
Operation codes are listed in the table below.If the device receives invalid operation code,the device will be diselected. Instruction Descriptio n Instruction format WREN Write Enable 0000 0110 WRDI Write Disable 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array 0000 0011 WRITE Write to Memory Array 0000 0010
WREN(Write Enable) It is necessary to set Write Enable Latch（WEL）bit before write-operation (WRITE and WRSR). WREN command sets WEL bit. WRDI(Write Disable) WRDI command resets WEL bit. CS# SCK SI WP# Fixed “H” 01 23456 7 SO High-Z CS# SCK SI WP# Fixed “H” 0 1 2 3 4 5 6 7 SO High-Z
RDSR(READ Status Register) The RDSR command allows to read data of status register. WRSR(WRITE Status Register） WRSR command allows to write data to status register(SRWD,BP0,BP1). It is necessary to set Write Enable Latch（WEL）bit by WREN command before executing WRSR. CS# SCK SI WP# Fixed “H” SO High-Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SRWD BP1 BP0 WEL WIP SRWD000 76543 2 1 07 CS# SCK SI SO High-Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BP0 X X 76543 2 1 0 BP1 X X XSRWD Note: WP#=Fix ”H”
READ(Read from Memory Array) READ command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial input”SI”. The inputted adresses are loaded to internal register,then the data from corresponded address is output at serial-output “SO”.If CS# will keep “L”,the internal adress will be incresed automatically after 8 clocks and will output the data from new-address.When it reaches the most significant adress,the adress counter rolls over tostarting adress,and reading cycle can be continued infinitely. CS# SCK SI SO High-Z 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 A2 A1 A0 15 14 13 11 2 1 0 A11 X XX 16bit Address An X CS# SCK SI SO 25 26 27 28 29 30 31 32 33 34 35 38 39 m Data Out (An) Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Data Out (An+1) Qx 36 37 Note : WP# = fixed ”H”
WRITE(Write to Memory Array） Write command can be valid when CS# goes “L”,then the op-code and 16bit-adresses are inputted to serial input”SI”. Writing is terminated when CS# goes high af ter data-input. If CS# will keep “L”,the internal adress will be incresed automatically.When it reaches the most significant adress,the adress counter rolls over to starting adress 0000h,and writing cycle(overwriting) can be continued infinitely. WRITE(1Byte) WRITE(Page) CS# SCK SI 0 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 A2 A1 A0 15 14 13 11 2 1 0 A11 X XX 16bit Address An X CS# SCK SI Note : WP# = Fixed ”H” , SO=High-Z 24 25 26 27 28 29 30 31 Data Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 CS# SCK SI 0 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 A2 A1 A0 15 14 13 11 2 1 0 A11 X XX 16bit Address An X CS# SCK SI Note : WP# = Fixed ”H” , SO=High-Z 24 25 26 27 28 29 30 31 32 33 34 35 38 39 Data Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte 2 36 37 CS# SCK SI 40 41 42 43 44 45 46 47 Data Byte 3 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte N
Writing protection block is shown as follows: Protect Block size Block Protect BIT BP1 BP0 Protected Block Protected Address Area 0 0 None None 0 1 Upper 1/4 block C00h – FFFh 1 0 Upper 1/2 block 800h – FFFh 1 1 All 000h – FFFh Writing Protect Protection status in memory WP# SRWD mode Writing protection status in status register Protected blocks Unprotected blocks 1 0 0 0 1 1 Software protection (SPM) Status register is unprotected when WEL-bit is set by WREN command. BP0 and BP1 are unprotected. Protected Unprotected 0 1 Hardware protection (HPM) Status register is protected. BP0 and BP1 are protected. Protected Unprotected
Hold status is used for suspending serial comunication without disable the chip. SO becomes “High-Z” and SI is “Don’t care” during the hold status. It is necessary to keep CS#=L in hold status. HOLD# SCK Hold status Hold status
ELECTRICAL CHARACTERISTICS
pplication of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. Therefore, do not allow actual characteristics to exceed any one parameter ratings Pin voltages Rating Parameter Symbol Min. Max. Unit Pin Voltage (Input Signal) VIN –0.5 VCC + 0.5 V Pin Voltage (Input/Output Voltage) VINQ, VOUTQ –0.5 VCC + 0.5 V Power Supply Voltage VCC –0.5 4.0 V Temperature Range Rating Parameter Symbol Min. Max. Unit Note Storage Temperature (Extended Temperature Version) Tstg –55 125 °C Operating Temperature (Extended Temperature Version) Topr –40 85 °C Others Parameter Symbol Rating Unit Power Dissipation PD 1,000mW Allowable Input Current IIN +/- 20mA Ta=25°C Allowable Output Current IOUT +/- 20mA Ta=25°C
Recommended Operating Conditions Power Supply Voltage [V] Parameter Symbol Min. Typ. Max. Note Power Supply Voltage VCC 2.7 3.3 3.6 Ground Voltage VSS 0 0 0 DC Input Voltage [V] Parameter Symbol Min. Max. Note Input High Voltage VIH V CC x 0.8 VCC＋0.3 Input Low Voltage VIL –0.3 VCC x 0.2 Overshoot/Undershoot tolerance Parameter Symbol Pulse Width Peak “H” input VIH OVERSHOOT 20ns VCC+1.0V “L” input VIL UNDERSHOOT 20ns – 1.0V
DC Input/Output Characteristics Parameter Symbol Condition Min. Max. Unit Note Output High Voltage VOH IOH =－2mA VCC 0.85 ― V Output Low Voltage VOL I OL =2mA ― VCC 0.15 V Input Leakage Current ILI ― –10 10 µA Output Leakage Current ILO ― –10 10 µA Power Supply Current VCC=Max.to Min, Ta=Topr Parameter Symbol Condition Max. Unit Note Power Supply Current (Standby) ICCS VIN=0.2V or VCC－0.2V 400 µA Power Supply Current (Operating) ICCA VIN=0.2V or VCC－0.2V, SCK=15MHz, IOUT=0mA 10 mA
AC Characteristics (Read Cycle) VCC=Max. to Min., Ta=Topr. MR45V032A Parameter Symbol Min. Max. Unit Note Clock frequency fC D.C. 15 MHz CS# Active setup time tSLCH 10 ― ns CS# In-active setup-time tSHCH 10 ― ns CS# De-select time tSHSL 10 ― ns CS# Active hold time tCHSH 10 ― ns CS# In-active hold-time tCHSL 10 ― ns SCK High time tCH 30 ― ns 1 SCK Low time tCL 30 ― ns 1 SCK Rise time tCLCH ― 1 ns 2 SCK Fall time tCHCL ― 1 ns 2 Data Setup time tDVCH 5 ― ns Data Hold time tCHDX 5 ― ns SCK Low Hold time after HOLD# inactive tHHCH 10 ― ns SCK Low Hold time after HOLD# active tHLCH 10 ― ns SCK High Setup time before HOLD# active tCHHL 10 ― ns SCK High Setup time before HOLD# inactive t CHHH 10 ― ns Output disable time tSHQZ ― 20 ns 2 SCK Low to Output Valid time tCLQV ― 35 ns Output Hold time tCLQX 0 ― ns Output Rise time tQLQH ― 50 ns 2 Output Fall time tQHQL ― 50 ns 2 HOLD# High to Output Low impedance time tHHQX ― 20 ns 2 HOLD# High to Output High impedance time tHLQZ ― 20 ns 2 Note: 1. t CH＋tCL≧1/fC 2. sample value
CS# tCHSL SCK SI SO MSB IN LSB IN High Impedance tSLCH tDVCH tCHDX tCLCH tCHCL tSHCH tCHSH tSHSL CS# SCK SO SI HOLD# tCHHL tHLCH tHHCH tHHQX tCHHH tHLQZ CS# SCK SO SI Address, LSB IN tCH tCL tSHQZ tCLQV tCLQX tCLQX tCLQV tQLQH tQHQL LSB OUT
Power-On and Power-Off Characteristics (Under recommended operating conditions) Parameter Symbol Min. Max. Unit Note Power-On CS# High Hold Time tVHEL 20 s 1, 2 Power-Off CS# High Hold Time tEHVL 100 ns 1 Power-On Interval Time tVLVH 1 s 2 Power-On time tR 50 s/V Power-Off time tF 100 s/V Notes: 1. To prevent an erroneous operation, be sure to main tain CS#="H", and set the FeRAM in an inactive state (standby mode) before and after power-on and power-off. 2. Powering on at the intermediate voltage level will cau se an erroneous operation; thus, be sure to power up from 0 V. 3. Enter all signals at the same time as power-on or enter all signals after power-on. Power-On and Power-Off Sequences VIL Max. VCC Min. VCC VIH Min. CS# VIL Max. VCC Min. VCC VIH Min. CS# tVHEL tVLVH tEHVL tR tF
Read/Write Cycles and Data Retention (Under recommended operating conditions) Parameter Min. Max. Unit Note Read/Write Cycle 1012 Cycle Data Retention 10 Year Capacitance Signal Symbol Min. Max. Unit Note Input Capacitance CIN 10 pF 1 Input/Output Capacitance COUT 10 pF 1 Note: Sampling value. Measurement conditions are V IN = VOUT = GND, f = 1MHz, and Ta = 25°C
Notes for Mounting the Surface Mount Type Package The surface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (Unit: mm)
REVISION HISTORY
Document No. Date Previous Edition Current Edition
Description
FEDR45V032A-01 Oct. 23, 2013 – – Final edition 1
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