MR2A16A | DigiCamel IC Datasheet

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MR2A16A EVERSPIN | Alldatasheet

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Technical content

Fast 35 ns Read/Write cycle
SRAM compatible timing, uses existing SRAM control- lers without redesign
Unlimited Read & Write endurance
Data non-volatile for >20 years at temperature
One memory replaces Flash, SRAM, EEPROM and BBSRAM in a system for simpler, more efficient design
Replaces battery-backed SRAM solutions with MRAM to improve reliability
3.3 volt power supply
Automatic data protection on power loss
Commercial, Industrial, Extended temperatures
AEC-Q100 Grade 1 option
All products meet MSL-3 moisture sensitivity level
RoHS-compliant SRAM TSOP2 and BGA Packages The MR2A16A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device orga- nized as 262,144 words of 16 bits. The MR2A16A offers SRAM compatible 35 ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20 years. Data is automati- cally protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR2A16A is the ideal memory solution for applications that must permanently store and re- trieve critical data and programs quickly. The M2A16A is available in a small footprint 48-pin ball grid array (BGA) package and a 44-pin thin small outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and other nonvolatile RAM products. The MR2A16A provides highly reliable data storage over a wide range of temperatures. The prod- uct is offered with Commercial (0 to +70 °C), Industrial (-40 to +85 °C), Extended (-40 to +105 °C), and AEC-Q100 Grade 1 (-40 to +125 °C) operating temperature range options. RoHS

FEATURES

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 MR2A16A Figure 1 – Block Diagram Table 1 – Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable UB Upper Byte Enable LB Lower Byte Enable DQ Data I/O VDD Power Supply VSS Ground DC Do Not Connect NC No Connection BLOCK DIAGRAM AND PIN ASSIGNMENTS

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 DQL0 DQL1 VDD E VSS DQL2 DQL3 W A₁₅ G DQL7 DQL6 VSS VDD DQL5 DQL4 A₁₄ A₁₃ A₁₂ A₁₁ A₁₀ DC A₁₇ A₁₆ UB LB DQU15 DQU14 DQU13 DQU12 DQU11 DQU10 DQU9 DQU8 1 2 3 4 5 6 LB G A0 A1 A2 NC A DQU8 UB A3 A4 E DQL0 B DQU9 DQU10 A5 A6 DQL1 DQL2 C VSS DQU11 A15 DQL3 VDD D VDD DQU12 NC A16 DQL4 VSS E DQU14 DQU13 A14 A13 DQL5 DQL6 F DQU15 NC A10 A17 A11 W DQL7 G NC A9A8 A12 DC H Figure 2 – Pin Diagrams for Available Packages (Top View) 44-Pin TSOP Type2 48-Pin BGA Table 2 – Operating Modes E 1 G1 W 1 LB 1 UB1 Mode VDD Current DQL[7:0]2 DQU[15:8]2 H X X X X Not selected ISB1, ISB2 Hi-Z Hi-Z L H H X X Output disabled IDDR Hi-Z Hi-Z L X X H H Output disabled IDDR Hi-Z Hi-Z L L H L H Lower Byte Read IDDR DOut Hi-Z L L H H L Upper Byte Read IDDR Hi-Z DOut L L H L L Word Read IDDR DOut DOut L X L L H Lower Byte Write IDDW Din Hi-Z L X L H L Upper Byte Write IDDW Hi-Z Din L X L L L Word Write IDDW Din Din Notes: 1. H = high, L = low, X = don’t care 2. Hi-Z = high impedance

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 MR2A16A This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. 1 Table 3 – Absolute Maximum Ratings Symbol Parameter Temp Range Package Value Unit VDD Supply voltage 2 - - -0.5 to 4.0 V VIN Voltage on any pin 2 - - -0.5 to VDD + 0.5 V IOUT Output current per pin - - ±20 mA TBIAS Temperature under bias Commercial - -10 to 85 Industrial - -45 to 95 Extended - -45 to 110 AEC-Q100 Grade 1 - -45 to 130 Tstg Storage Temperature - - -55 to 150 °C TLead Lead temperature during solder (3 minute max) - - 260 °C Hmax_write Maximum magnetic field during write Commercial TSOP2, BGA 2,000 A/mIndustrial, Extended BGA 2,000 TSOP2 10,000 AEC-Q100 Grade 1 TSOP2 2,000 Hmax_read Maximum magnetic field during read or standby Commercial TSOP2, BGA 8,000 A/mIndustrial, Extended BGA 8,000 TSOP2 10,000 AEC-Q100 Grade 1 TSOP2 8,000 Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability depends on package characteristics and use environment. ABSOLUTE MAXIMUM RATINGS

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 Parameter Symbol Min Typical Max Unit Power supply voltage 1 VDD 3.0 3.3 3.6 V Write inhibit voltage VWI 2.5 2.7 3.0 1 V Input high voltage VIH 2.2 - VDD + 0.3 2 V Input low voltage VIL -0.5 3 - 0.8 V Temperature under bias MR2A16A (Commercial) MR2A16AC (Industrial) MR2A16AV (Extended) MR2A16AM (AEC-Q100 Grade 1) 4 TA -40 -40 -40 105 125 Notes: 1. There is a 2 ms startup time once VDD exceeds VDD,(max). See “Power Up and Power Down Sequencing” on page 8. 4. AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2 years out of 20 years life.) OPERATING CONDITIONS

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 MR2A16A The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). Figure 3 – Power Up and Power Down Sequencing Timing Diagram BROWNOUT or POWER LOSS NORMAL OPERATION VDD READ/WRITE INHIBITED VWI 2 ms READ/WRITE INHIBITED VIH STARTUP NORMAL OPERATION 2 ms E W RECOVER VIH Power Up and Power Down Sequencing

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 Parameter Symbol Min Typical Max Unit Input leakage current Ilkg(I) - - ±1 μA Output leakage current Ilkg(O) - - ±1 μA Output low voltage (IOL = +4 mA) (IOL = +100 μA) VOL - - 0.4 VSS + 0.2 V Output high voltage (IOH = -4 mA) (IOH = -100 μA) VOH 2.4 VDD - 0.2 - - V Table 4 – DC Characteristics Table 5 – Power Supply Characteristics Parameter Symbol Typical Max Unit AC active supply current - read modes1 (IOUT= 0 mA, VDD= max) IDDR 55 80 mA AC active supply current - write modes1 (VDD= max) Commercial Grade Industrial Grade Extended Grade AEC-Q100 Grade IDDW 105 105 105 105 155 165 165 165 mA AC standby current (VDD= max, E = VIH) no other restrictions on other inputs ISB1 18 28 mA CMOS standby current (E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD - 0.2 V) (VDD = max, f = 0 MHz) ISB2 9 12 mA Notes: 1. All active current measurements are measured with one address transition per cycle and at minimum cycle time. DC CHARACTERISTICS

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 MR2A16A Table 9 – Write Cycle Timing 1 (W Controlled) Parameter 1 Symbol Min Max Unit Write cycle time 2 tAVAV 35 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 18 - ns Address valid to end of write (G low) tAVWH 20 - ns Write pulse width (G high) tWLWH tWLEH 15 - ns Write pulse width (G low) tWLWH tWLEH 15 - ns Data valid to end of write tDVWH 10 - ns Data hold time tWHDX 0 - ns Write low to data Hi-Z 3 tWLQZ 0 12 ns Write high to output active 3 tWHQX 3 - ns Write recovery time tWHAX 12 - ns Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given voltage or temperate, tWLQZ(max) < tWHQX(min) W (WRITE ENABLE) A (ADDRESS) E (CHIP ENABLE) t AVAV t AVWH t WHAX t AVWL t WLEH t WLWH DATA VALID t DVWH t WHDX Q (DATA OUT) D (DATA IN) t WLQZ t WHQX Hi -Z Hi -Z Figure 8 – Write Cycle Timing 1 (W Controlled) Write Mode

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 Table 10 – Write Cycle Timing 2 (E Controlled) Figure 9 – Write Cycle Timing 2 (E Controlled) Parameter 1 Symbol Min Max Unit Write cycle time 2 tAVAV 35 - ns Address set-up time tAVEL 0 - ns Address valid to end of write (G high) tAVEH 18 - ns Address valid to end of write (G low) tAVEH 20 - ns Enable to end of write (G high) tELEH tELWH 15 - ns Enable to end of write (G low) 3 tELEH tELWH 15 - ns Data valid to end of write tDVEH 10 - ns Data hold time tEHDX 0 - ns Write recovery time tEHAX 12 - ns Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) Q (DATA OUT) D (DATA IN) tAVAV tAVEH tEHAX tELEH tEHDXtDVEH tAVEL Hi-Z tELWH Data Valid UB, LB (BYTE ENABLE)

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 MR2A16A Parameter 1 Symbol Min Max Unit Write cycle time 2 tAVAV 35 - ns Address set-up time tAVBL 0 - ns Address valid to end of write (G high) tAVBH 18 - ns Address valid to end of write (G low) tAVBH 20 - ns Write pulse width (G high) tBLEH tBLWH 15 - ns Write pulse width (G low) tBLEH tBLWH 15 - ns Data valid to end of write tDVBH 10 - ns Data hold time tBHDX 0 - ns Write recovery time tBHAX 12 - ns Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or LB/UB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. Figure 10 – Write Cycle Timing 3 (LB / UB Controlled) W (WRITE ENABLE) A (ADDRESS) E (CHIP ENABLE) UB, LB (BYTE ENABLED) t AVAV t AVEH t BHAX t AVBL t BLEH t BLWH Data Valid t DVBH t BHDX Q (DATA OUT) D (DATA IN) Hi -Z Hi -Z Table 11 – Write Cycle Timing 3 (LB / UB Controlled)

ORDERING INFORMATION

Memory Density Type I/O Width Rev. Temp Package Speed Packing Grade Example Ordering Part Number MR 2 A 16 A C MA 35 R MRAM MR

256 Kb 256

1 Mb 0

4 Mb 2

16 Mb 4

Async 3.3v A Async 3.3v Vdd and 1.8v Vddq D Async 3.3v Vdd and 1.8v Vddq with 2.7v min. Vdd DL 8-bit 8 16-bit 16 Rev A A Rev B B Commercial 0 to 70°C Blank Industrial -40 to 85°C C Extended -40 to 105°C V AEC Q-100 Grade 1 -40 to 125°C M 44-TSOP-2 YS 48-FBGA MA 16-SOIC SC 32-SOIC SO 35 ns 35 45 ns 45 Tray Blank Tape and Reel R Engineering Samples ES Customer Samples Blank Mass Production Blank Table 12 – Ordering Part Number System for Parallel I/O MRAM

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 MR2A16A Table 13 – MR2A16A Ordering Part Numbers Temp Grade Temp Package Shipping Ordering Part Number Commercial 0 to +70 °C 44-TSOP2 Tray MR2A16AYS35 Tape and Reel MR2A16AYS35R 48-BGA Tray MR2A16AMA35 Tape and Reel MR2A16AMA35R Industrial -40 to +85 °C 44-TSOP2 Tray MR2A16ACYS35 Tape and Reel MR2A16ACYS35R 48-BGA Tray MR2A16ACMA35 Tape and Reel MR2A16ACMA35R Extended -40 to +105 °C 44-TSOP2 Tray MR2A16AVYS35 Tape and Reel MR2A16AVYS35R 48-BGA Tray MR2A16AVMA35 Tape and Reel MR2A16AVMA35R Automotive AEC- Q100 Grade 1 -40 to +125 °C 44-TSOP2 Tray MR2A16AMYS35 Tape and Reel MR2A16AMYS35R

44 PLACES

Print Version Not To Scale 1. Dimensions and tolerances per ASME Y14.5M - 1994. 2. Dimensions in Millimeters. 3. Dimensions do not include mold protrusion. 4. Dimension does not include DAM bar protrusions. DAM Bar protrusion shall not cause the lead width to exceed 0.58.

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 MR2A16A Figure 12 – 48-FBGA Packge Outline Notes: 1. Dimensions in Millimeters. 2. Dimensions and tolerances per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured paral- lel to DATUM A 4. DATUM A, the seating plane is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any ef- fect of mark on top surface of package.

5 Sept 21, 2007

Changed MR2A16ATS35C product description to Legacy Commercial. Added the New Com- merical temperature product (MR2A16AYS35) information. Table 3: MR2A16AYS35 Hmax- write=25 Oe. Table 4: MR2A16AYS35 has a 2 ms power up waiting period. Table 6: Applied values to TBD’s in IDD specifications.

6 Nov 12, 2007

Table 2: Changed IDDA to IDDR or IDDW. Table 13: Added noteindicating that TS and YS are both valid package codes. Current Part Numbering System: Added commercial (missing let- ter) temperature range.

7 Sep 12, 2008

Reformat Datasheet for EverSpin, Add BGA Packaging Information, Add Tape & Reel Part Numbers, Add Power Sequencing Info, Correct IOH spec of VOH to -100 uA, Correct ac Test Conditions. 8 July 22, 2009 Add TSOP2 Lead Cross-Section, Add Production Note. Converted to new document format. 9 Dec 16, 2011 Added AEC-Q100 Grade 1 product option for TSOP2 package to Table 4.1. Revised Tables 10 August 29, 2012 Corrected error in Table 1.1. Corrected Figure 2.1. Improved magnetic immunity for Indus- trial and Extended Grades. Corrected minor errors in Table 4.1 Product Numbering. 10.1 July 30, 2013 Corrected G to read G for 44-TSOP Type2 in Figure 1.2.

11 October 14,

MR2A16AMYS35/R is released from Preliminary to fully qualified. Reformatted to meet cur- rent standards. 11.1 May 19, 2015 Revised Everspin contact information. 11.2 June 11, 2015 Corrected Japan Sales Office telephone number.

11.3 March 23, 2018 Updated the Contact Us table

REVISION HISTORY

MR2A16A Rev. 11.3 3/2018 Copyright © Everspin Technologies 2018 MR2A16A Everspin Technologies, Inc. Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies as- sume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each customer application by cus- tomer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Tech- nologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiar- ies, affiliates, and distributors harmless against all claims, costs, dam- ages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Ever- spin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright © Everspin Technologies, Inc. 2018 HOW TO CONTACT US How to Reach Us: Home Page: www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com Filename: EST00193_MR2A16A_Datasheet_Rev11.3 032318

Product Information

MR2A16A specifications and overview.

Summary

256K x 16 MRAM Memory Rev. 11.3 3/2018

Description

256K x 16 MRAM Memory Rev. 11.3 3/2018

Source title MR2A16A Datasheet(PDF) - Everspin Technologies Inc.

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