MR256A08B EVERSPIN | Alldatasheet

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Technical content

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies 32K x 8 MRAM The MR256A08B is a 262,144-bit magnetoresistive random access memory (MRAM) device organized as 32,768 words of 8 bits. The MR256A08B offers SRAM compatible 35ns read/write timing with un- limited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR256A08B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR256A08B is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP type-2 package, or an 8 mm x 8 mm, 48-pin ball grid array (BGA) package. (The 32-SOIC package options is obsolete and no longer available for new orders.) All package footprints are compatible with similar low-power SRAM products and other non-volatile RAM products. The MR256A08B provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial temperature (0 to +70 °C) and industrial temperature (-40 to +85 °C) range options.

FEATURES

  • One memory replaces FLASH, SRAM, EEPROM and MRAM in system for simpler, more efficient design
  • Improves reliability by replacing battery-backed SRAM
  • 3.3 Volt power supply
  • Fast 35 ns read/write cycle
  • SRAM compatible timing
  • Native non-volatility
  • Unlimited read & write endurance
  • Data always non-volatile for >20 years at temperature
  • Commercial and industrial temperatures
  • All products meet MSL-3 moisture sensitivity level
  • RoHS-Compliant TSOP2 and BGA packages INTRODUCTION 48-ball FBGA 44-pin TSOP2 RoHS

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B CHIP ENABLE BUFFER OUTPUT ENABLE BUFFER ADDRESS BUFFER WRITE ENABLE BUFFER G E OUTPUT ENABLE 32K x 8 BIT MEMORY ARRAY ROW DECODER COLUMN DECODER SENSE AMPS OUTPUT BUFFER WRITE DRIVER FINAL WRITE DRIVERS WRITE ENABLE W A[14:0] 8 8 DQ[7:0] Figure 1 – MR256A08B Block Diagram Table 1 – MR256A08B Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O V DD Power Supply V SS Ground DC Do Not Connect NC No Connection - Pin 2, 40, 41,43 (TSOP2); Ball C2, C5, D3, F2, F5, G1, G2, G6, H1, H6 (BGA); Pin 9, 24, 31(SOIC) Reserved For Future Expansion BLOCK DIAGRAM AND PIN ASSIGNMENTS

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies 1 2 3 4 5 6 G A A A A A A E B DQ A A DQ DQ C VSS DQ VDD D VDD DQ VSS EDQ A DQ FNC A A W GNC A A H NCNC NC NC DCDC DCDC A DQ3 NC NC NC NC NC VSS VDD A A14 DC Figure 2 – Pin Diagrams for Available Packages (Top View) 1 Table 2 – Operating Modes E 1 G 1 W 1 Mode V DD Current DQ[7:0] 2 H X X Not selected I SB1 , I SB2 Hi-Z L H H Output disabled I DDR Hi-Z L L H Byte Read I DDR D Out L X L Byte Write I DDW D in Notes: 1. H = high, L = low, X = don’t care 2. Hi-Z = high impedance

48 Pin FBGA32 Pin SOIC 144 Pin TSOP2

A A A A VDD E VSS W A A A DC A DC 22 44 DC DC A G VSS A VDD DC A A A DC DC A A DC NC NC NC NC V V SS DD 1DC 2A14 3A12 4A7 5A6 6A5 7A4 8A3 9NC 10A2 11A1 12A0 13DQ0 14DQ1 VDD NC W A13 A11 G NC A10 E DQ7 DQ6 DQ5 DQ4 DQ3 15DQ2 17VSS Note: 1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer available for new orders.

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B ELECTRICAL SPECIFICATIONS This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. 1 Parameter Symbol Value Unit Supply voltage 2 V DD -0.5 to 4.0 V Voltage on an pin 2 V IN -0.5 to V DD + 0.5 V Output current per pin I OUT ±20 mA Package power dissipation 3 P D 0.600 W Temperature under bias MR256A08B (Commercial) MR256A08BC (Industrial) T BIAS -10 to 85 -45 to 95 Storage Temperature T stg -55 to 150 °C Lead temperature during solder (3 minute max) T Lead 260 °C Maximum magnetic field during write H max_write

2000 A/m

Maximum magnetic field during read or standby H max_read

8000 A/m

Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional oper- ation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2. All voltages are referenced to V SS 3. Power dissipation capability depends on package characteristics and use environment. Table 3 – Absolute Maximum Ratings Absolute Maximum Ratings

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies Parameter Symbol Min Typical Max Unit Power supply voltage V DD 3.0 1 3.3 3.6 V Write inhibit voltage V WI 2.5 2.7 3.0 1 V Input high voltage V IH 2.2 - V DD + 0.3 2 V Input low voltage V IL -0.5 3 - 0.8 V Temperature under bias MR256A08B (Commercial) MR256A08BC (Industrial) T A -40 Notes: 1. There is a 2 ms startup time once V DD exceeds V DD, (min). See “Power Up and Power Down Sequencing Timing Diagram” . 2. V IH (max) = V DD + 0.3 V DC ; V IH (max) = V DD + 2.0 V AC (pulse width ≤ 10 ns) for I ≤ 20.0 mA. 3. V IL (min) = -0.5 V DC ; V IL (min) = -2.0 V AC (pulse width ≤ 10 ns) for I ≤ 20.0 mA. Table 4 – Operating Conditions OPERATING CONDITIONS

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B Figure 3 – Power Up and Power Down Sequencing Timing Diagram BROWNOUT or POWER LOSS NORMAL OPERATION VDD READ/WRITE INHIBITED VWI 2 ms READ/WRITE INHIBITED VIH STARTUP NORMAL OPERATION 2 ms E W RECOVER VIH The MRAM is protected from write operations whenever V DD is less than V WI . As soon as V DD exceeds V DD (min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power sup- plies to stabilize. The E and W control signals should track V DD on power up to V DD - 0.2 V or V IH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where V DD goes below V WI , writes are protected and a startup time must be observed when power returns above V DD (min). Power Up and Power Down Sequencing

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies Parameter Symbol Min Typical Max Unit Input leakage current I lkg(I) - - ±1 μA Output leakage current I lkg(O) - - ±1 μA Output low voltage OL = + 4 mA) OL = + 100 μA) V OL - - 0.4 V SS + 0.2 V Output high voltage OL = - 4 mA) OL = - 100 μA) V OH 2.4 V DD - 0.2 - - V Table 5 – DC Characteristics DC CHARACTERISTICS

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B Table 6 – Power Supply Characteristics Parameter Symbol Typical Max Unit AC active supply current - read modes 1 OUT = 0 mA, V DD = max) I DDR 25 30 mA AC active supply current - write modes 1 DD = max) MR256A08B (Commercial) MR256A08BC (Industrial) I DDW mA AC standby current DD = max, E = V IH no other restrictions on other inputs MR256A08B (Commercial) MR256A08BC (Industrial) I SB1 8 mA CMOS standby current (E ≥ V DD - 0.2 V and V In V SS + 0.2 V or ≥ V DD - 0.2 V) DD = max, f = 0 MHz) MR256A08B (Commercial) MR256A08BC (Industrial) I SB2 7 mA Notes: 1. All active current measurements are measured with one address transition per cycle and at minimum cycle time.

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B Parameter 1 Symbol Min Max Unit Read cycle time tAVAV 35 - ns Address access time tAVQV - 35 ns Enable access time 2 tELQV - 35 ns Output enable access time tGLQV - 15 ns Output hold from address change tAXQX 3 - ns Enable low to output active 3 tELQX 3 - ns Output enable low to output active 3 tGLQX 0 - ns Enable high to output Hi-Z 3 tEHQZ 0 15 ns Output enable high to output Hi-Z 3 tGHQZ 0 10 ns Notes: 1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. 2. Addresses valid before or at the same time E goes low. 3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. Table 9 – Read Cycle Timing Read Mode Figure 6 – Read Cycle 1 A (ADDRESS) Q (DATA OUT) tAVAV tAXQX tAVQV Previous Data Valid Data Valid

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies Figure 7 – Read Cycle 2 A (ADDRESS) E (CHIP ENABLE) G (OUTPUT ENABLE) Q (DATA OUT) Data Valid tAVAV tAVQV tELQV tELQX tGHQZ tEHQZ tGLQV tGLQX

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B Table 10 – Write Cycle Timing 1 (W Controlled) Parameter 1 Symbol Min Max Unit Write cycle time 2 tAVAV 35 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 18 - ns Address valid to end of write (G low) tAVWH 20 - ns Write pulse width (G high) tWLWH tWLEH 15 - ns Write pulse width (G low) tWLWH tWLEH 15 - ns Data valid to end of write tDVWH 10 - ns Data hold time tWHDX 0 - ns Write low to data Hi-Z 3 tWLQZ 0 12 ns Write high to output active 3 tWHQX 3 - ns Write recovery time tWHAX 12 - ns Notes: 1. All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must re- main in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given voltage or temperature, t WLQZ (max) < t WHQX (min) Write Mode

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) Q (DATA OUT) D (DATA IN) tAVAV tAVWH tWHAX tWLEH tWHDXtDVWH tWHQX tAVWL t Hi-Z Hi-Z WLQZ tWLWH Data Valid Figure 8 – Write Cycle Timing 1 (W Controlled)

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B Table 11 – Write Cycle Timing 2 (E Controlled) Parameter 1 Symbol Min Max Unit Write cycle time 2 tAVAV 35 - ns Address set-up time tAVEL 0 - ns Address valid to end of write (G high) tAVEH 18 - ns Address valid to end of write (G low) tAVEH 20 - ns Enable to end of write (G high) tELEH tELWH 15 - ns Enable to end of write (G low) 3 tELEH tELWH 15 - ns Data valid to end of write tDVEH 10 - ns Data hold time tEHDX 0 - ns Write recovery time tEHAX 12 - ns Notes: 1. All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being as- serted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state.

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies Figure 9 – Write Cycle Timing 2 (E Controlled) A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) Q (DATA OUT) D (DATA IN) tAVAV tAVEH tEHAX tELEH tEHDXtDVEH tAVEL Hi-Z tELWH Data Valid

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B

ORDERING INFORMATION

Table 12 – Ordering Part Number System for Parallel I/O MRAM Memory Density Type I/O Width Rev. Temp Package Speed Packing Grade Example Ordering Part Number MR 256 A 08 B C MA 35 R MRAM MR

256 Kb 256

1 Mb 0

4 Mb 2

16 Mb 4

Async 3.3v A Async 3.3v Vdd and 1.8v Vddq D Async 3.3v Vdd and 1.8v Vddq with 2.7v min. Vdd DL 8-bit 08 16-bit 16 Rev A A Rev B B Commercial 0 to 70°C Blank Industrial -40 to 85°C C Extended -40 to 105°C V AEC Q-100 Grade 1 -40 to 125°C M 44-TSOP-2 YS 48-FBGA MA 16-SOIC SC 32-SOIC SO 35 ns 35 45 ns 45 Tray Blank Tape and Reel R Engineering Samples ES Customer Samples Blank Mass Production Blank

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies Table 13 – MR256A08B Ordering Part Numbers 1 Temp Grade Temp Package Shipping Ordering Part Number Commercial 0 to +70 °C 44-TSOP2 Tray MR256A08BYS35 Tape and Reel MR256A08BYS35R 48-BGA Tray MR256A08BMA35 Tape and Reel MR256A08BMA35R 32-SOIC 1 Tray MR256A08BSO35 Obsolete Tape and Reel MR256A08BSO35R Obsolete Industrial -40 to +85 °C 44-TSOP2 Tray MR256A08BCYS35 Tape and Reel MR256A08BCYS35R 48-BGA Tray MR256A08BCMA35 Tape and Reel MR256A08BCMA35R 32-SOIC 1 Tray MR256A08BCSO35 Obsolete Tape and Reel MR256A08BCSO35R Obsolete 1 The 32-SOIC package option is obsolete and no longer available. See PCN02895 here.

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B Figure 10 – 44-TSOP2 Package Outline PACKAGE OUTLINE DRAWINGS Not To Scale 1. Dimensions and tolerances per ASME Y14.5M - 1994. 2. Dimensions in Millimeters. 3. Dimensions do not include mold protrusion. 4. Dimension does not include DAM bar protrusions. 5. DAM Bar protrusion shall not cause the lead width to exceed 0.58.

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies Figure 11 – 48-BGA Package Outline TOP VIEW BOTTOM VIEW SIDE VIEW 0.410.31 0.32 0.22 Not To Scale 1. Dimensions in Millimeters. 2. Dimensions and tolerances per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured parallel to DATUM A 4. DATUM A, the seating plane is determined by the spherical crowns of the solder balls. surface of package.

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies Figure 12 – 32-SOIC Package Outline 1 Unit A B C D E F G H I J K mm - Min - Max 20.574 20.878 1.00 1.50 0.355 0.508 0.66 0.81 0.101 0.254 2.286 2.540 Radius 0.101 0.533 1.041 0.152 0.304 7.416 7.594 10.287 10.642 inch - Min - Max 0.810 0.822 0.04 0.06 0.14 0.02 0.026 0.032 0.004 0.010 0.09 0.10 Radius 0.0040 0.021 0.041 0.006 0.012 0.292 0.299 0.405 0.419 1 16 32 17 PIN 1 ID A B C D E F G H J K I Reference JEDEC MO-119 Note: 1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer available for new orders.

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies Revision Date Description of Change

0 Sept 12, 2008 Initial Advance Information Release

1 Mar 25, 2009 Add Industrial and Automotive Temperature Options

2 August 16, 2011 Removed Automotive temperature options. Included SOIC package. Revised formatting

3 October 28, 2011

Changed TSOP-II to TSOP2. Changed logo to new EST Logo. Revisions to Available Parts, Table 4.1: Added Industrial Temp Grade option in SOIC package. Deleted Tape & Reel pack option for all SOIC packaged parts.

4 Dec 9, 2011

Figure 2.1 cosmetic update. Figure 5.2 BGA package outline drawing revised for package ball size. Revisions to ISB1, ISB2 and IDDW for Indus- trial Grade options in Table 2.4. 5 July 9, 2013 MR256A08BCSO35 removed Preliminary status. Now MP . 6 October 11, 2013 Added Tape and Reel shipping option for SOIC packaged products. Re- formatted to current standards. 6.1 May 19, 2015 Revised Everspin contact information. 6.2 June 11, 2015 Corrected Japan Sales Office telephone number. 6.3 July 20, 2015 32-SOIC package options Not Recommended for New Designs. 6.4 October 17, 2015 32-SOIC package options are obsolete and no longer available.

6.5 March 23, 2018 Updated the Contact Us table

REVISION HISTORY

MR256A08B Rev. 6.5 3/2018 Copyright © 2018 Everspin Technologies MR256A08B Everspin Technologies, Inc. Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies as- sume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each customer application by cus- tomer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Tech- nologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiar- ies, affiliates, and distributors harmless against all claims, costs, dam- ages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Ever- spin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright © Everspin Technologies, Inc. 2018 HOW TO CONTACT US How to Reach Us: Home Page: www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com Filename: EST00355_MR256A08B_Datasheet_Rev6.5 032318