MR25H10

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MR25H10 EVERSPIN | Alldatasheet

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No write delays
Unlimited write endurance
Data retention greater than 20 years
Automatic data protection on power loss
Block write protection
Fast, simple SPI interface with up to 40 MHz clock rate
2.7 to 3.6 Volt power supply range
Low current sleep mode
Industrial temperatures
Available in 8-pin DFN or 8-pin DFN Small Flag RoHS-compliant packages
Direct replacement for serial EEPROM, Flash, FeRAM
AEC-Q100 Grade 1 Option INTRODUCTION The MR25H10 is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as 131,072 words of 8 bits. The MR25H10 offers serial EEPROM and serial Flash compatible read/write timing with no write delays and unlimited read/write endurance. Unlike other serial memories, both reads and writes can occur randomly in memory with no delay between writes. The MR25H10 is the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of I/O pins. The MR25H10 is available in either a 5 mm x 6 mm 8-pin DFN package or a 5 mm x 6 mm 8-pin DFN Small Flag package. Both are compatible with serial EEPROM, Flash, and FeRAM products. The MR25H10 provides highly reliable data storage over a wide range of temperatures. The product is offered with Industrial (-40° to +85 °C) and AEC-Q100 Grade 1 (-40°C to +125 °C) operating temperature range options.

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 Signal Name Pin I/O Function Description CS 1 Input Chip Select An active low chip select for the serial MRAM. When chip select is high, the memory is powered down to minimize standby power, inputs are ignored and the serial output pin is Hi-Z. Multiple serial memories can share a com- mon set of data pins by using a unique chip select for each memory. SO 2 Output Serial Output The data output pin is driven during a read operation and remains Hi-Z at all other times. SO is Hi-Z when HOLD is low. Data transitions on the data output occur on the falling edge of SCK. WP 3 Input Hold A low on the write protect input prevents write operations to the Status Register. VSS 4 Supply Ground Power supply ground pin. SI 5 Input Serial Input All data is input to the device through this pin. This pin is sampled on the rising edge of SCK and ignored at other times. SI can be tied to SO to create a single bidirectional data bus if desired. SCK 6 Input Serial Clock Synchronizes the operation of the MRAM. The clock can operate up to 40 MHz to shift commands, address, and data into the memory. Inputs are captured on the rising edge of clock. Data outputs from the MRAM occur on the falling edge of clock. The serial MRAM supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is normally low. In Mode 3, the clock is normally high. Memory operation is static so the clock can be stopped at any time. HOLD 7 Input Hold A low on the Hold pin interrupts a memory operation for another task. When HOLD is low, the current operation is suspended. The device will ignore transitions on the CS and SCK when HOLD is low. All transitions of HOLD must occur while CS is low. VDD 8 Supply Power Supply Power supply voltage from +2.7 to +3.6 volts. Table 1.1 Pin Functions Figure 1.3 Pin Diagrams (Top View) 8-Pin DFN or 8-Pin DFN Small Flag Package DEVICE PIN ASSIGNMENT CS SO WP V V HOLD SCK SI 5SS DD

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 2. SPI COMMUNICATIONS PROTOCOL Instruction Description Binary Code Hex Code Address Bytes Data Bytes WREN Write Enable 0000 0110 06h 0 0 WRDI Write Disable 0000 0100 04h 0 0 RDSR Read Status Register 0000 0101 05h 0 1 WRSR Write Status Register 0000 0001 01h 0 1 READ Read Data Bytes 0000 0011 03h 3 1 to ∞ WRITE Write Data Bytes 0000 0010 02h 3 1 to ∞ SLEEP Enter Sleep Mode 1011 1001 B9h 0 0 WAKE Exit Sleep Mode 1010 1011 ABh 0 0 Table 2.1 Command Codes MR25H10 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1). For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS falls. All memory transactions start when CS is brought low to the memory. The first byte is a command code. De- pending upon the command, subsequent bytes of address are input. Data is either input or output. There is only one command performed per CS active period. CS must go inactive before another command can be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or aborted accesses. Status Register and Block Write Protection The status register consists of the 8 bits listed in table 2.2. Status register bits BP0 and BP1 define the mem- ory block arrays that are protected as described in table 2.3. The Status Register Write Disable bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) as shown in table 2.4 to enable writes to status register bits. The fast writing speed of MR25H10 does not require write status bits. The state of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the status register are pre-set from the factory to the “0” state. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRWD Don’t Care Don’t Care Don’t Care BP1 BP0 WEL Don’t Care Table 2.2 Status Register Bit Assignments

0 X X Protected Protected Protected

1 0 X Protected Writable Writable 1 1 Low Protected Writable Protected 1 1 High Protected Writable Writable Table 2.4 Memory Protection Modes Status Register Memory Contents BP1 BP0 Protected Area Unprotected Area 0 0 None All Memory 0 1 Upper Quarter Lower Three-Quarters 1 0 Upper Half Lower Half 1 1 All None Table 2.3 Block Memory Write Protection Read Status Register (RDSR) The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can be read at any time to check the status of write enable latch bit, status register write protect bit, and block write protect bits. For MR25H10, the write in progress bit (bit 0) is not written by the memory because there is no write delay. The RDSR command is entered by driving CS low, sending the command code, and then driving CS high. When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1, status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD, BP0 and BP1. SCK SI SO CS Status Register Out High Impedance High Z Mode 3 Mode 0 10 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 1 MSB MSB 7 6 5 4 3 2 1 0

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 SPI COMMUNICATIONS PROTOCOL Write Data Bytes (WRITE) The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by the 24-bit address. Only address bits 0-16 are decoded by the memory. The data bytes are written sequen- tially in memory until the write operation is terminated by bringing CS high. The entire memory can be written in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed without write delays or data polling. Back to back WRITE commands to any random location in mem- ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or block organized memory so it is ideal for both program and data storage. The WRITE command is entered by driving CS low, sending the command code, and then sequential write data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS high. Figure 2.6 WRITE SCK SI SO CS 24-Bit Address High Impedance Instruction (02h) 0 0 0 0 0 0 1 0 X X X 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK SI SO CS Data Byte 3 High Impedance Data Byte NData Byte 2 34 2 1 0 7 6 5 4 3 2 1 0 MSB 7 6 5 4 3 2 1 0 7 6 5 MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3 Mode 0

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the field intensity specified in the maximum ratings. Symbol Parameter Conditions Limit Unit VDD Supply voltage2 -0.5 to 4.0 V VIN Voltage on any pin2 -0.5 to VDD + 0.5 V IOUT Output current per pin ±20 mA TBIAS Temperature under bias Industrial -45 to 95 °C AEC-Q100 Grade 1 -45 to 130 °C Tstg Storage Temperature -55 to 150 °C TLead Lead temperature 3 minutes max 260 °C Hmax_write Maximum magnetic field exposure Write 12,000 A/mHmax_read Maximum magnetic field exposure Read or Standby 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than 20mA. 3 Power dissipation capability depends on package characteristics and use environment. Table 3.1 Absolute Maximum Ratings1

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 Symbol Parameter Grade Min Max Unit VDD Power supply voltage Industrial 2.7 3.6 V AEC-Q100 Grade1 3.0 3.6 V VIH Input high voltage All 2.2 VDD + 0.3 V VIL Input low voltage All -0.5 0.8 V TA Temperature under bias Industrial -40 85 °C AEC-Q100 Grade1 1 -40 125 °C

1 AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years

out of 20-year life.) Table 3.2 Operating Conditions ELECTRICAL SPECIFICATIONS Symbol Parameter Conditions Min Typical Max Unit ILI Input leakage current - - ±1 μA ILO Output leakage current - - ±1 μA VOL Output low voltage IOL = +4 mA - - 0.4 V IOL = +100 μA - - VSS + 0.2v V VOH Output high voltage (IOH = -4 mA) 2.4 - - V (IOH = -100 μA) VDD - 0.2 - - V Table 3.3 DC Characteristics Table 3.4 Power Supply Characteristics Symbol Parameter Conditions Typical Max Unit IDDR Active Read Current 1 MHz 2.5 3 mA

40 MHz 6 10 mA

1 MHz 8 13 mA

40 MHz 23 27 mA

ISB Standby Current CS high and SPI bus inactive 90 115 μA Izz Standby Sleep Mode Current CS high and SPI bus inactive 7 30 μA

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 TIMING SPECIFICATIONS Power-Up Timing The MR25H10 is not accessible for a start-up time, tPU= 400 μs after power up. Users must wait this time from the time when VDD (min) is reached until the first CS low to allow internal voltage references to become stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up sequence. Symbol Parameter Min Typical Max Unit VWI Write Inhibit Voltage 2.2 - 2.7 V tPU Startup Time 400 - - μs Table 4.3 Power-Up VDD VDD V (max) VDD(min) WI t PU Time Normal Operation Chip Selection not allowed Reset state of the device Figure 4.3 Power-Up Timing

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 TIMING SPECIFICATIONS Symbol Parameter Conditions Min Max Unit fSCK SCK Clock Frequency 0 40 MHz tRI Input Rise Time - 50 ns tRF Input Fall Time - 50 ns tWH SCK High Time 11 - ns tWL SCK Low Time 11 - ns Synchronous Data Timing (See figure 4.4) tCS CS High Time 40 - ns tCSS CS Setup Time 10 - ns tCSH CS Hold Time 10 - ns tSU Data In Setup Time 5 - ns tH Data In Hold Time 5 - ns tV Output Valid Industrial Grade VDD = 2.7 to 3.6v. 0 10 ns Output Valid Industrial Grade VDD = 3.0 to 3.6v. 0 9 ns Output Valid AEC-Q100 Grade 1 VDD = 3.0 to 3.6v. 0 10 ns tHO Output Hold Time 0 - ns HOLD Timing (See figure 4.5) tHD HOLD Setup Time 10 - ns tCD HOLD Hold Time 10 - ns tLZ HOLD to Output Low Impedance - 20 ns tHZ HOLD to Output High Impedance - 20 ns Other Timing Specifications tWPS WP Setup To CS Low 5 - ns tWPH WP Hold From CS High 5 - ns tDP Sleep Mode Entry Time 3 - μs tRDP Sleep Mode Exit Time 400 - μs tDIS Output Disable Time 12 - ns

1 Over the Operating Temperature Range and CL= 30 pF

Table 4.4 AC Timing Parameters1 Synchronous Data Timing

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 5. ORDERING INFORMATION Table 5.1 Available Parts Figure 5.1 Part Numbering System Package Options DC 8 Pin DFN on Tray DCR DF DFR

8 Pin DFN on Tape and Reel

8 pin DFN Small Flag on Tray 8 pin DFN Small Flag on Tape and Reel Temperature Range C -40 to +85 °C ambient (Industrial) M -40 to +125 °C ambient (AEC-Q100 Grade 1) Memory Density 10 1 Mb Interface 25H High Speed Serial SPI Family Product Type MR Magnetoresistive RAM MR 25H 10 C DC Grade Temperature Range Package Shipping Container Order Part Number Industrial -40 to +85 C 8-DFN 1 Tray MR25H10CDC 1 Tape and Reel MR25H10CDCR 1 Small Flag 8-DFN Tray MR25H10CDF Tape and Reel MR25H10CDFR AEC-Q100 Grade 1 -40 to +125 C 8-DFN 1 Tray MR25H10MDC 1 Tape and Reel MR25H10MDCR 1 Small Flag 8-DFN Tray MR25H10MDF Tape and Reel MR25H10MDFR Note: 1. The DC pckage option (8-DFN) is not recommended for new designs. Please select the DF (small flag 8-DFN) option for new designs.

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 6. MECHANICAL DRAWINGS Figure 6.1 DFN Package NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229 Dimension A B C D E F G H I J K L M N Max. Min. 5.10 4.90 6.10 5.90 1.00 0.90 1.27 BSC 0.45 0.35 0.05 0.00 0.35 Ref. 0.70 0.50 4.20 4.00 4.20 4.00 0.261 0.195 C0.35 R0.20 0.05 0.00

0.10 C2X

NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229 6. MECHANICAL DRAWINGS Figure 6.2 Small Flag DFN Package Exposed metal Pad. Do not con- nect anything except VSS Dimension A B C D E F G H I J K L M N Max Min 5.10 4.90 6.10 5.90 0.90 0.80 1.27 BSC 0.45 0.35 0.05 0.00 1.60 1.20 0.70 0.50 2.10 1.90 2.10 1.90 .210 .196 C0.45 R0.20 0.05 0.00

0 Sep 12, 2008 Initial Advance Information Release

1 Jul 10, 2009 Change ac load resistance, tPU to 400 us, tRDP to 400 us, Change # of Address Bytes in Table 2 to 3, New Package Drawing, Make Preliminary

2 Jul 16, 2009 Increase Absolute Max Magnetic Field during write, read, and standby to 12,000 A/m

3 Jan 5, 2010 Described block protect in detail with power sequencing. 4 Feb 5, 2010 Added section system configuration. 5 May 17, 2010 Removed commercial specifications. All parts meet industrial specifications.

6 Sep 14, 2011

Corrected various typos. Clarified block and status register protection description. Revised Table 3.4 Power Supply specifications. Added AEC-Q100 Grade 1 ordering option. Revised

7 November 18,

Corrected VOL in Table 3.3 to read VOL Max = VSS + 0.2v. Operating Conditions Power Supply Voltage for AEC-Q100 Grade1revised to 3.0-3.6v. Table 4.4: Output Valid tV specifications revised to include VDD ranges for Industrial and AEC-Q100 Grade 1 options. Corrected SI waveform in Figure 2.8. Output Valid, tv for AEC-Q100 Grade revised from 9ns max to 10ns max in Table 4.4. New Small Flag DFN package option added to Page 1 Features and avail- able parts Table 5.1. DFN Small Flag drawing and dimensions table added as Figure 6.2. Figure 6.1, DFN Package, cleaned up with better quality drawing and dimension table. No specifications were changed in Figure 6.1.

8 October 19,

Reformatted tables for Section 3 Electrical Characteristics and timing parameters, Table and MDCR options are now qualified. Added Small Flag DFN illustrations. Revised 8-DFN package drawing to show correct proportion for flag and package. Corrected errors in DFN package outline drawings. Corrected VDD range for AEC-Q100 tV specification. 9 April 17, 2013 Added Automotive Grade AEC-Q100 Grade 1 for Small Flag DFN package. 9.1 May 19, 2015 Revised Everspin contact information. 9.2 June 11, 2015 Corrected Japan Sales Office telephone number.

9.3 December 13,

Changed all large flag DFN optoins to “The DC pckage option (8-DFN) is not recom- mended for new designs. Please select the DF (small flag 8-DFN) option for new designs. ”

9.4 February 2, 2017 Added tHO and tV relationship to Synchronous Data Timing

9.5 March 23, 2018 Updated the Contact Us table

REVISION HISTORY

Copyright © Everspin Technologies 2018 MR25H10 Rev. 9.5 3/2018 MR25H10 Everspin Technologies, Inc. Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technol- ogies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each customer application by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica- tion in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its of- ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright © Everspin Technologies, Inc. 2018 How to Reach Us: Home Page: www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com

Product Information

MR25H10 specifications and overview.

Summary

1Mb Serial SPI MRAM Rev. 9.5 3/2018

Description