MR2A08AYS35

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MR2A08A EVERSPIN | Alldatasheet

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Fast 35ns Read/Write Cycle
SRAM Compatible Timing, Uses Existing SRAM Controllers Without Redesign
Unlimited Read & Write Endurance
Data Always Non-volatile for >20 years at Temperature
One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in System for Simpler, More Efficient Design
Replace battery-backed SRAM solutions with MRAM to eliminate battery assembly, improving reliability
3.3 Volt Power Supply
Automatic Data Protection on Power Loss
Commercial, Industrial, Automotive Temperatures
RoHS-Compliant SRAM TSOP2 Package
RoHS-Compliant SRAM BGA Package
AEC-Q100 Grade 1 Qualified INTRODUCTION The MR2A08A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as 524,288 words of 8 bits. The MR2A08A offers SRAM compatible 35ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR2A08A is the ideal memory solution for applications that must permanently store and retrieve criti- cal data and programs quickly. The MR2A08A is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP type 2 package or an 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are compatible with similar low-power SRAM products and other non-volatile RAM products. The MR2A08A provides highly reliable data storage over a wide range of temperatures. The product is of- fered with commercial temperature range (0 to +70 °C), industrial temperature range (-40 to +85 °C), and AEC-Q100 Grade 1 temperature range (-40 to +125 °C) options. RoHS

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. CHIP ENABLE BUFFER OUTPUT ENABLE BUFFER ADDRESS BUFFER WRITE ENABLE BUFFER G E OUTPUT ENABLE 512k x 8 BIT MEMORY ARRAY ROW DECODER COLUMN DECODER SENSE AMPS OUTPUT BUFFER WRITE DRIVER FINAL WRITE DRIVERS WRITE ENABLE W A[18:0] 8 8 DQ[7:0] 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O VDD Power Supply VSS Ground DC Do Not Connect NC No Connection - Pin 2, 43 (TSOPII); Ball H6, G2 (BGA) Reserved For Future Expansion MR2A08A

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. DQ₀ DQ₁ VDD E VSS DQ₂ DQ₃ W DC DC 22 44 DC NC A₁₈ A₁₇ DC A₁₅ G DQ₇ DQ₆ VSS A₁₆ VDD DQ₅ DQ₄ DC A₁₄ A₁₃ A₁₂ A₁₁ A₁₀ DC DC DC NC 1 2 3 4 5 6 G A₀ A₁ A₂ A A₃ A₄ E B DQ₀ A₅ A₆ DQ₅ DQ₄ C VSS A₁₅ DQ₆ VDD D VDD DQ₁ DC A₁₇ A₁₄ VSS E DQ₃ DQ₂ A₁₂ A₁₃ DQ₇ F NC NC A₁₀ A₁₁ W GNC A₁₈ A₉ NC H NC NCNC NC NC DCDC DCDC A₁₆ Figure 1.2 Pin Diagrams for Available Packages (Top View)

44 Pin TSOP2 48 Pin FBGA

Table 1.2 Operating Modes E1 G1 W1 Mode VDD Current DQ[7:0]2 H X X Not selected ISB1, ISB2 Hi-Z L H H Output disabled IDDR Hi-Z L L H Byte Read IDDR DOut L X L Byte Write IDDW Din

1 H = high, L = low, X = don’t care

2 Hi-Z = high impedance

DEVICE PIN ASSIGNMENT MR2A08A

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Table 2.1 Absolute Maximum Ratings1 MR2A08A Symbol Parameter Temp Range Package Value Unit VDD Supply voltage 2 - - -0.5 to 4.0 V VIN Voltage on any pin 2 - - -0.5 to VDD + 0.5 V IOUT Output current per pin - - ±20 mA TBIAS Temperature under bias Commercial - -10 to 85 °CIndustrial - -45 to 95 AEC-Q100 Grade 1 - -45 to 130 Tstg Storage Temperature - - -55 to 150 °C TLead Lead temperature during solder (3 minute max) - - 260 °C Hmax_write Maximum magnetic field during write Commercial TSOP2, BGA 2,000 A/mIndustrial BGA 2,000 TSOP2 10,000 AEC-Q100 Grade 1 TSOP2 2,000 Hmax_read Maximum magnetic field during read or standby Commercial TSOP2, BGA 8,000 A/mIndustrial BGA 8,000 TSOP2 10,000 AEC-Q100 Grade 1 TSOP2 8,000 Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability depends on package characteristics and use environment.

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. Parameter Symbol Min Typical Max Unit Power supply voltage 1 VDD 3.0 3.3 3.6 V Write inhibit voltage VWI 2.5 2.7 3.0 1 V Input high voltage VIH 2.2 - VDD + 0.3 2 V Input low voltage VIL -0.5 3 - 0.8 V Temperature under bias MR2A08A (Commercial) MR2A08AC (Industrial) MR2A08AM (AEC-Q100 Grade 1)4 TA -40 -40 125 1 There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below. 2 VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA. 3 V IL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA. 4 AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life) Table 2.2 Operating Conditions Power Up and Power Down Sequencing The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). Figure 2.1 Power Up and Power Down Diagram MR2A08AElectrical Specifications BROWNOUT or POWER LOSS NORMAL OPERATION VDD READ/WRITE INHIBITED VWI 2 ms READ/WRITE INHIBITED VIH STARTUP NORMAL OPERATION 2 ms E W RECOVER VIH

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. Parameter Symbol Min Max Unit Input leakage current Ilkg(I) - ±1 μA Output leakage current Ilkg(O) - ±1 μA Output low voltage (IOL = +4 mA) (IOL = +100 μA) VOL - 0.4 VSS + 0.2 V Output high voltage (IOL = -4 mA) (IOL = -100 μA) VOH 2.4 VDD - 0.2 - V Table 2.3 DC Characteristics Table 2.4 Power Supply Characteristics Parameter Symbol Typical Max Unit AC active supply current - read modes1 (IOUT= 0 mA, VDD= max) IDDR 30 66 mA AC active supply current - write modes1 (VDD= max) Commercial Grade Industrial Grade AEC-Q100 Grade IDDW 135 135 135 mA AC standby current (VDD= max, E = VIH) no other restrictions on other inputs ISB1 13 20 mA CMOS standby current (E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD - 0.2 V) (VDD = max, f = 0 MHz) ISB2 8 10 mA 1 All active current measurements are measured with one address transition per cycle and at minimum cycle time. MR2A08AElectrical Specifications

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. MR2A08ATiming Specifications Table 3.4 Write Cycle Timing 1 (W Controlled)1 Parameter Symbol Min Max Unit Write cycle time 2 tAVAV 35 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 18 - ns Address valid to end of write (G low) tAVWH 20 - ns Write pulse width (G high) tWLWH tWLEH 15 - ns Write pulse width (G low) tWLWH tWLEH 15 - ns Data valid to end of write tDVWH 10 - ns Data hold time tWHDX 0 - ns Write low to data Hi-Z 3 tWLQZ 0 12 ns Write high to output active 3 tWHQX 3 - ns Write recovery time tWHAX 12 - ns 1 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 All write cycle timings are referenced from the last valid address to the first transition address. 3 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given voltage or temperature, tWLQZ(max) < tWHQX(min) W (WRITE ENABLE) A (ADDRESS) E (CHIP ENABLE) t AVAV t AVWH t WHAX t AVWL t WLEH t WLWH DATA VALID t DVWH t WHDX Q (DATA OUT) D (DATA IN) t WLQZ t WHQX Hi -Z Hi -Z Figure 3.4 Write Cycle Timing 1 (W Controlled)

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. MR2A08ATiming Specifications Table 3.5 Write Cycle Timing 2 (E Controlled) 1 Figure 3.5 Write Cycle Timing 2 (E Controlled) Parameter Symbol Min Max Unit Write cycle time 2 tAVAV 35 - ns Address set-up time tAVEL 0 - ns Address valid to end of write (G high) tAVEH 18 - ns Address valid to end of write (G low) tAVEH 20 - ns Enable to end of write (G high) tELEH tELWH 15 - ns Enable to end of write (G low) 3 tELEH tELWH 15 - ns Data valid to end of write tDVEH 10 - ns Data hold time tEHDX 0 - ns Write recovery time tEHAX 12 - ns 1 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 All write cycle timings are referenced from the last valid address to the first transition address. 3 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) Q (DATA OUT) D (DATA IN) tAVAV tAVEH tAVEL tEHAX tEHDXtDVEH Hi-Z Data Valid tELEH tELWH

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. MR2A08A 4. ORDERING INFORMATION Figure 4.1 Part Numbering System Carrier (Blank = Tray, R = Tape & Reel) Speed (35 ns) Temperature Range (Blank= Commercial (0 to +70 °C, C= Industrial (-40 to +85 °C, M= AEC- Q100 Grade 1 (-40 to +125 °C) Revision Data Width (08 = 8-Bit, 16 = 16-bit) Type (A = Asynchronous, S = Synchronous) Density (256 = 256 Kb, 0 = 1Mb, 1 =2Mb, 2 =4Mb, 4 =16Mb) Magnetoresistive RAM (MR) MR 2 A 08 A C YS 35 R Part Number Description Package Ship Pack Temp Range MR2A08AYS35 3.3 V 512Kx8 MRAM Commercial 44-TSOP2 Tray 0 to +70 °C MR2A08ACYS35 3.3 V 512Kx8 MRAM Industrial 44-TSOP2 Tray -40 to +85 °C MR2A08AMYS35 3.3 V 512Kx8 MRAM AEC-Q100 Grade 1 44-TSOP2 Tray -40 to +125 °C MR2A08AYS35R 3.3 V 512Kx8 MRAM Commercial 44-TSOP2 Tape & Reel 0 to +70 °C MR2A08ACYS35R 3.3 V 512Kx8 MRAM Industrial 44-TSOP2 Tape & Reel -40 to +85 °C MR2A08AMYS35R 3.3 V 512Kx8 MRAM AEC-Q100 Grade 1 44-TSOP2 Tape & Reel -40 to +125 °C MR2A08AMA35 3.3 V 512Kx8 MRAM Commercial 48-BGA Tray 0 to +70 °C MR2A08ACMA35 3.3 V 512Kx8 MRAM Industrial 48-BGA Tray -40 to +85 °C MR2A08AMA35R 3.3 V 512Kx8 MRAM T&R Commercial 48-BGA Tape & Reel 0 to +70 °C MR2A08ACMA35R 3.3 V 512Kx8 MRAM T&R Industrial 48-BGA Tape & Reel -40 to +85 °C Table 4.1 Available Parts

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. Figure 5.1 TSOP2 MR2A08A 5. MECHANICAL DRAWING Print Version Not To Scale 1. Dimensions and tolerances per ASME Y14.5M - 1994. 2. Dimensions in Millimeters. 3. Dimensions do not include mold protrusion. 4. Dimension does not include DAM bar protrusions. DAM Bar protrusion shall not cause the lead width to exceed 0.58.

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. TOP VIEW BOTTOM VIEW SIDE VIEW Figure 5.2 FBGA Print Version Not To Scale 1. Dimensions in Millimeters. 2. Dimensions and tolerances per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured parallel to DATUM A 4. DATUM A, the seating plane is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. MR2A08AMechanical Drawings

1 Oct 29, 2007 Designate pin 23, 24, 42 of TSOPII as DC "Don't Connect" pins since these pins

should remain floating at all times. Functional operation of E2 pin defined.

2 Sep 12, 2008

Reformat Datasheet for Everspin, Delete E2 pin Function, Add BGA Package Infor- mation Add Tape & Reel Part Numbers, Add Power Sequencing Info, Correct IOH Spec For VOH to -100 uA, Correct ac Test Conditions

3 Apr 10, 2009 Add typical and worst case current specifications

4 July 6, 2009 Changed datasheet from Preliminary to Production except where noted. Updated format.

5 Dec 16, 2011

Added AEC-Q100 Grade 1 temp performance specifications to Table 2.1, Table 2.2, addition of AEC-Q100 Grade 1 and revision of IDDW Typical values in Table 2.4. AEC-Q100 Grade 1 ordering options added to Figure 4.1 and Table 4.1. Changed TSOP-II to TSOP2 everywhere. New logo design. Cosmetic revision to Table 2.1. 6 August 2, 2012 Improved magnetic immunity for Industrial and Extended Grades. Revised Power Up/Power Down Diagram. 6.1 May 19, 2015 Revised contact information. 6.2 June 11, 2015 Corrected Japan Sales Office telephone number.

6.3 March 23, 2018 Update the Contact Us table

REVISION HISTORY

MR2A08A Rev. 6.3, 3/2018 Copyright © 2018 Everspin Technologies, Inc. Everspin Technologies, Inc. Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this docu- ment. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifi- cally disclaims any and all liability, including without limitation consequen- tial or incidental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each customer application by customer’s technical experts. Everspin Technolo- gies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthor- ized use, even if such claim alleges that Everspin Technologies was negli- gent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright © Everspin Technologies, Inc. 2018 How to Reach Us: Home Page: www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com Filename: EST00170_MR2A08A_Datasheet_Rev6.3 032318 HOW TO CONTACT US

Product Information

MR2A08AYS35 specifications and overview.

Summary

512K x 8 MRAM Memory Rev. 6.3, 3/2018

Description