MR20H40

MR20H40 EVERSPIN | Alldatasheet

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Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 MR20H40 - 50MHz/20ns tSCK 4Mb SPI Interface MRAM

• No write delays
• Unlimited write endurance
• Data retention greater than 20 years
• Automatic data protection on power loss
• Fast, simple SPI interface, up to 50 MHz clock rate with MR20H40.
• 3.0 to 3.6 Volt power supply range
• Low-current sleep mode
• Commercial (0 to 70°C), Industrial (-40 to 85°C), Extended (-40 to 105°C), and AEC-Q100 Grade 1 (-40 to 125°C) temperature range options.
• Available in 8-pin DFN or 8-pin DFN Small Flag, RoHS-compliant packages.
• Direct replacement for serial EEPROM, Flash, and FeRAM
• MSL Level 3 MR2xH40 is a family of 4,194,304-bit magnetoresistive random access memory (MRAM) devices organized as 524,288 words of 8 bits. They are the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of I/O pins. They have serial EE- PROM and serial Flash compatible read/write timing with no write delays and unlimited read/write endurance. Unlike other serial memories, with the MR2xH40 family both reads and writes can occur randomly in memory with no delay between writes. The MR2xH40 family provides highly reliable data storage over a wide range of temperatures. The MR20H40 (50MHz) is offered with Industrial (-40° to 85 °C) range. The MR25H40 (40MHz) is offered with Commercial (0 to 70°C), Industrial (-40° to 85 °C), Extended (-40 to 105°C), and AEC-Q100 Grade 1 (-40°C to 125 °C) operating temperature range options. Both are available in a 5 x 6mm, 8-pin DFN package. The pinout is compatible with serial SRAM, EEPROM, Flash, and FeRAM products. RoHS 8-DFN 8-DFN Small Flag

FEATURES

DESCRIPTION

MR25H40 - 40MHz/25ns tSCK 4Mb SPI Interface MRAM For more information on product options, see “Table 16 – Ordering Part Numbers” on page 25.

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 Signal Name Pin I/O Function Description CS 1 Input Chip Select An active low chip select for the serial MRAM. When chip select is high, the memory is powered down to minimize standby power, inputs are ignored and the serial output pin is Hi-Z. Multiple serial memories can share a com- mon set of data pins by using a unique chip select for each memory. SO 2 Output Serial Output The data output pin is driven during a read operation and remains Hi-Z at all other times. SO is Hi-Z when HOLD is low. Data transitions on the data output occur on the falling edge of SCK. WP 3 Input Write Protect A low on the write protect input prevents write operations to the Status Register. VSS 4 Refer- ence Ground Power supply ground pin. SI 5 Input Serial Input All data is input to the device through this pin. This pin is sampled on the rising edge of SCK and ignored at other times. SI can be tied to SO to create a single bidirectional data bus if desired. SCK 6 Input Serial Clock Synchronizes the operation of the MRAM. The clock can operate up to 50 MHz to shift commands, address, and data into the memory. Inputs are captured on the rising edge of clock. Data outputs from the MRAM occur on the falling edge of clock. The serial MRAM supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is normally low. In Mode 3, the clock is normally high. Memory operation is static so the clock can be stopped at any time. HOLD 7 Input Hold A low on the Hold pin interrupts a memory operation for another task. When HOLD is low, the current operation is suspended. The device will ignore transitions on the CS and SCK when HOLD is low. All transitions of HOLD must occur while CS is low. VDD 8 Supply Power Supply Power supply voltage from +3.0 to +3.6 volts. Table 1 – Pin Functions Figure 3 – DFN Package Pin Diagram (Top View) CS SO WP V V HOLD SCK SI 5SS DD Pin Functions

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 SPI COMMUNICATIONS PROTOCOL Instruction Description Binary Code Hex Code Address Bytes Data Bytes WREN Write Enable 0000 0110 06h 0 0 WRDI Write Disable 0000 0100 04h 0 0 RDSR 1 Read Status Register 0000 0101 05h 0 1 WRSR Write Status Register 0000 0001 01h 0 1 READ Read Data Bytes 0000 0011 03h 3 1 to ∞ WRITE Write Data Bytes 0000 0010 02h 3 1 to ∞ SLEEP Enter Sleep Mode 1011 1001 B9h 0 0 WAKE Exit Sleep Mode 1010 1011 ABh 0 0 Table 2 – Command Codes The MR2xH40 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1). For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS falls. All memory transactions start when CS is brought low to the memory. The first byte is a command code. Depending upon the command, subsequent bytes of address are input. Data is either input or output. There is only one command performed per CS active period. CS must go inactive before another command can be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or aborted accesses. Command Codes Note: 1. An RDSR command cannot immediately follow a READ command. If an RDSR command immediately follows a READ com- mand, the output data will not be correct. Any other sequence of commands is allowed. If an RDSR command is required immediately following a READ command, it is necessary that another command be inserted before the RDSR is executed. Alternatively, two successive RDSR commands can be issued following the READ command. The second RDSR will output the proper state of the Status Register.

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 WEL SRWD WP Protected Blocks Unprotected Blocks Status Register

0 X X Protected Protected Protected

1 0 X Protected Writable Writable 1 1 Low Protected Writable Protected 1 1 High Protected Writable Writable Table 4 – Memory Protection Modes When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1, status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD, BP0 and BP1. Memory Protection Modes The status register consists of the 8 bits listed in Table 3. As seen in Table 4, the Status Register Write Disable bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) to provide hardware memory block protection. Bits BP0 and BP1 define the memory block arrays that are protected as described in Table 5. The fast writing speed of the MR2xH40 does not require write status bits. The state of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the status register are pre-set from the factory in the “0” state. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRWD Don’t Care Don’t Care Don’t Care BP1 BP0 WEL Don’t Care Table 3 – Status Register Bit Assignments Status Register, Memory Protection and Block Write Protection

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 Table 5 – Block Memory Write Protection The memory enters hardware block protection when the WP input is low and the Status Register Write Dis- able (SRWD) bit is set to 1. The memory leaves hardware block protection only when the WP pin goes high. While WP is low, the write protection blocks for the memory are determined by the status register bits BP0 and BP1 and cannot be modified without taking the WP signal high again. If the WP signal is high (independent of the status of SRWD bit), the memory is in software protection mode. This means that block write protection is controlled solely by the status register BP0 and BP1 block write pro- tect bits and this information can be modified using the WRSR command. Status Register Memory Contents BP1 BP0 Protected Area Unprotected Area 0 0 None All Memory 0 1 Upper Quarter Lower Three-Quarters 1 0 Upper Half Lower Half 1 1 All None Block Protection Modes

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the 24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are read out sequentially from memory until the read operation is terminated by bringing CS high. The entire memory can be read in a single command. The address counter will roll over to 0000H when the address reaches the top of memo- ry. The READ command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi- nated by bringing CS high. Figure 8 – Read Data Bytes (READ) Timing Read Data Bytes (READ) SCK SI SO CS 24-Bit Address High Impedance Instruction (03h) Data Out 1 Data Out 2 0 0 0 0 0 0 1 1 212223 3 7 6 5 4 3 2 1 0 7 2 1 0 MSB MSB 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by the 24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are written sequen- tially in memory until the write operation is terminated by bringing CS high. The entire memory can be written in a single command. The address counter will roll over to 0000H when the address reaches the top of memory. Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed without write delays or data polling. Back to back WRITE commands to any random location in memory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or block organized memory so it is ideal for both program and data storage. The WRITE command is entered by driving CS low, sending the command code, and then sequential write data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS high. Write Data Bytes (WRITE)

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation. The WAKE command is entered by driving CS low, sending the command code, and then driving CS high. The memory returns to standby mode after tRDP . The CS pin must remain high until the tRDP period is over. WAKE must be executed after sleep mode entry and prior to any other command. Figure 11 – Exit Sleep Mode (WAKE) Timing Exit Sleep Mode (WAKE) SCK SI SO CS Sleep Mode Current Mode 3 Mode 0 Standby Current Instruction (ABh) 1 0 1 0 1 0 1 1 0 1 2 3 4 5 6 7 RDPt

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Symbol Parameter Conditions Value Unit VDD Supply voltage 2 -0.5 to 4.0 V VIN Voltage on any pin 2 -0.5 to VDD + 0.5 V IOUT Output current per pin ±20 mA TBIAS Temperature under bias Commercial -10 to 85 °C Industrial -45 to 95 °C Extended -45 to 115 °C AEC-Q100 Grade 1 -45 to 135 °C Tstg Storage Temperature -55 to 150 °C TLead Lead temperature during solder (3 minute max) 260 °C Hmax_write Maximum magnetic field during write Write 12,000 A/m Hmax_read Maximum magnetic field during read or standby Read or Standby 12,000 A/m Notes: 1. All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than 20mA. 2. Power dissipation capability depends on package characteristics and use environment. Table 6 – Absolute Maximum Ratings ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability.

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 Symbol Parameter Temp Grade Min Max Unit VDD Power supply voltage 3.0 3.6 V VIH Input high voltage 2.2 VDD + 0.3 V VIL Input low voltage -0.5 0.8 V TA Ambient temperature under bias Commercial 0 70 °C Industrial -40 85 °C Extended -40 105 °C AEC-Q100 Grade 1 1 -40 125 °C Notes: 1. AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years out of 20-year life.) Table 7 – Operating Conditions Symbol Parameter Conditions Min Max Unit ILI Input leakage current - ±1 μA ILO Output leakage current - ±1 μA VOL Output low voltage IOL = +4 mA - 0.4 V IOL = +100 μA - VSS + 0.2v V VOH Output high voltage IOH = -4 mA 2.4 - V IOH = -100 μA VDD - 0.2 - V Table 8 – DC Characteristics

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 Symbol Parameter Conditions Typical Max Unit IDDR Active Read Current @ 1 MHz 5.0 11 mA @ 40 MHz 12 17 mA @ 50MHz 13.8 18.5 mA IDDW Active Write Current @ 1 MHz 9.0 25 mA @ 40 MHz 28 42 mA @ 50 MHz 33 46.5 mA ISB1 AC Standby Current (CS High) @ 40 MHz 250 400 μA @ 50 MHz 650 750 μA ISB2 CMOS Standby Current (CS High) 90 180 μA IZZ Standby Sleep Mode Current (CS High) 15 40 μA Table 9 – Power Supply Characteristics

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 The MR2xH40 is not accessible for a start-up time, tPU= 400 μs after power up. Users must wait this time from the time when VDD (min) is reached until the first CS low to allow internal voltage references to become stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up sequence. Symbol Parameter Min Typical Max Unit VWI Write Inhibit Voltage 2.2 - - V tPU Startup Time 400 - - μs Table 12 – Power-Up Timing Figure 14 – Power-Up Timing Power Up Timing VDD VDD V (max) VDD(min) WI t PU Time Normal Operation Chip Selection not allowed Reset state of the device

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 Symbol Parameter Temp Range Min Typical Max Unit fSCK SCK Clock Frequency Industrial 0 - 50 MHz tRI Input Rise Time Industrial - - 50 ns tRF Input Fall Time Industrial - - 50 ns tWH SCK High Time Industrial 7 - - ns tWL SCK Low Time Industrial 7 - - ns Synchronous Data Timing see Figure 15 tCS CS High Time Industrial 40 - - ns tCSS CS Setup Time Industrial 5 - - ns tCSH CS Hold Time Industrial 5 - - ns tSU Data In Setup Time Industrial 2 - - ns tH Data In Hold Time Industrial 5 - - ns tV Output Valid Industrial 0 - 9 ns tHO Output Hold Time Industrial 0 - - ns HOLD Timing see Figure 16 Table 13 – MR20H40 (fSCK = 50MHz) AC Timing Parameters AC Timing Parameters Industrial Temperature Range, VDD=3.0 to 3.6 V, CL= 30 pF for all values. tHD HOLD Setup Time Industrial 5 - - ns tCD HOLD Hold Time Industrial 5 - - ns tLZ HOLD to Output Low Impedance Industrial - - 20 ns tHZ HOLD to Output High Imped- ance Industrial - - 20 ns Other Timing Specifications tWPS WP Setup To CS Low Industrial 5 - - ns tWPH WP Hold From CS High Industrial 5 - - ns tDP Sleep Mode Entry Time Industrial 3 - - μs tRDP Sleep Mode Exit Time Industrial 400 - - μs tDIS Output Disable Time Industrial 12 - - ns

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 Table 14 – MR25H40 (fSCK = 40MHz) AC Timing Parameters Commercial Industrial, Extended and AEC-Q100 Grade 1 Temperature Ranges, VDD=3.0 to 3.6 V, CL= 30 pF for all values. Symbol Parameter Temp Grade Min Typical Max Unit fSCK SCK Clock Frequency All 0 - 40 MHz tRI Input Rise Time All - - 50 ns tRF Input Fall Time All - - 50 ns tWH SCK High Time All 11 - - ns tWL SCK Low Time All 11 - - ns Synchronous Data Timing see Figure 15 tCS CS High Time All 40 - - ns tCSS CS Setup Time All 10 - - ns tCSH CS Hold Time All 10 - - ns tSU Data In Setup Time All 5 - - ns tH Data In Hold Time All 5 - - ns tV Output Valid Comm./Ind./Ext. 0 - 9 ns AEC-Q100 Grade 1 0 - 10 ns tHO Output Hold Time All 0 - - ns Table continues next page.

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 HOLD Timing see Figure 16 Symbol Parameter Temp Grade Min Typical Max Unit tHD HOLD Setup Time All 10 - - ns tCD HOLD Hold Time All 10 - - ns tLZ HOLD to Output Low Impedance All - - 20 ns tHZ HOLD to Output High Impedance All - - 20 ns Other Timing Specifications tWPS WP Setup To CS Low All 5 - - ns tWPH WP Hold From CS High All 5 - - ns tDP Sleep Mode Entry Time All 3 - - μs tRDP Sleep Mode Exit Time All 400 - - μs tDIS Output Disable Time All 12 - - ns Table 14 (Cont’d) - MR25H40 (fSCK = 40MHz) AC Timing Parameters Commercial, Industrial, Extended and AEC-Q100 Grade 1 Temperature Ranges, VDD=3.0 to 3.6 V, CL= 30 pF for all values.

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 PART NUMBERS AND ORDERING Table 15 – Part Numbering System Product Family Number MR 25H 40 Memory Interface Density Revision Temp Package Grade Ordering Part Number MR 25H 40 C DC ES MRAM MR

50 MHz Serial Family 20H

40 MHz Serial Family 25H

256 Kb 256

512 Kb 512

1 Mb 10

4 Mb 40

Commercial 0 to 70°C Blank Industrial -40 to 85°C C Extended -40 to 105°C V AEC Q-100 Grade 1 -40 to 125°C M 8-pin DFN in Tray DC 8-pin DFN Tape and Reel DCR 8-pin DFN (small flag) in Tray DF 8-pin DFN (small flag) Tape and Reel DFR Engineering Samples ES Customer Samples Blank Mass Production Blank Product Family Number and Ordering Part Number given are for illustration only.

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 Speed Grade Temp Grade Tempera- ture Package Shipping Con- tainer Order Part Number 50MHz Industrial -40 to +85 C 8-DFN Small Flag Trays MR20H40CDF Tape and Reel MR20H40CDFR

40 MHz

8-DFN 1 Trays MR25H40CDC 1 Tape and Reel MR25H40CDCR 1 8-DFN Small Flag Trays MR25H40CDF Tape and Reel MR25H40CDFR Extended -40 to +105 C 8-DFN Small Flag Trays MR25H40VDF Tape and Reel MR25H40VDFR AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag Trays MR25H40MDF Tape and Reel MR25H40MDFR Table 16 – Ordering Part Numbers Note: 1. The DC pckage option (8-DFN) is not recommended for new designs. Please select the DF (8-DFN small flag) option for new designs.

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 PACKAGE OUTLINE DRAWINGS Figure 17 – DFN Package Outline Exposed metal Pad. Do not connect anything except VSS Notes: 1. Reference JEDEC MO-229. 2. All dimensions are in mm. Angles in degrees. 3. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 4. Warpage shall not exceed 0.10 mm. Dimension A B C D E F G H I J K L M N BSC 0.45 0.05 0.35 Ref. 0.70 4.20 4.20 0.261 C0.35 R0.20 0.05 A D B C G K N H DAP Size 4.4 x 4.4 L M E F 5 8 J I Detail A Detail A Pin 1 Index

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 A D B C G K N H L M E F J I Detail A Detail A Pin 1 Index

0.10 C2X

Figure 18 – DFN Small Flag Package Dimension A B C D E F G H I J K L M N BSC C0.45 R0.20 0.05 Notes: 1. Reference JEDEC MO-229. 2. All dimensions are in mm. Angles in degrees. 3. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 4. Warpage shall not exceed 0.10 mm. Exposed metal Pad. Do not connect anything except VSS

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 Revision Date Description of Change

0 Jan 15, 2010 Product Concept Release

0 .1 Feb. 23, 2010 Fixed typos in text. 1 May 5, 2010 Removed commercial specifications. All parts meet industrial specifications. 2 Jan 11, 2011 Preliminary Product Release. Updated description of status register non-volatility, WAKE command, Table 3.4. 3 Apr 25, 2011 Removed DIP package part to seperate datasheet. Added inset detail for mechanical pack- age drawings.

4 September 22,

revised and Note 2 deleted, revised Figure 5.1 and Table 5.1.

5 Nov 18, 2011

New Small Flag DFN package option added to Page 1 Features and available parts Table 5.1. DFN Small Flag drawing and dimensions table added as Figure 6.2. Figure 6.1, DFN Pack- age, cleaned up with better quality drawing and dimension table. No specifications were changed in Figure 6.1.

6 August 23, 2012

CDF and CDFR options changed to Preliminary. Added Small Flag DFN illustrations. Refor- matted all parametric tables. Revised 8-DFN package drawing to show correct proportion for flag and package. Added MR20H40 as 50MHz speed option. Deleted large flag DFN ordering option for AEC-Q100 products. Corrected errors in DFN package outline drawings.

7 January 17,

2013 Removed Preliminary status from MR25H40CDF, CDFR. 8 May 24, 2013 Removed Preliminary status from MR20H40CDF(R), and from MR20H40DF(R). 9 March 28, 2014 Removed Preliminary status from 25H40MDF(R). VWI max to unspecified from TBD. Added MSL-3 status to the Features list. 10 July 11, 2014 MR20H40DF and MR20H40DFR withdrawn from sales status. 11 August 13, 2014 Added Extended temperature grade offering. 11.1 May 19, 2015 Revised Everspin contact information. 11.2 June 11, 2015 Corrected Japan Sales Office telephone number.

12.0 December 9,

2015 Clarification of RDSR command operation.

12.1 December 18,

Minor edits to the revised RDSR command operation. Corrected wrong bit number for the WEL in the WRDI command description. Clarification of SRWD bit location in the Status Reg- ister within the WRSR command description. Condensed Note 1 in Table 2, referring to RDSR operation after a READ command.

REVISION HISTORY

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6, 8/2020 REVISION HISTORY - Cont’d Revision Date Description of Change

12.2 December 13,

Change all large flag DFN options to “The DC pckage option (8-DFN) is not recommended for new designs. Please select the DF (8-DFN small flag) option for new designs.”

12.3 February 2, 2017 Added tHO and tV relationship to Synchronous Data Timing

12.4 March 23, 2018 Updated the Contact Us table

12.5 December 16,

Corrected sentence in Block Protection Modes section on page 9 to ” The memory enters hardware block protection when the WP input is low and the Status Register Write Disable (SRWD) bit is set to 1” . 12.6 August 7, 2020 Added a Commercial temperature range product option to MR25H40 family.

Copyright © Everspin Technologies 2020 MR20H40 / MR25H40 MR20H40 / MR25H40 Revision 12.6 8/2020 Information in this document is provided solely to enable system and soft- ware implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representa - tion or guarantee regarding the suitability of its products for any particu - lar purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each cus - tomer application by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of oth - ers. Everspin Technologies products are not designed, intended, or au - thorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may oc - cur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affili - ates, and distributors harmless against all claims, costs, damages, and ex - penses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright © Everspin Technologies, Inc. 2020 Everspin Technologies, Inc. HOW TO REACH US How to Reach Us: Home Page: www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com