MR10Q010

MR10Q010 EVERSPIN | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 72

Technical content

Copyright © 2018 Everspin Technologies, Inc. MR10Q010

• High bandwidth – Read and Write at 52MB/sec
• Quad I/O with the use of dual purpose pins to maintain a low pin count
• Operates in both standard, single SPI mode and high speed quad SPI mode
• Fast quad Read and Write with quad address input and quad I/O
• Intended for next generation RAID controllers, server system logs, storage device buffers, and embedded system data and program memory
• Data is non-volatile with retention greater than 20 years
• Automatic data protection on power loss
• Unlimited write endurance
• Low-current sleep mode
• Dual 3.3v VDD / 1.8v VDDQ power supply
• Tamper Detect function will detect possible data modification from outside mag- netic fields.
• Quad Peripheral Interface (QPI) mode is supported to enhance system performance for Execute in Place (XIP) operation.
• MSL Level 3. The MR10Q010 is the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of pins, low power, and choice of a 24-ball BGA or a 16-pin SOIC package. The four I/O’s in Quad SPI mode allow very fast reads and writes, making it an attractive alternative to conventional parallel data bus inter- faces in next generation RAID controllers, server system logs, storage device buffers, and embedded system data and program memory. Using Everspin’s patented MRAM technology, both reads and writes can occur randomly in memory with no delay between writes. Standard Serial Peripheral Interface (SPI), Quad SPI and Quad Peripheral Interface (QPI) modes are supported at a clock rate up to 104MHz. XIP operation is supported for Read commands in all three modes. The MR10Q010 Quad SPI MRAM is organized as 131,072 words of 8 bits. 16-SOIC

DESCRIPTION

1 Mb High Speed Quad SPI MRAM

Mode Command Set Utility Commands XIP Command Operation SPI Mode Read 40MHz. Write, Fast Read 104MHz Write Enable/Disable, Sleep Mode, Read/Write Status Register, Tamper Detect, Read Device ID, Enable QPI Mode Fast Read Quad SPI Mode Quad I/O mode Read/Write data, or both address and data None. Fast Read Quad Output, Fast Read Quad Address and Data QPI Mode Enables command instruction entry in quad I/O mode. (2 clocks) Disable QPI Mode. Fast Read, Fast Read Quad Output, Fast Read Quad Address and Data Operational Overview

FEATURES

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 The Serial Peripheral Interface, SPI, is becoming increasingly popular in system design due to the reduced pin count of the serial interface and increasing data bandwidth offered when compared against x8 or x16 parallel interface architectures. The SPI interface has evolved from a single data line to a four data line, or quad architecture. This interface provides a data bandwidth in excess of 50Mbytes/sec. SPI is currently well-established in microcontroller/microprocessor based systems. The Everspin family of single I/O SPI MRAM is popular in smart meter applications and a variety of other embedded systems. How- ever, the 40MHz limitation with a single data I/O may be too slow for higher performance applications such as the next generation RAID controllers, server system logs, and storage device buffers . Operating at 52MB/second for both Read and Write the Everspin 1Mb Quad I/O SPI MRAM will meet the needs of these applications. And as a non-volatile memory with over 20 years of data retention, this SPI memory family is equally suited for embedded system data and program memory. The Quad Peripheral Interface, QPI, mode provides a lower overhead to load commands, which will improve system throughput when operating in an Execute in Place, XIP , environment. This added feature will make the device attractive in embedded applications that store program code in an external memory. QPI effec- tively increases the effective clock rate and, when combined with Quad SPI instructions, Quad SPI memory performance will outstrip asynchronous parallel memories. OVERVIEW Table 1 – Operational Parameters Summary Density Interface Voltage (V) Read/ Write Active Current R/W (mA) Standby Current (mA) Sleep Current (μA) Package 1 Mb 104MHz Quad SPI 3.3v VDD 1.8v VDDQ 52MB/sec 60/100 8.0 100 16-SOIC Operation in 3.3v Data Bus Systems - Evaluation Board Available The Everspin MR10Q010 Quad SPI Serial MRAM requires a 3.3v VDD power supply and is designed to operate on a 1.8v I/O bus. Adapting the MR10Q010 to operate on a 3.3v data bus can be done by interfacing it to the bus through a level translator. An evaluation board is available to test this adaptation of the MR10Q010 in an existing system. It can be connected to the bus at the board position currently occupied by a SPI or Quad SPI E2PROM and operate with the MR10Q010 I/O levels translated for operation on a 3.3v bus. Contact Everspin for more information about the MR10Q010 3.3v evaluation board and adapting your 3.3v bus system to operate with MR10Q010 MRAM.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 1 – MR10Q010 Block Diagram SCK WP or I/O2 HOLD or I/O3 SO or I/O1 Data I/O Register Instruction Decode Control Logic Write Protect Clock Generator Nonvolatile Status Register 1 Mb SPI MRAM Array CS Serial I/O Interface SI or I/O0 Address Register Counter

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 MOSI or I/O0 MISO or I/O1 (Master Out - Slave In) SCK SCK CS SPI Micro Controller SO I/O1 WP I/O2 SI I/O0 HOLD or I/O3 (1) CS (1) WP or I/O2 (1) HOLD I/O3 SCK CS SO I/O1 WP I/O2 SI I/O0 HOLD I/O3 HOLD or I/O3 (2) CS (2) WP or I/O2 (2) (Master In - Slave Out) Figure 2 – System Configuration

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Table 2 – 16-SOIC Pin Functions Signal Name Pin SPI Mode Quad SPI Mode 1 Description CS 7 Chip Select Chip Select An active low chip select for the serial MRAM. When chip select is high, the memory is powered down to minimize standby power, inputs are ignored and the serial output pin is Hi-Z. Multiple serial memories can share a common set of data pins by using a unique chip select for each memory. SO (I/O1) 8 Serial Output I/O 1 SPI Mode: The data output pin is driven during a read operation and remains Hi-Z at all other times. SO is Hi-Z when HOLD is low. Data transitions on the data output occur on the falling edge of SCK. Quad SPI Mode: Bidirectional I/O to serially write instructions, ad- dresses or data to the device on the rising edge of SCK or read data output from the device on the falling edge of SCK. Table continues on next page. 16-SOIC16-SOIC HOLD (I/O 3) VDDQ NC VDD NC VDD NC VSS NC VSS SCK SI (I/O 0) VSSQ SO (I/O 1) CS WP (I/O 2) TOP VIEW Figure 3 – 16-SOIC Package Pin Assignments

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 16-SOIC Pin Functions - Continued Signal Name Pin SPI Mode Quad SPI Mode 1 Description WP (I/O2) 9 Write Protect I/O 2 SPI Mode: A low on the write protect input prevents write opera- tions to the Status Register. Quad SPI Mode: Bidirectional I/O to serially write instructions, ad- dresses or data to the device on the rising edge of SCK or read data output from the device on the falling edge of SCK. VSS 11, 14 Ground Ground Power supply ground pin. VSSQ 10 Ground Ground I/O Voltage ground pin. SI (I/O0) 15 Serial Input I/O 0 SPI Mode: All data is input to the device through this pin. This pin is sampled on the rising edge of SCK and ignored at other times. SI can be tied to SO to create a single bidirectional data bus if desired. Quad SPI Mode: Bidirectional I/O to serially write instructions, ad- dresses or data to the device on the rising edge of SCK or read data output from the device on the falling edge of SCK. SCK 16 Clock Clock Synchronizes the operation of the MRAM. The clock can operate up to 104 MHz to shift commands, address, and data into the memory. Inputs are captured on the rising edge of clock. Data outputs from the MRAM occur on the falling edge of clock. The serial MRAM sup- ports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is normally low. In Mode 3, the clock is normally high. Memory operation is static so the clock can be stopped at any time. HOLD (I/O3) 1 HOLD I/O 3 SPI Mode: A low on the HOLD pin interrupts a memory operation for another task. When HOLD is low, the current operation is sus- pended. The device will ignore transitions on the CS and SCK when HOLD is low. All transitions of HOLD must occur while CS is low. Quad SPI Mode: Bidirectional I/O to serially write instructions, ad- dresses or data to the device on the rising edge of SCK or read data output from the device on the falling edge of SCK. VDD 3, 6 Power Supply Power Supply Power supply voltage from +3.0 to +3.6 volts. VDDQ 2 I/O Bus Power Supply I/O Bus Power Supply I/O Bus supply voltage from +1.7 volts to +1.9 volts.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Table 3 – 24-BGA Ball Functions Signal Name Ball SPI Mode Quad SPI Mode 1 Description CS C2 Chip Select Chip Select An active low chip select for the serial MRAM. When chip select is high, the memory is powered down to minimize standby power, inputs are ignored and the serial output pin is Hi-Z. Multiple serial memories can share a common set of data pins by using a unique chip select for each memory. SO (I/O1) D2 Serial Output I/O 1 SPI Mode: The data output pin is driven during a read operation and remains Hi-Z at all other times. SO is Hi-Z when HOLD is low. Data transitions on the data output occur on the falling edge of SCK. Quad SPI Mode: Bidirectional I/O to serially write instructions, ad- dresses or data to the device on the rising edge of SCK or read data output from the device on the falling edge of SCK. Table continues on next page. Figure 4 – 24-BGA Package Ball Assignments 1 2 3 4 5 ABCDE NCNC NC NC NC SCK NC NC NC NC NC NC NC NC NC NC VDD VSS VDDQ CS WP IO₂ SO IO₃IO₁ SO IO₀ HOLD

• 24-ball BGA package.
• 8mm x 6mm package outline.
• Serial NOR Flash pinout compatible.
• VDDQ on ball E4 to support 1.8v I/O.
• No VSSQ ball.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 24-BGA Ball Functions - Continued Signal Name Ball SPI Mode Quad SPI Mode 1 Description WP (I/O2) C4 Write Protect I/O 2 SPI Mode: A low on the write protect input prevents write opera- tions to the Status Register. Quad SPI Mode: Bidirectional I/O to serially write instructions, ad- dresses or data to the device on the rising edge of SCK or read data output from the device on the falling edge of SCK. VSS B3 Ground Ground Power supply ground pin. SI (I/O0) D3 Serial Input I/O 0 SPI Mode: All data is input to the device through this pin. This pin is sampled on the rising edge of SCK and ignored at other times. SI can be tied to SO to create a single bidirectional data bus if desired. Quad SPI Mode: Bidirectional I/O to serially write instructions, ad- dresses or data to the device on the rising edge of SCK or read data output from the device on the falling edge of SCK. SCK B2 Clock Clock Synchronizes the operation of the MRAM. The clock can operate up to 104 MHz to shift commands, address, and data into the memory. Inputs are captured on the rising edge of clock. Data outputs from the MRAM occur on the falling edge of clock. The serial MRAM sup- ports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is normally low. In Mode 3, the clock is normally high. Memory operation is static so the clock can be stopped at any time. HOLD (I/O3) D4 HOLD I/O 3 SPI Mode: A low on the HOLD pin interrupts a memory operation for another task. When HOLD is low, the current operation is sus- pended. The device will ignore transitions on the CS and SCK when HOLD is low. All transitions of HOLD must occur while CS is low. Quad SPI Mode: Bidirectional I/O to serially write instructions, ad- dresses or data to the device on the rising edge of SCK or read data output from the device on the falling edge of SCK. VDD B4 Power Supply Power Supply Power supply voltage from +3.0 to +3.6 volts. VDDQ E4 I/O Bus Power Supply I/O Bus Power Supply I/O Bus supply voltage from +1.7 volts to +1.9 volts.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 The status register consists of the 8 bits shown in Table 3 below. The Status Register Write Disable bit (SRWD, Bit 7) is used in conjunction with the Write Enable Latch (WEL, bit 1) and the Write Protection pin (WP) to provide hardware memory block protection. Their usage for memory block protection is defined in “Table 5 – Memory Protection Modes” . The Status Register Write Dis- able bit is non-volatile and will remain set whenever power is removed from the memory. The WEL bit (Bit 7) is volatile and set by the Write Enable command. It is set to “0” at power up and reset to “0” when recovering from a loss of power. The status of memory block protection is indicated by the states of bits BP0 and BP1 (Bits 2 and 3) and are also defined in “Table 5 – Memory Protection Modes” on page 15. BP0 and BP1 are non-volatile and re- main set if power is removed from the memory. The QPI Mode bit (Bit 6) indicates whether the memory is in QPI mode or not. Its value is set when the En- able QPI (EQPI) or Disable QPI (DQPI) commands are invoked. Logic “1” indicates QPI mode is enabled. The QPI Mode Bit is volatile and set to “0” at power up and reset to “0” when recovering from a loss of power. The fast writing speed of the MR10Q010 does not require write status bit information (Normally Bit 0). The state of reserved bits 4, 5, and 0 can be modified by the user but do not affect memory operation. All bits in the status register are pre-set at the factory to the “0” state. Non-reserved Status Register bits are non-volatile with the exception of the WEL and QPI Mode which are reset to 0 upon power cycling. STATUS REGISTER Table 4 – Status Register Bit Definitions Bit Definitions: 7 - SRWD - Status Register Write Disable 6 - QPI Mode bit. Logic 1 = The device is in QPI Mode. Set by the Enable QPI (page 40) and Disable QPI Commands (page 41). Cannot be modified by the Write Status Register Command (page 21). Reset to “0” upon any power cycling. 5 - R2 - Reserved bit 2 4 - R1 - Reserved bit 1 3 - BP1 - Block Protect bit 1 2 - BP0 - Block Protect bit 0 1 - WEL - Write Enable Latch bit. Set by the Write Enable (page 19) Command. Reset to “0” upon any power cycling. 0 - R0 - Reserved bit 0. This is the “Write in Progress” bit for many memory devices. For MR10Q010, the “Write in progress” bit (bit 0) is not written by the memory because there is no write delay with MRAM. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRWD (Non volatile) QPI Mode (Volatile) R2 R1 BP1 (Non-Volatile) BP0 (Non-Volatile) WEL (Volatile) R0

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 WEL SRWD WP Protected Blocks Unprotected Blocks Status Register

0 X X Protected Protected Protected

1 0 X Protected Writable Writable 1 1 Low Protected Writable Protected 1 1 High Protected Writable Writable Table 5 – Memory Protection Modes Table 6 – Block Memory Write Protection The memory enters hardware block protection when the WP input is low and the Status Register Write Dis- able (SRWD) Bit is set to 1. The memory leaves hardware block protection only when the WP pin goes high. While WP is low, the write protection blocks for the memory are determined by the status register bits BP0 and BP1 and cannot be modified without taking the WP signal high again. If the WP signal is high (independent of the status of SRWD Bit), the memory is in software protection mode. This means that block write protection is controlled solely by the status register BP0 and BP1 block write pro- tect bits and this information can be modified using the WRSR command. Status Register Memory Contents BP1 BP0 Protected Area Unprotected Area 0 0 None All Memory 0 1 Upper Quarter Lower Three-Quarters 1 0 Upper Half Lower Half 1 1 All None Block Protection Modes When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1, status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD, BP0 and BP1. Memory Protection Modes

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 SPI MODE COMMANDS All memory transactions start when CS is brought low, selecting the memory. The first byte is an 8-bit com- mand code in hexadecimal. The subsequent 24 bits entered are address input. Following the address input (except for the FREAD command) the device will read/write data beginning at the address entered. For the FREAD command the Mode Byte must be entered following the address. The Mode Byte will either set or reset the XIP mode. See ”Execute in Place (XIP) Mode” on page 42. There is only one command performed per CS active period. CS must go inactive before another command can be accepted. Note: To avoid partial or aborted accesses, memory access must remain active (CS low) for a multiple of 8 clocks from CS going low (the end of a byte.) At power up, the default operational mode is SPI mode. SPI COMMUNICATIONS PROTOCOL The MR10Q010 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1). For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS falls. All memory transactions start when CS is brought low to the memory. The first byte is a command code. Depending upon the command, subsequent bytes of address are input. Data is either input or output. There is only one command performed per CS active period. CS must go inactive before another command can be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping to avoid partial or aborted accesses.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Name Operation Code Description RDSR Read Status Register 05h Returns the contents of the 8 Status Register bits. WREN Write Enable 06h Sets the Write Enable Latch (WEL) bit in the status register to 1. WRDI Write Disable 04h Sets the Write Enable Latch (WEL) bit in the status register to 0. WRSR Write Status Register 01h Writes new values to the entire Status Register. READ Read Data Bytes 03h Continuously reads data bytes starting at an initial address specified. FREAD 1 Fast Read Data Bytes 0Bh High-speed READ with XIP operation option. WRITE Write Data Bytes 02h Continuously writes data bytes starting at an address specified. SLEEP Enter Sleep Mode B9h Initiates Sleep Mode. WAKE Exit Sleep Mode ABh Terminates Sleep Mode. TDET Tamper Detect 17h Returns 4 data bytes indicating corrupted or uncorrupted memory. RDID Read ID 4Bh Returns the Everspin device ID assigned by JEDEC. Table 7 – SPI Mode Commands Overview SPI Mode Commands Overview Notes: 1. FREAD has the option of using XIP operational mode. See “Execute in Place (XIP) Mode” on page 42 for details of XIP mode with the FREAD command.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 The Status Register can be read at any time to check the status of the Write Enable Latch Bit, status register Write Protect Bit, QPI mode, and the block write protect bits. The RDSR command is entered by driving CS low, sending the command code, and then driving CS high. See “Table 3 – Status Register Bit Definitions” on page 11 for Status Register Bit definitions. Read Status Register (RDSR) Figure 5 – Read Status Register (RDSR) Command Operation SCK SI SO CS Status Register Bits High Impedance High Z 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 1 0 1 7 6 5 4 3 2 1 0 Instruction (05h) Mode 3 Mode 0 Clock Number 2 Name Operation 0 - 7 1 8 - 15 16 - 23 24 - 31 32 - 39 40 - n RDSR Read Status Register 05h S7-S0 3 - - - - Notes: 1. Clocks 0 - 7 are the command byte. 2. See “AC Timing Parameters” on page 61 for timing requirements. 3. See “Table 3 – Status Register Bit Definitions” on page 11 for status register bit definitions.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 The Write Enable (WREN) command sets the Write Enable Latch Bit (WEL) in the status register (Bit 1). The Write Enable Latch must be set prior to writing in the status register or the memory. The WREN command is entered by driving CS low, sending the command code, and then driving CS high. See “Table 3 – Status Register Bit Definitions” on page 11 for Status Register Bit definitions. Write Enable (WREN) Figure 6 – Write Enable (WREN) Command Operation SI SO CS Instruction (06h) High Impedance Mode 3 Mode 0 Mode 3 Mode 0 10 2 3 4 5 6 7 0 0 0 0 0 1 1 0 SCK Clock Number 1 Name Operation 0 - 7 2 8 - 15 16 - 23 24 - 31 32 - 39 40 - n WREN Write Enable 06h - - - - - Notes: 1. See “AC Timing Parameters” on page 61 for timing requirements. 2. Clocks 0 - 7 are the command byte.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 7 – Write Disable (WRDI) Command Operation Write Disable (WRDI) SCK SI SO CS Instruction (04h) High Impedance Mode 3 Mode 0 Mode 3 Mode 0 10 2 3 4 5 6 7 0 0 0 0 0 1 0 0 The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 1) to 0. This prevents writes to status register or memory. The WRDI command is entered by driving CS low, sending the command code, and then driving CS high. The Write Enable Latch (WEL) is reset to 0 on power-up or when the WRDI command is completed. See “Table 3 – Status Register Bit Definitions” on page 11 for Status Register bit definitions. Clock Number 1 Name Operation 0 - 7 2 8 - 15 16 - 23 24 - 31 32 - 39 40 - n WRDI Write Disable 04h - - - - - Notes: 1. See “AC Timing Parameters” on page 61 for timing requirements. 2. Clocks 0 - 7 are the command byte.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 The Write Status Register (WRSR) command allows new values for certain bits to be written to the Status Register. The WRSR command cannot be executed unless the Write Enable Latch (WEL) has been set to 1 by executing a WREN command while pin WP the SRWD Bit correspond to values that make the status register writable as seen in Table 5 on page 15. QPI Mode Bit, Bit 6, and the WEL Bit, Bit 0, are set by other commands and cannot be changed by this com- mand. The WRSR command is entered by driving CS low, sending the command code and status register write data byte, and then driving CS high. Figure 8 – Write Status Register (WRSR) Command Operation Write Status Register (WRSR) SCK SI SO CS Status Register In High Impedance Instruction (01h) 0 0 0 0 0 0 0 1 7 6 (DC) 5 4 3 2 1 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15Mode 3 Mode 0 0 (DC) Clock Number Name Operation 0 - 7 1 8 - 15 2 16 - 23 24 - 31 32 - 39 40 - n WRSR Write Status Register 01h S7-S0 - - - - Notes: 1. Clocks 0 - 7 are the command byte. 2. Neither the QPI Mode Bit, Bit 6, or the WEL Bit, bit 0, can be changed by this command. Notes: 1. Neither the QPI Mode Bit, Bit 6, or the WEL Bit, bit 0, can be changed by this command. Treat as Don’t Care.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 The Read Data Bytes (READ) command allows data bytes to be continuously read starting at an initial ad- dress specified by the 24-bit address entry. The data bytes are read out sequentially from memory until the read operation is terminated by bringing CS high. The entire memory can be read in a single command. The address counter will roll over to 0000H when the address reaches the top of memory. The READ command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the SO pin. Reads continue as long as the memory is clocked. (Maximum READ clock frequency 40MHz.) The command is terminated by bringing CS high. Figure 9 – Read Data Bytes (READ) Command Operation Read Data Bytes (READ) SCK SI SO CS 24-Bit Address High Impedance Instruction (03h) Data Out 1 Data Out 2 0 0 0 0 0 0 1 1 212223 3 7 6 5 4 3 2 1 0 7 2 1 0 MSB 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Data Clocked Out Continuously until CS high. Mode 3 Mode 0 Clock Number Name Operation 0 - 7 1 8 - 15 16 - 23 24 - 31 32 - 39 40 - n READ Read Data Bytes 03h A23-A16 A15-A8 A7-A0 D7-D0, until CS high Notes: 1. Clocks 0 - 7 are the command byte. 2. For timing details, see “Figure 35 – Synchronous Data Timing (READ)” on page 63.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Fast Read Data Bytes (FREAD) The Fast Read Data Bytes FREAD command is similar to the READ command except that the device can be operated at the highest frequency (fSCK = 104MHz ) and the command has an XIP operation option. For more detail on the XIP option, see “Table 13 – XIP Mode with FREAD Command” on page 43. The FREAD command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi- nated by bringing CS high. Figure 10 – Fast Read Data Bytes (FREAD) Command Operation SCK CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SI 24-Bit AddressInstruction (0Bh) 0 0 0 0 1 0 1 1 212223 3 2 1 0 MSB SO High Impedance LSB CS SCK 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SI Mode Bits Set /Reset XIP Mode SO High Impedance 7 6 5 4 3 2 1 0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 Mode 3 Mode 0

0 M5 M4M7 M6 M3 M2 M1 M0

Data Clocked Out Continuously until CS high. Clock Number Name Operation 0 - 7 1 8 - 15 16 - 23 24 - 31 32 - 39 40 - n FREAD Fast Read Data Bytes 0Bh A23-A16 A15-A8 A7-A0 Mode bits 2 (7-0) D7-D0, until CS high Notes: 1. Clocks 0 - 7 are the command byte. 2. Mode Byte to Set/Reset XIP operation. Set/Continue XIP Mode = EFh. Reset XIP Mode FFh (exit XIP). See “Execute in Place (XIP) Mode” on page 42 for more detailed information on XIP operation with FREAD. 3. For timing details, see “Figure 36 – Synchronous Data Timing Fast Read (FREAD)” on page 63.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 11 – Write Data Bytes (WRITE) Command Operation The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by the 24-bit address. The data bytes are written sequentially in memory until the write operation is terminat- ed by bringing CS high. The entire memory can be written in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. MRAM is a random access memory rather than a page, sector, or block organized memory so it is ideal for both program and data storage. Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed without write delays or data polling. Back to back WRITE commands to any random location in memory can be executed without write delay. The WRITE command is entered by driving CS low, sending the command code, and then sequential write data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS high. Write Data Bytes (WRITE) SCK SI SO CS 24-Bit Address High Impedance Instruction (02h) 0 0 0 0 0 0 1 0 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39Mode 3 Mode 0 Data Byte 1 SCK SI SO CS Data Byte 3 High Impedance Data Byte NData Byte 2 34 2 1 0 7 6 5 4 3 2 1 0 MSB 7 6 5 4 3 2 1 0 7 6 5 MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Clock Number Name Operation 0 - 7 1 8 - 15 16 - 23 24 - 31 32 - 39 40 - n WRITE Write Data Bytes 02h A23-A16 A15-A8 A7-A0 D7-D0, until CS high Notes: 1. Clocks 0 - 7 are the command byte. 2. For timing details see “Figure 37 – Synchronous Data Timing (WRITE)” on page 64.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall chip standby power to 15 μA typical. The SLEEP command is entered by driving CS low, sending the com- mand code, and then driving CS high. The standby current is achieved after time, tDP . See “Table 23 – AC Timing Parameters” on page 61 for the tDP value. If power is removed when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid command following SLEEP mode entry is a WAKE command. Figure 12 – Enter Sleep Mode (SLEEP) Command Operation Enter Sleep Mode (SLEEP) SCK SI SO CS Standby CurrentActive Current Mode 3 Mode 0 Sleep Mode Current Instruction (B9h) 1 0 1 1 1 0 0 1 0 1 2 3 4 5 6 7 DPt Clock Number Name Operation 0 - 7 1 8 - 15 16 - 23 24 - 31 32 - 39 40 - n SLEEP Enter Sleep Mode B9h - - - - - Notes: 1. Clocks 0 - 7 are the command byte.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 13 – Exit Sleep Mode (WAKE) Command Operation Exit Sleep Mode (WAKE) SCK SI SO CS Sleep Mode Current Standby Current Instruction (ABh) 1 0 1 0 1 0 1 1 0 1 2 3 4 5 6 7 RDPt Mode 3 Mode 0 The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation. The WAKE command is entered by driving CS low, sending the command code, and then driving CS high. The memory returns to standby mode after tRDP . See “Table 23 – AC Timing Parameters” on page 61 for the tRPD value. The CS pin must remain high until the tRDP period is over. WAKE must be executed after sleep mode entry and prior to any other command when the device is in Sleep mode. Clock Number Name Operation 0 - 7 1 8 - 15 16 - 23 24 - 31 32 - 39 40 - n WAKE Exit Sleep Mode ABh - - - - - Notes: 1. Clocks 0 - 7 are the command byte.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Tamper Detect (TDET) The Tamper Detect command is used to check whether the memory contents have been corrupted by ex- posure to external magnetic fields. The command is invoked by entering the command code followed by the 8-bit Mode Byte. The device reads dedicated pre-programmed memory bits located around the memory physical array. The contents of these bits are compared to reference bits that are hard programmed into the device via a metal mask. The result of the comparison is returned in 32 status bits of data on SO beginning after the last Mode Byte clock. All 0’s in the 32 TDET status bits indicates that the tamper check bits are correct against the reference bits and the memory has not been corrupted. Presence of any 1’s in the 32-bit string indicates that at least one of the check bits does not match its reference bit and the memory contents have likely been corrupted. Following CS high, any new command can be entered on the next access, except another TDET command. If it is necessary to immediately enter another TDET command, a Tamper Detect Exit (TDETX) command must be issued first to reset the device for another Tamper Detect sequence. Figure 14 – Tamper Detect (TDET) Command Operation TDET Status Bits CS SCK SI SO Instruction (4Bh) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 44 45 460 Mode Bits 0 1 0 0 11 0 1 T31 T30 T29 T3 T2 T1 T0 High Impedance High-Z Don’t Care M7 M6 M5 M4 M3 M2 M1 M0 1 1 1 1 1 1 1 1 Don’t Care Clock Number Name Operation 0 - 7 1 8 - 15 16 - 47 48 - n TDET Tamper Detect 17h Mode Byte bits 7 - 0 3 T31 - T0 2 CS high Notes: 1. Clocks 0 - 7 are the command byte. 2. 32 Tamper Detect indication bits. Any 1’s present in the 32-bit string indicate probable corruption of the memory contents. 3. In the TDET command operation, the Mode Byte is used as a time delay to read the check and reference bits. The Mode Byte must be set to FFh. Notes: 1. In the TDET command operation, the Mode Byte must be set to FFh.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 15 – Tamper Detect Exit (TDETX) Command Operation Clock Number Name Operation 0 - 7 1 8 - n 2 TDETX Tamper Detect Exit 07h CS high. Any command can be entered on next access. Notes: 1. Clocks 0 - 7 are the command byte. 2. After CS goes high any other command can be given on the next access. Tamper Detect Exit (TDETX) After running a TDET command, any other command can be run as the next command, except another TDET command. If another TDET command is to be run, then the Tamper Detect Exit (TDETX) command must be run first to reset the device. This is necessary only if immediately running another TDET command. See “Tamper Detect (TDET)” on page 27.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Read ID (RDID) The Read Device ID command (RDID) returns 40 bits of information that identify the Everspin device. The command is invoked with CS low, and sending command code 4Bh on the Serial Input (SI) pin. See “Fig- ure 16 – Read ID (RDID) Command Operation” below. After 8 clocks for the Mode Byte, 40 bits of data uniquely identifying the Everspin device are returned on the Serial Out (SO) pin. See “Table 8 – Device ID for MR10Q010” . If CS remains low after reading the 40 ID bits, additional clocks with CS low will return zeros on SO until CS goes high. Figure 16 – Read ID (RDID) Command Operation Device ID Data Bits CS SCK SI SO Instruction (4Bh) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 50 51 520 Mode Bits 0 1 0 0 1 0 Bit 39 Bit 38 Bit 37 Bit 36 Bit 35 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5453 High Impedance High-Z Don’t Care Mode 3 Mode 0 1 1 M7 M6 M5 M4 M3 M2 M1 M0 1 1 1 1 1 1 1 1 Notes: 1. Clocks 0 - 7 are the command byte. 2. In the RDID command operation, the Mode Byte is used as a time delay to read the device ID bits. The Mode Byte must be set to FFh. 3. For the Everspin device ID codes, see “Table 8 – Device ID for MR10Q010” on page 30. Clock Number Name Operation 0 - 7 1 8 - 15 16 - 23 24 - 31 32 - 39 40 - n RDID Read ID 4Bh Mode Byte 2 Bits 7 - 0 Device ID 3 Clocks 16 - 55 Notes: 1. In the RDID command operation, the Mode Byte must be set to FFh.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Complete Hexadecimal and Binary Device ID for MR10Q010 Hexadecimal 076B111111 Binary 0000_0111_0110_1011_0001_0001_0001_0001_0001_0001 RDID Device ID for MR10Q010 Bit # 39 - 24 23 - 20 19 - 16 15 - 12 11 - 8 7 - 4 3 - 0 Meaning Manufacturer’s ID (JEP 106AH) Technology Interface Speed Density Voltage Die Rev MR10Q010 6Bh, eighth bank Toggle MRAM Quad IO SPI 104MHz 1 Mb 3.3v VDD / 1.8v VDDQ A Binary 0000_0111_0110_1011 0001 0001 0001 0001 0001 0001 Table 8 – Device ID for MR10Q010

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 QUAD SPI MODE COMMANDS Quad SPI commands allow data to be transferred to or from the device at least four times the rate of conven- tional SPI mode. When using Quad SPI commands the DI and DO pins become bidirectional IO0 and IO1, and the WP and HOLD pins become IO2 and IO3 respectively. Address and data information can be input to the device on four IO’s and data output can be read from four IO’s, offering a significant improvement in continu- ous and random access transfers. XIP mode operation is available for FRQO and FRQAD commands. Name Operation Code Description FRQO 1 Fast Read Quad Output 6Bh Initial address entry on IO0, returns data continuously in Quad SPI Mode on all four I/O. Has XIP operation option. FWQD Fast Write Quad Data 32h Initial address entry on IO0, writes data continuously in Quad SPI Mode on all four I/O. FRQAD 1 Fast Read Quad Address and Data EBh Initial address entry on all four IO’s, returns data continuously in quad mode on all four I/O’s. Has XIP operation option. FWQAD Fast Write Quad Address and Data 12h Initial address entry on all four IO’s, writes data continuously in quad mode on all four I/O’s. Table 9 – Quad SPI Mode Commands Overview Quad SPI Mode Commands Overview Notes: 1. XIP mode option. See “Execute in Place (XIP) Mode” on page 42 for details of how to use FRQD and FRQAD in XIP mode.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Fast Read Quad Output (FRQO) The Fast Read Quad Output (6Bh) command is similar to the Fast Read Output except that a data byte is output on the four I/O pins, requiring only two clocks. An XIP mode is available for this command. See “Table 14 – XIP Operation with FRQO Command” on page 47 for more information about XIP mode op- eration. The I/O pins should be high impedance prior to the falling edge of the first Mode clock. The FRQO command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the IO pins. Reads continue as long as the memory is clocked. The command is terminated by bringing CS high. Commmand Operation and Timing next page.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 SCK CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 24-Bit AddressInstruction (6Bh) 0 1 1 0 1 0 1 1 212223 3 2 1 0 MSB LSB Mode 3 Mode 0 IO0 IO1 High Impedance IO2 IO3 SCK CS 31 32 33 34 35 36 37 38 39 40 41 Mode Bits IO0 0 IO1 IO2 IO3 IO switches from Input to Output 404 0 4 0 4 0 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 (Low) LSB High High M0M4 M1M5 M2M6 M3M7 Data Clocked Out Continuously until CS high. Set / Reset XIP 1 Note: 1. The I/O pins should be high impedance prior to the falling edge of the second mode clock. Figure 17 – Fast Read Quad Output (FRQO) Command Operation Clock Number Name Title 0 - 7 1 8 - 15 16 - 23 24 - 31 32 - 33 34 - 35 36 - n FRQO Fast Read Quad Output 6Bh A23-A16 A15 - A8 A7- A0 M7- M0 2 D7 - D0, until CS high 3 Notes: 1. Clocks 0 - 7 are the command byte. All commands and address bits on I/O0. 2. Mode Byte. See “Execute in Place (XIP) Mode” on page 42 for more information on XIP operation with FRQO. 3. Quad Mode data output. I/O0 switches from Input to Output. I/O1-3 active outputs until CS returns high. tCSH must be ob- served for valid output when bringing CS high.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Fast Read Quad Address and Data (FRQAD) The Fast Read Quad Address and Data (FRQAD) command is similar to the FRQO command except that the address bits are loaded into the four I/O’s, requiring six clocks instead of 24. The data bytes also are read from the four I/O’s as shown in Figure 18 below. An XIP operating mode is available for this command. See “Table 15 – XIP Operation with FRQAD Command” on page 51 for more information on the XIP operating mode for this command. The FRQAD command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the IO pins. Reads continue as long as the memory is clocked. The command is terminated by bringing CS high. Commmand Operation and Timing next page.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 SCK CS 0 1 2 3 4 5 6 7 Instruction (EBh) 1 1 1 0 1 0 1 1 Mode 3 Mode 0 IO0 SCK CS 13 14 15 16 17 18 19 20 21 22 23 Mode Bits IO0 0 IO1 IO2 IO3 1620 8 4 0 (Low) A23 - 16 A15 - 8 A7 - 0 24-Bit Address 131721 9 5 1 141822 10 6 2 151923 11 7 3 High Impedance High High IO switches from Input to Output 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 404 0 4 0 4 0 4 IO1 IO2 IO3 8 9 10 11 12 13 14 15 Mode Bits M0M4 M1M5 M2M6 M3M7 Data Clocked Out Continuously until CS high. Note: 1. The I/O pins should be high impedance prior to the falling edge of the second mode clock. Figure 18 – Fast Read Quad Address and Data (FRQAD) Command Operation Notes: 1. Clocks 0 - 7 are the command byte. All commands and address bits on I/O0. 2. Mode Byte. See “Execute in Place (XIP) Mode” on page 42 for more information on XIP operation with FRQAD. 3. Quad Mode data output. I/O0 switches from Input to Output. I/O1-3 active outputs until CS returns high. tCSH must be ob- served for valid output when bringing CS high. 4. For timing details, see “Figure 38 – Synchronous Data Timing Fast Write Quad Data and Fast Write Quad Address and Data (FWQD and FWQAD)” on page 64. Clock Number Name Description 0 - 7 1 8 - 13 4 14- 15 2 16 - 17 18 - n FRQAD Fast Read Quad Address and Data EBh A23 - A0 M7 - M0 2 D7 - D0 every two clocks until CS high 3

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Fast Write Quad Data (FWQD) The Fast Write Quad Data FWQD command provides a high speed write capability to the memory using four I/O’s for data input. The FWQD command can operate at the highest frequency, fSCK = 104MHz. The FWQD command is entered by driving CS low and sending the command code (32h). Data is input on all four I/O’s and Writes continue as long as the memory is clocked. The command is terminated by bringing CS high. Figure 19 – Fast Write Quad Data (FWQD) Command Operation SCK CS 0 1 2 3 4 5 6 7Mode 3 Mode 0 8 9 10 29 30 31 SCK CS 31 32 33 34 35 36 37 38 39 (Low) IO0 IO1 IO2 IO3 Data Bytes 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 404 0 4 0 4 0 4 Byte n Instruction (32h) 0 0 1 1 0 0 1 0IO0 24-Bit Address High Impedance High High IO1 IO2 IO3 2223 21 2 1 0 Data Writes Continuously until CS high. Notes: 1. Clocks 0 - 7 are the command byte. All commands and address bits on I/O0. 2. Quad Mode address input. I/O0 remains input. I/O1-3 active inputs until CS returns high. 3. For timing details, see “Figure 38 – Synchronous Data Timing Fast Write Quad Data and Fast Write Quad Address and Data (FWQD and FWQAD)” on page 64. Clock Number Name Title 0 - 7 1 8 - 15 16 - 23 24 - 31 32 - 33 34 - 35 36 - n FWQD Fast Write Quad Data 32h A23-A16 A15 - A8 A7- A0 D7 - D0 every two clocks until CS high 2

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Fast Write Quad Address and Data (FWQAD) The Fast Write Quad Address and Data Command (FWQAD) provides a very fast write at both the highest frequency and fewest clock cycles. The 24-bit address is input on all four I/O’s, reducing the number of clock cycles. The data bytes to be written are also input on all four I/O’s following the address bits. The FWQAD command can operate at the highest frequency, fSCK = 104MHz. The FWQAD command is entered by driving CS low and sending the command code (12h). Data are input on all four I/O’s and Writes continue as long as the memory is clocked. The command is terminated by bring- ing CS high. Figure 20 – Fast Write Quad Address and Data (FWQAD) Command Operation SCK CS 0 1 2 3 4 5 6 7 Instruction (12h) 0 0 0 1 0 0 1 0 Mode 3 Mode 0 IO0 SCK CS 13 14 15 16 17 18 19 20 21 1620 8 4 0 (Low) A23 - 16 A15 - 8 A7 - 0 24-Bit Address 131721 9 5 1 141822 10 6 2 151923 11 7 3 High Impedance High High IO1 IO2 IO3 8 9 10 11 12 13 IO0 IO1 IO2 IO3 Data Bytes 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 404 0 4 0 4 0 4 Byte n Data Writes Continuously until CS high. Clock Number Name Description 0 - 7 1 8 - 13 4 14 - 15 2 16 - n FWQAD Fast Write Quad Address and Data 12h A23 - A0 D7 - D0 every two clocks until CS high 2 Notes: 1. Clocks 0 - 7 are the command byte. All commands and address bits on I/O0. 2. Quad Mode address input. I/O0 remains input. I/O1-3 active inputs until CS returns high.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 QPI MODE QPI Mode is designed to reduce command entry overhead in an XIP environment. QPI mode allows the instruction code to be entered on all four I/O’s, which reduces the number of clock cycles required for com- mand entry to two from eight. Otherwise, all SPI or Quad SPI commands operate normally. In SPI or Quad SPI mode device operation is determined by which command is entered. To operate in QPI Mode, the device must be specifically placed into QPI Mode by invoking the Enable QPI Command. When in QPI Mode, the Status Register Bit 6 is set to 1 and will reset to 0 when either power is removed from the device or the QPI Mode is exited with an DQPI command. At power up, QPI mode is disabled. Table 10 – SPI Mode Command Structures in QPI Mode Clock Number Name Description 0 - 1 1 2 - 9 10 - 17 18 - 25 26 - 33 34 - n RDSR Read Status Register 05h S7-S0 - - - - WREN Write Enable 06h - - - - - WRDI Write Disable 04h - - - - - WRSR Write Status Register 01h S7-S0 - - - - READ Read Data Bytes 03h A23-A16 A15-A8 A7-A0 D7-D0 until CS high FREAD Fast Read Data Bytes 08h A23-A16 A15-A8 A7-A0 M7 - M0 2 D7-D0 until CS high WRITE Write Data Bytes 02h A23-A16 A15-A8 A7-A0 D7-D0 until CS high SLEEP Enter Sleep Mode B9h - - - - - WAKE Exit Sleep Mode ABh - - - - - TDET Tamper Detect 17h M7 - M0 3 T7 - T0 RDID Read ID 4Bh M7 - M0 3 Device ID 40 bits DQPI Disable QPI FFh - - - - - Notes: 1. Clocks 0 - 1 are the command bits while in QPI mode. 2. M7 - M0 is the Mode Byte to Set/Reset XIP Mode. Set XIP Mode = EFh; Reset XIP Mode = FFh. 3. Mode Byte must be FFh for TDET and RDID.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Clock Number Name Description 0 - 1 1 2 - 9 10 - 17 18 - 25 26 - 27 28 - n DQPI Disable QPI FFh - - - - - FRQO Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 M7 - M0 2 D7-D0 until CS high FWQD Fast Write Quad Data 32h A23-A16 A15-A8 A7-A0 D7-D0 until CS high Clock Number Name Description 0 - 1 1 2 - 3 4 - 5 6 - 7 8 - 9 10 - n FRQAD Fast Read Quad Ad- dress and Data EBh A23-A16 A15-A8 A7-A0 M7 - M0 2 D7-D0 until CS high FWQAD Fast Write Quad Ad- dress and Data 12h A23-A16 A15-A8 A7-A0 D7-D0 until CS high Table 11 – Quad SPI Mode Command Structures in QPI Mode Notes: 1. Clocks 0 - 1 are the command bits while in QPI mode. 2. Mode Byte. Set/Reset XIP operating mode. See “Execute in Place (XIP) Mode” on page 42.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Enable QPI (EQPI) Command Figure 21 – Enable QPI Mode (EQPI) Command Operation The Enable QPI command is used to enter the device into QPI mode. The command code, 38h, is entered on the DI pin. The command is entered by driving CS low and sending the command code. The command is terminated by driving CS high. When in QPI Mode, the Status Register Bit 6 is set to “1” and the device stays in QPI mode until a power-on reset or the Disable QPI command is entered. SCK CS 0 1 2 3 4 5 6 7 Instruction (38h) 0 0 1 1 1 0 0 Mode 3 Mode 0 SI High Impedance SO Clock Number Name Description 0 - 7 1 8 9 - n EQPI Enable QPI Mode 38h CS high In QPI Mode Notes: 1. Clocks 0 - 7 are the command byte.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Disable QPI (DQPI) Command Figure 22 – Disable QPI Mode (DQPI) Command Timing The Disable QPI command is used to exit QPI mode and return to the standard SPI/Quad SPI mode and set the Status Register Bit 6 to “0” . The command code FFh is entered on all four IO’s in just two clock cycles as shown below. The command is entered by driving CS low and sending the command code. The command is terminated by driving CS high. SCK CS 0 1 Instruction (FFh) Mode 3 Mode 0 1 1IO3 1 1IO0 1 1IO2 1 1IO1 Clock Number Name Description 0 - 1 1 2 9 - n DQPI Disable QPI Mode FFh CS high Now in SPI / Quad SPI Mode Notes: 1. Clocks 0 - 1 are the command byte on all four I/O.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 EXECUTE IN PLACE (XIP) MODE Execute in Place (XIP) mode provides faster read operations by not requiring a command code for each new starting address during consecutive reads. This improves random access time and eliminates the need to shadow code onto RAM for fast execution. The read commands supported in XIP mode are FREAD (SPI Mode), FRQO, and FRQAD (both Quad SPI Mode commands). XIP may be run when in QPI mode. Entering or exiting XIP mode will not affect other aspects of QPI mode operation. The device will stay in QPI mode until QPI is disabled with the DQPI command. XIP mode for these commands is Set or Reset by entering the Mode Byte as shown in “Table 12 – Mode Byte Definitions to Set/Reset XIP Mode” on page 42 below. In XIP Mode it is possible to perform a series of reads beginning at different addresses without having to load the command code for every new starting address / CS cycle. XIP can be entered or exited during these commands at any time and in any sequence. If it is necessary to perform another operation, not supported by XIP , such as a write, then XIP must be exited before the new command code is entered for the desired operation. Table 12 – Mode Byte Definitions to Set/Reset XIP Mode XIP Operation Hex M7 M6 M5 M4 M3 M2 M1 M0 Set/Continue EF 1 1 1 0 1 1 1 1 Reset/Stop (Default) FF 1 1 1 1 1 1 1 1

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Initial Command Clock Number SPI Mode 0 - 7 1 8 - 31 32 - 39 40 - 47 48 - n QPI Mode 0 - 1 1 3 - 26 27 - 34 35 - 42 43 - n FREAD Fast Read Data Bytes 0Bh A23-A0 M7 - M0 2 D7 - D0 Read Next Byte 24-bit Address Set XIP Mode 3 Read Data Byte Repeat until CS goes high. Table 13 – XIP Mode with FREAD Command Notes: 1. Command code eight bits. 2. Mode Byte will Set/Reset the XIP mode. See “Table 12 – Mode Byte Definitions to Set/Reset XIP Mode” on page 42 above for the Set/Reset XIP mode bit definitions. 3. If the XIP mode is not Set on the initial command, the command operates in normal SPI Mode until CS high. And, on the next new address, the FREAD the command must be reentered. If XIP Mode has been Set during this initial command entry, the command still operates normally until CS goes high. But on the next CS low, the device remains in FREAD Command mode. No command is entered and the initial read address is entered on the first clock. See the table below. If XIP Set - Next CS Low Clock Number Either SPI or QPI Mode 0 - 23 1 24 - 31 32 - 39 40 - n FREAD Fast Read Data Bytes A23-A0 M7 - M0 D7 - D0 Read Next Byte If XIP Mode is Set, the Command need not be reentered. Initial 24-bit ad- dress entry begins on the first clock. 24-bit Address Set/Reset XIP Mode Read Data Byte Repeat until CS goes high. Notes: 1. In XIP mode, the last command code sent remains in effect. The starting address is entered beginning on the first clock after CS low. 2. If XIP Mode is Reset, the device is out of XIP mode and any command may be entered on the next access.

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SI 24-Bit AddressInstruction (0Bh) 0 0 0 0 1 0 1 1 212223 3 2 1 0 MSB SO High Impedance LSB CS SCK 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SI EFh Set XIP Mode SO High Impedance 7 6 5 4 3 2 1 0 Read Data Byte 7 6 5 4 3 2 1 0 Read Next Byte Mode 3 Mode 0 Data Clocked Out Continuously until CS high. 1 1 1 0 1 1 1 1 LSB Figure 23 – FREAD Command- Set XIP Mode - Initial Access Note: 1. Initial FREAD access, XIP mode set for next access.

Figure 24 – FREAD Command - XIP Mode Set - Next Access SCK CS 0 1 2 20 21 22 23 SI 24-Bit Address 212223 3 2 1 0 MSB SO High Impedance LSB CS SCK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI EFh Continue XIP Mode SO High Impedance 7 6 5 4 3 2 1 0 Read Data Byte 7 6 5 4 3 2 1 0 Read Next Byte Mode 3 Mode 0 Data Clocked Out Continuously until CS high. 1 1 1 0 1 1 1 1 LSB Note: 1. Continue FREAD in XIP Mode after this access.

Figure 25 – FREAD Command - XIP Mode Exit SCK CS 0 1 2 20 21 22 23 SI 24-Bit Address 212223 3 2 1 0 MSB SO High Impedance LSB CS SCK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI FFh Exit XIP Mode SO High Impedance 7 6 5 4 3 2 1 0 Read Data Byte 7 6 5 4 3 2 1 0 Read Next Byte Mode 3 Mode 0 Data Clocked Out Continuously until CS high. 1 1 1 1 1 1 1 1 LSB Note: 1. XIP Mode code FFh: Reset XIP Mode. After this access a comnmand must be entered on the next access. Any new command may be en- tered, including the original command.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Table 14 – XIP Operation with FRQO Command Initial Command Clock Number Quad SPI Mode 0 - 7 1 8 - 31 32 - 33 34 - 35 36 - n QPI Mode 0 - 1 1 2 - 25 26 - 27 28 - 29 30 - n FRQO Fast Read Quad Output 6Bh A23-A0 M7 - M0 2 D7 - D0 Read Next Byte 24-bit Address Set XIP Mode 3 Read Data Byte Repeat until CS goes high. Notes: 1. Command code eight bits. 2. Mode Byte entered Set/Reset the XIP mode. See “Table 12 – Mode Byte Definitions to Set/Reset XIP Mode” on page 42 above for the Set/Reset XIP mode bit definitions. 3. If the XIP mode is not set on the initial command, the command operates in normal SPI Mode until CS high. And, on the next FRQO the command must be reentered. If XIP has been set during this initial command entry, the command still operates normally until CS goes high. But on the next CS low, the device remains in FRQO Command mode, and the initial read ad- dress is entered on the first clock. See the table below. If XIP Set - Next CS Low Either Quad SPI or QPI Mode 0 - 23 24 - 25 26 - 27 28 - n FRQO Set Fast Read Quad Output A23-A0 M7 - M0 D7 - D0 Read Next Byte If XIP Mode is Set, the Command need not be reentered. Initial 24-bit address entry begins on the first clock. 24-bit Address Set/Reset XIP Mode Read Data Byte Repeat until CS goes high. Notes: 1. In XIP operating mode, the last command code sent remains in effect and no command entry is required on the next access.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 26 – FRQO Command - Set XIP Mode - Initial Access SCK CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 24-Bit AddressInstruction (6Bh) 0 1 1 0 1 0 1 1 212223 3 2 1 0 MSB LSB Mode 3 Mode 0 IO0 IO1 High Impedance IO2 IO3 SCK CS 31 32 33 34 35 36 37 38 39 40 41 EFh IO0 0 IO1 IO2 IO3 IO switches from Input to Output 404 0 4 0 4 0 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 (Low) LSB High High Data Clocked Out Continuously until CS high. Set XIP Mode 1,2 Notes: 1. Initial access, XIP Mode Byte set for next access. 2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 27 – FRQO Command - XIP Mode Set - Next Access SCK CS 23 24 25 26 27 28 29 30 31 32 33 EFh IO0 0 IO1 IO2 IO3 IO switches from Input to Output 404 0 4 0 4 0 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 (Low) LSB Data Clocked Out Continuously until CS high. Set (Continue) XIP Mode 1,2 SCK CS 0 1 2 20 21 22 23 24-Bit Address 212223 3 2 1 0 MSB LSB Mode 3 Mode 0 IO0 IO1 High Impedance IO2 IO3 High High Notes: 1. Next access, set to continue XIP Mode. 2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 28 – FRQO Command - XIP Mode Exit SCK CS 0 1 2 20 21 22 23 24-Bit Address 212223 3 2 1 0 MSB LSB Mode 3 Mode 0 IO0 IO1 High Impedance IO2 IO3 High High SCK CS FFh IO0 0 IO1 IO2 IO3 IO switches from Input to Output 404 0 4 0 4 0 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 (Low) LSB Data Clocked Out Continuously until CS high. Reset XIP Mode 1,2 23 24 25 26 27 28 29 30 31 32 33 Notes: 1. XIP Mode Byte FFh. Exit XIP Mode. 2. The I/O pins should be high impedance prior to the falling edge of the second mode clock. 3. After this access a command must be entered on the next access. Any new command may be entered, including the original command.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Table 15 – XIP Operation with FRQAD Command Initial Command Clock Number Quad SPI Mode 0 - 7 1 8 - 13 14 - 15 16 - 17 18 - n QPI Mode 0 - 1 1 2 - 7 8 - 9 10 - 11 12 - n FRQAD Fast Read Quad Ad- dress and Data EBh A23-A0 M7 - M0 2 D7 - D0 Read Next Byte 24-bit Address Set XIP Mode 3 Read Data Byte Repeat until CS goes high. Notes: 1. Command code eight bits. 2. Mode Byte entered Set/Reset the XIP mode. See “Table 12 – Mode Byte Definitions to Set/Reset XIP Mode” on page 42 above for the Set/Reset XIP mode bit definitions. 3. If the XIP mode is not set on the initial command, the command operates in normal SPI Mode until CS high. And, on the next FRQAD the command must be reentered. If XIP has been set during this initial command entry, the command still operates normally until CS goes high. But on the next CS low, the device remains in FREAD Command mode, and the initial read ad- dress is entered on the first clock. See the table below. If XIP Set - Next CS Low Either Quad SPI or QPI Mode 0 - 5 6 - 7 8 - 9 10 - n FRQAD Set Fast Read Quad Ad- dress and Data A23-A0 M7 - M0 D7 - D0 Read Next Byte If XIP Mode is Set, the Command need not be reentered. Initial 24-bit address entry begins on the first clock. 24-bit Address Set/Reset XIP Mode Read Data Byte Repeat until CS goes high. Notes: 1. In XIP operating mode, the last command code sent remains in effect and no command entry is required on the next access.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 29 – FRQAD Command - Set XIP Mode - Initial Access SCK CS 0 1 2 3 4 5 6 7 Instruction (EBh) 1 1 1 0 1 0 1 1 Mode 3 Mode 0 IO0 SCK CS 13 14 15 16 17 18 19 20 21 22 23 EFh Set XIP Mode IO0 0 IO1 IO2 IO3 1620 8 4 0 (Low) A23 - 16 A15 - 8 A7 - 0 24-Bit Address 131721 9 5 1 141822 10 6 2 151923 11 7 3 High Impedance High High IO switches from Input to Output 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 404 0 4 0 4 0 4 IO1 IO2 IO3 8 9 10 11 12 13 Data Clocked Out Continuously until CS high. Notes: 1. Initial access, XIP Mode Byte set for next access. 2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 30 – FRQAD Command - XIP Mode Set - Next Access SCK CS Mode 3 Mode 0 IO0 1620 8 4 0 A23 - 16 A15 - 8 A7 - 0 24-Bit Address 131721 9 5 1 141822 10 6 2 151923 11 7 3 IO1 IO2 IO3 0 1 2 3 4 5 CS EFh Set (Continue) XIP Mode IO0 0 IO1 IO2 IO3 (Low) IO switches from Input to Output 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 404 0 4 0 4 0 4 Data Clocked Out Continuously until CS high. SCK 5 6 7 8 9 10 11 12 13 14 15 Notes: 1. Next access, set to continue XIP Mode. 2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 31 – FRQAD Command - XIP Mode Exit SCK CS Mode 3 Mode 0 IO0 1620 8 4 0 A23 - 16 A15 - 8 A7 - 0 24-Bit Address 131721 9 5 1 141822 10 6 2 151923 11 7 3 IO1 IO2 IO3 0 1 2 3 4 5 SCK CS FFh Reset (Exit) XIP Mode IO0 0 IO1 IO2 IO3 (Low) IO switches from Input to Output 515 1 5 1 5 1 626 2 6 2 6 2 737 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 404 0 4 0 4 0 4 Data Clocked Out Continuously until CS high. 5 6 7 8 9 10 11 12 13 14 15 Notes: 1. XIP Mode Byte FFh. Exit XIP Mode. 2. The I/O pins should be high impedance prior to the falling edge of the second mode clock. 3. After this access a command must be entered on the next access. Any new command may be entered, including the original command.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Symbol Parameter Conditions Value Unit VDD Supply voltage 1 -0.5 to 4.0 V VDDQ I/O Bus Supply voltage 1 -0.5 to 2.4 V VIN Voltage on any pin 1 -0.5 to VDDQ + 0.5 V IOUT Output current per pin ±20 mA TBIAS Temperature under bias Commercial Grade -45 to 95 °C Tstg Storage Temperature -55 to 150 °C TLead Lead temperature during solder (3 minute max) 260 °C Hmax_write Maximum magnetic field during write Write 12,000 A/m Hmax_read Maximum magnetic field during read or standby Read or Standby 12,000 A/m Notes: 1. All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than 20mA. Table 16 – Absolute Maximum Ratings ELECTRICAL SPECIFICATIONS Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Symbol Parameter Conditions Min Typical Max Unit VDD Power supply voltage 3.0 3.3 3.6 V VDDQ I/O Bus Power supply voltage 1.7 1.8 2.0 V VIH Input high voltage 1.4 VDDQ + 0.2 V VIL Input low voltage -0.2 0.4 V TA Ambient temperature under bias Commercial Grade 0 70 °C Industrial Grade -40 85 °C Extended Grade -40 105 °C Table 17 – Operating Conditions Symbol Parameter Conditions Min Max Unit IIL Input leakage current - ±2 μA IOL Output leakage current - ±2 μA VOL Output low voltage IOL = 4mA - 0.4 V VOH Output high voltage IOH = -100μA 1.4 - V Table 18 – DC Characteristics

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Symbol Parameter Conditions Typical Max Unit IDDR Active Read Current SPI @ 1 MHz 5.0 11 mA SPI @ 40 MHz 12 17 mA Quad SPI @ 104MHz - 60 mA IDDW Active Write Current @ 1 MHz 9.0 25 mA @ 40 MHz 28 42 mA Quad SPI @ 104MHz - 100 mA IDDQ Active VDDQ Current Note 1 - 3 mA ISB1 AC Standby Current (CS High = VIH. No other restrictions on other inputs.) f ≤104MHz - 8 mA ISB1Q AC Standby Current on VDDQ supply (CS High = VIH. No other restrictions on other inputs.) f ≤104MHz - 1 mA ISB2 CMOS Standby Current (CS High) f = 0 MHz - 3 mA ISB2Q CMOS Standby Current on VDDQ Supply (CS High) f = 0 MHz - 10 μA IZZ Standby Sleep Mode Current (CS High) Sleep Mode - 100 μA Table 19 – Power Supply Characteristics Symbol Parameter Typical Max Unit CIn Control input capacitance 1 - 6 pF CI/O Input/Output capacitance 1 - 8 pF Notes: 1. ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested. Table 20 – Capacitance Note 1. IDDQ Conditions: Quad SPI at 104MHz, VDDQ = 2.0v, VIH = 1.8v, VIL = 0v.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 To provide protection for data during initial power up, power loss or brownout, whenever VDD falls below VWIDD or VDDQ falls below VWIDDQ the device cannot be selected (CS is restricted from going low) and the device is inhibited from Read or Write operations. See “Table 22 – Power-Up Delay Minimum Voltages and Timing” below. Power Up Delay Time During initial power up or when recovering from brownout or power loss, a power up delay time (tPU) must be added to the time required for voltages to rise to their specified minimum voltages (VDD(min) and VDDQ(min)) before normal operations may commence. This time is required to insure that the device internal voltages have stabilized. See “Table 22 – Power-Up Delay Minimum Voltages and Timing” below. tPU is measured from the time that both VDD and VDDQ have reached their specified minimum voltages. See “Figure 34 – Power-Up Timing” for an illustration of the timing. During initial startup or power loss recovery the CS pin should always track VDDQ (up to VDDQ + 0.2 V) or VIH, whichever is lower, and remain high for the total startup time, tPU. In most systems, this means that CS should be pulled up to VDDQ with a resistor. Any logic that drives other inputs or IOs should hold the signals at VDDQ until normal operation can commence. Symbol Parameter Min Unit VWIDD Write Inhibit Voltage 2.2 V VWIDDQ I/O Write Inhibit Voltage 1.2 V tPU Power Up Delay Time 400 μs Table 22 – Power-Up Delay Minimum Voltages and Timing Power Up Timing

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 34 – Power-Up Timing BROWNOUT or POWER LOSS VDDQ min NORMAL OPERATION tPU STARTUP TIME INITIAL POWER ON VDD min VWIDD VWIQQ VDDQ VDD READ/WRITE operations inhibited NORMAL OPERATION RECOVER TIME tPU READ/WRITE operations inhibited Note: CS may not be enabled until tPU startup or recovery time is met.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Symbol Parameter Min Typical Max Unit fSCK SCK Clock Frequency for all instructions except READ - - 104 MHz SCK Clock freq for READ - - 40 MHz tRI Input Rise Time - - 50 ns tRF Input Fall Time - - 50 ns tWH SCK High Time except READ 4 - - ns tWHR SCK High Time READ 11 - - ns tWL SCK Low Time except READ 4 - - ns tWLR SCK Low Time READ 12 - - ns Synchronous Data Timing see Figures 35, 36, 37, 38 tCSS CS Setup Time 5 - - ns tCSH CS Hold Time 5 - - ns tSU Data In Setup Time 2 - - ns tH Data In Hold Time 5 - - ns tV Output Valid - - 7 ns tHO Output Hold Time 1.5 - - ns tCS CS High Time at end of all Cycles except Writes 10 - - ns tCSW CS High Time at end of Write Cycles 50 - - ns Table 23 – AC Timing Parameters AC Timing Parameters

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Symbol Parameter Min Typical Max Unit HOLD Timing see Figure 39 tHD HOLD Setup Time 2 - - ns tCD HOLD Hold Time 2 - - ns tLZ HOLD to Output Low Impedance - - 12 ns tHZ HOLD to Output High Impedance - - 7 ns Other Timing Specifications tWPS WP Setup To CS Low 5 - - ns tWPH WP Hold From CS High 5 - - ns tDP Sleep Mode Entry Time - - 3 μs tRDP Sleep Mode Exit Time - - 400 μs tDIS Output Disable Time - - 7 ns AC Timing Parameters - Continued

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 SCK SO CS HOLD HDt HZt CDt CDt LZt HDt Figure 39 – HOLD Timing

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 PART NUMBERS AND ORDERING Table 24 – Part Numbering System Memory Interface Density Revision Temp Package Ship Grade Example Ordering Part Number MR 10Q 010 C SC R MRAM (Toggle) MR 104MHz Quad SPI Family 10Q

1 Mb 010

4 Mb 040

Commercial 0 to 70°C Blank Industrial -40 to 85°C C 16-pin SOIC SC Tray Blank Tape and Reel R Customer Samples CS Mass Production Blank Extended -40 to 105°C V 24-ball BGA MB Table 25 – Ordering Part Numbers Temp Grade Temperature Package Shipping Container Order Part Number Commercial 0 to 70°C 16-SOIC Trays MR10Q010SC Tape and Reel MR10Q010SCR 24-BGA Trays MR10Q010MB Tape and Reel MR10Q010MBR Industrial -40 to 85°C 16-SOIC Trays MR10Q010CSC Tape and Reel MR10Q010CSCR 24-BGA Trays MR10Q010CMB Tape and Reel MR10Q010CMBR Extended -40 to 105°C 16-SOIC Trays MR10Q010VSC Tape and Reel MR10Q010VSCR 24-BGA Trays MR10Q010VMB Tape and Reel MR10Q010VMBR

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 PACKAGE CHARACTERISTICS Table 26 – Thermal Resistance 16-pin SOIC Velocity TA 1 PD

2 TJ Max 3 ΘJA

4 ΘJB ΘJC m/s °C W °C °C/W 25 0.792 71.0 58.1 30.6 31.6 1 64.5 49.9 2 62.8 47.7 3 61.8 46.4 Notes: 1. TA - Ambient temperature. 2. PD - Power dissipation at maximum VDD and IDDW. 3. TJ Max - Maximum junction temperature reached at maximum power dissipation. 4. ΘJA - Junction to ambient. 5. ΘJB - Junction to board. 6. ΘJC - Junction to package case. All thermal resistance values are estimated by simulation.

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Figure 40 – 16-SOIC Package Outline Dimensions next page. E b e D A A2 LD C L L1

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Symbol JEDEC MS - 013 (AA) issue (mm) Everspin POD 16L SOIC PKG OUTLINE DWG. 300 MIL (mm) Ref MIN NOM MAX MIN NOM MAX A - - 2.65 2.46 2.56 2.64 A2 2.05 - - 2.29 2.34 2.39 D 10.30 BSC 10.21 10.34 10.46 E 10.30 BSC 10.16 10.31 10.63 E1 7.50 BSC 7.44 7.52 7.59 L1 1.40 REF N/A e 1.27 BSC 1.27 BSC Θ 0° - 8° 0° 5° 8°

Figure 41 – 24 Ball BGA Package Outline

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Revision Date Description of Change 1.7 February 26, 2013 Initial Release Preliminary. 1.8 March 7, 2013 Revision to Table 5. Revision to HOLD timing Table 15. Corrected package illustration. 1.9 May 14, 2013 Added QPI Commands. 2.0 October 24, 2013 Removed QPI Commands, TDET and reference to XIP . These features will be released in a future product revision.

3.0 April 17, 2014

Major revision. Complete restructure of command section. Added QPI Mode, TDET, TDETX commands and XIP operating mode commands, instructions and timing diagrams. Removed Preliminary watermark from all pages. Removed Max and Typical values for VWIDD and VWIDDQ.

4.0 December 17,

Added ISB1Q, ISB2, ISB2Q, IDDQ values. Revisions to Command Descriptions for FRQO and FRQAD. Revisions to Note 3 for Command Timing Diagrams for FRQO and FRQAD. Added package thermal resistance table. IDD values in Table 8 have been updated. 4.2 May 19, 2015 Revised Everspin contact information. 4.3 June 11, 2015 Corrected Japan Sales Office telephone number. 5.0 August 12, 2015 Added 6x8mm 24-ball BGA package outline and dimensions. 5.1 January 26, 2017 Table 23: Revised tWHR = 11ns; tWLR = 12ns. 16-SOIC package options released to MP . 24-BGA now qualified. 5.2 February 1, 2017 Figures 35 and 36 - Synchronous Data Timing. Added timing detail for tV and tHO.

5.3 December 4, 2017 Figure 40 updated with new dimensions

5.4 January 26, 2018 Added extended temperature range to the data sheet.

5.5 March 15, 2018 Added extended range to Table 17

5.6 June 1, 2018 Updated table 24

REVISION HISTORY

Copyright © 2018 Everspin Technologies, Inc. MR10Q010 Information in this document is provided solely to enable system and soft- ware implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representa- tion or guarantee regarding the suitability of its products for any particu- lar purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each cus- tomer application by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of oth- ers. Everspin Technologies products are not designed, intended, or au- thorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may oc - cur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affili- ates, and distributors harmless against all claims, costs, damages, and ex - penses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright © 2018 Everspin Technologies, Inc. HOW TO REACH US Contact Information: How to Reach Us: Home Page: www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com