MR0D08B

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MR0D08B EVERSPIN | Alldatasheet

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+3.3 Volt power supply
I/O Voltage range supports wide +1.65 to +3.6 Volt interfaces
Fast 45 ns read/write cycle
SRAM compatible timing
Unlimited read & write endurance
Data always non-volatile for >20-years at temperature
RoHS-compliant small footprint BGA package INTRODUCTION The MR0D08B is a dual power supply 1,048,576-bit magnetoresistive random access memory (MRAM) de- vice organized as 131,072 words of 8 bits. It supports I/O voltages from +1.65 to +3.6 volts. The MR0D08B offers SRAM compatible 45ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to pre- vent writes with voltage out of specification. The MR0D08B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR0D08B is available in small footprint 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. The MR0D08B provides highly reliable data storage over a wide range of temperatures. The product is of- fered with commercial temperature (0 to +70 °C). RoHS

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 CHIP ENABLE BUFFER OUTPUT ENABLE BUFFER ADDRESS BUFFER WRITE ENABLE BUFFER G E OUTPUT ENABLE 128Kx 8 BIT MEMORY ARRAY ROW DECODER COLUMN DECODER SENSE AMPS OUTPUT BUFFER WRITE DRIVER FINAL WRITE DRIVERS WRITE ENABLE W A[16:0] 8 8 DQ[7:0] 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O VDD Power Supply VDDQ I/O Power Supply VSS Ground DC Do Not Connect NC No Connection, Ball D3, H1, H6, G2 Reserved for Future Expansion MR0D08B

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 1 2 3 4 5 6 G A A A A A A E B DQ A A DQ DQ C VSS DQ VDDQ D VDDQ DQ VSS EDQ A A DQ FNC A A W GNC A A H NC NC NC DCDC DC A DQ3 NC DC VDD NC NC NC NC VDD Figure 1.2 Pin Diagrams for Available Packages (Top View)

48 Pin FBGA

Table 1.2 Operating Modes E1 G1 W1 Mode VDD Current DQ[7:0]2 H X X Not selected ISB1, ISB2 Hi-Z L H H Output disabled IDDR Hi-Z L L H Byte Read IDDR DOut L X L Byte Write IDDW Din

1 H = high, L = low, X = don’t care

2 Hi-Z = high impedance

DEVICE PIN ASSIGNMENT MR0D08B

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Parameter Symbol Value Unit Core Supply voltage2 VDD -0.5 to 4.0 V I/O Power Supply voltage2 VDDQ -0.5 to 4.0 V Voltage on any pin2 VIN -0.5 to +4.0 or VDDQ + 0.5 whichever is less V Output current per pin IOUT ±20 mA Package power dissipation 3 PD 0.600 W Temperature under bias TBIAS -10 to 85 °C Storage Temperature Tstg -55 to 150 °C Lead temperature during solder (3 minute max) TLead 260 °C Maximum magnetic field during write Hmax_write 2000 A/m Maximum magnetic field during read or standby Hmax_read 8000 A/m 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera- tion should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. 3 Power dissipation capability depends on package characteristics and use environment. Table 2.1 Absolute Maximum Ratings1 MR0D08B

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 Parameter Symbol Min Typical Max Unit Core Power supply voltage VDD 3.0 1 3.3 3.6 V I/O Power supply voltage VDDQ 1.65 1 - 3.6 V Write inhibit voltage VWIDD 2.5 2.7 3.0 1 V Write inhibit voltage VWIDDQ 1.2 1.4 1.651 V Input high voltage (VDDQ=1.65-2.2V) VIH 1.4 - VDDQ + 0.2 2 V Input high voltage (VDDQ=2.2-2.7V) VIH 1.8 - VDDQ + 0.2 2 V Input high voltage (VDDQ=2.7-3.6V) VIH 2.2 - VDDQ + 0.2 2 V Input low voltage (VDDQ=1.65-2.2V) VIL -0.2 3 - 0.4 V Input low voltage (VDDQ=2.2-2.7V) VIL -0.2 3 - 0.6 V Input low voltage (VDDQ=2.7-3.6V) VIL -0.2 3 - 0.8 V Temperature under bias TA 0 70 °C 1 VDDQ≤VDD. Write inhibit occurs when either VDD or VDDQ drops below its write inhibit voltage. There is a 2 ms startup time once VDD exceeds VDD(min). See Power Up and Power Down Sequencing. 2 VIH(max) = VDDQ + 0.2 V DC ; VIH(max) = VDDQ + 0.5 V AC (pulse width ≤ 20 ns) for I ≤ 20.0 mA. 3 V IL(min) = -0.2 V DC ; VIL(min) = -2.0 V AC (pulse width ≤ 20 ns) for I ≤ 20.0 mA. Table 2.2 Operating Conditions MR0D08BElectrical Specifications

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 Power Up and Power Down Sequencing The MRAM is protected from write operations whenever VDD is less than VWIDD or VDDQ is less than VWIDDQ. As soon as VDD exceeds VDD(min) and VDDQ exceeds VDDQ(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resis- tor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where either VDD goes below VWIDD or VDDQ goes below VWIDDQ, writes are pro- tected and a startup time must be observed when power returns above VDD(min) and / or VDDQ. Figure 2.1 Power Up and Power Down Diagram BROWNOUT or POWER LOSS NORMAL OPERATION VDD / VDDQ READ/WRITE INHIBITED VWIDD VWIDDQ 2 ms READ/WRITE INHIBITED VIH STARTUP NORMAL OPERATION 2 ms E W RECOVER VIH MR0D08BElectrical Specifications

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 Parameter Symbol Typical Max Unit AC active supply current - read modes1 (IOUT= 0 mA, VDD= max) IDDR 25 30 mA AC active supply current - write modes1 (VDD= max) IDDW 55 65 mA AC active operating current (VDDQ = VIH= 3.6V, VIL= 0V) input transitions <2ns, no output load IDDQ 0.50 2 mA AC standby current (VDD= max, E = VIH) no other restrictions on other inputs ISB1 6 8 mA CMOS standby current (E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDDQ - 0.2 V) (VDD = max, f = 0 MHz) ISB2 5 7 mA 1 All active current measurements are measured with one address transition per cycle and at minimum cycle time. Parameter Symbol Min Typical Max Unit Input leakage current Ilkg(I) - - ±1 μA Output leakage current Ilkg(O) - - ±1 μA Output low voltage (VDDQ=1.65-2.2V@ 0.1mA) VOL - - 0.2 V Output low voltage (VDDQ=2.2-2.7V@ 0.1mA) VOL - - 0.4 V Output low voltage (VDDQ=2.7-3.6V@ 2.1 mA) VOL - - 0.4 V Output high voltage (VDDQ=1.65-2.2V@ - 0.1 mA) VOH 1.4 - - V Output high voltage (VDDQ=2.2-2.7V@ -0.1 mA) VOH 2 - - V Output high voltage (VDDQ=2.7-3.6V@ -1.0 mA) VOH 2.4 - - V Table 2.3 DC Characteristics Table 2.4 Power Supply Characteristics MRD08BElectrical Specifications

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 MR0D08BTiming Specifications Table 3.4 Write Cycle Timing 1 (W Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 45 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 25 - ns Address valid to end of write (G low) tAVWH 25 - ns Write pulse width (G high) tWLWH tWLEH 20 - ns Write pulse width (G low) tWLWH tWLEH 20 - ns Data valid to end of write tDVWH 15 - ns Data hold time tWHDX 0 - ns Write low to data Hi-Z3 tWLQZ 0 15 ns Write high to output active3 tWHQX 3 - ns Write recovery time tWHAX 12 - ns 1 All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 All write cycle timings are referenced from the last valid address to the first transition address. 3 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given voltage or temperature, tWLQZ(max) < tWHQX(min) A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) Q (DATA OUT) D (DATA IN) tAVAV tAVWH tWHAX tWLEH tWHDXtDVWH tWHQX tAVWL t Hi-Z Hi-Z WLQZ tWLWH Data Valid Figure 3.4 Write Cycle Timing 1 (W Controlled)

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 MR0D08BTiming Specifications Table 3.5 Write Cycle Timing 2 (E Controlled)1 Figure 3.5 Write Cycle Timing 2 (E Controlled) Parameter Symbol Min Max Unit Write cycle time2 tAVAV 45 - ns Address set-up time tAVEL 0 - ns Address valid to end of write (G high) tAVEH 25 - ns Address valid to end of write (G low) tAVEH 25 - ns Enable to end of write (G high) tELEH tELWH 20 - ns Enable to end of write (G low)3 tELEH tELWH 20 - ns Data valid to end of write tDVEH 15 - ns Data hold time tEHDX 0 - ns Write recovery time tEHAX 12 - ns 1 All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 All write cycle timings are referenced from the last valid address to the first transition address. 3 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) Q (DATA OUT) D (DATA IN) tAVAV tAVEH tEHAX tELEH tEHDXtDVEH tAVEL Hi-Z tELWH Data Valid

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 MR0D08BTiming Specifications Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)1 Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled) Parameter Symbol Min Max Unit Write cycle time2 tAVAV 45 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 25 - ns Address valid to end of write (G low) tAVWH 25 - ns Write pulse width tWLWH tWLEH 20 - ns Data valid to end of write tDVWH 15 - ns Data hold time tWHDX 0 - ns Enable recovery time tEHAX -2 - ns Write recovery time3 tWHAX 6 - ns Write to enable recovery time3 tWHEL 12 - ns 1 All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 All write cycle timings are referenced from the last valid address to the first transition address. 3 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. t AVWL t AVAV t AVWH t WLWH t WLEH t DVWH tWHDX t WHAX t t EHAX WHEL W (WRITE ENABLE) A (ADDRESS) E (CHIP ENABLE) D (DATA IN)

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 MR0D08B 4. ORDERING INFORMATION Figure 4.1 Part Numbering System Carrier (Blank= Tray,R=Tape & Reel) Speed (45 = 45 ns) Package (MA = FBGA) Temperature Range (Blank= 0 to +70 °C) Revision (B = Revision) Data Width (08 = 8-Bit) Type (D = Dual Supply) Density (0 = 1Mb) Part Type (MR = Magnetoresistive RAM) MR 0 D 08 B MA 45 R Part Number Description Temperature MR0D08BMA45 Dual Supply 128x8 MRAM 48-BGA Commercial MR0D08BMA45R Dual Supply 128x8 MRAM 48-BGA Tape & Reel Commercial Table 4.1 Available Parts

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 TOP VIEW BOTTOM VIEW SIDE VIEW 0.410.31 0.32 0.22 Figure 5.1 FBGA Print Version Not To Scale 1. Dimensions in Millimeters. 2. Dimensions and tolerances per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured parallel to DATUM A 4. DATUM A, the seating plane is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. MR0D08BMechanical Drawings

0 Aug 24, 2009 Initial Product Concept

1 Oct 22, 2009

Added Write Cycle Timing 3. In table 2.4, ISB1 max changes from 7 to 8 mA and ISB2 from 6 to 7 mA. Added Tape & Reel Option in table 4.1. Changed to Pro- duction Level 2 Apr 7, 2010 Added IDDQ specification in table 2.4. 3 Dec 9, 2011 Corrected Figure 5.1 FBGA drawing ball dimensions. 3.1 May 19, 2015 Revised contact information on Contact US page. 3.2 June 11, 2015 Correction to Japan Sales Office telephone number.

3.3 March 22,

2018 Updated the Contact Us table

REVISION HISTORY

MR0D08B Rev. 3.3, 3/2018 Copyright © Everspin Technologies 2018 Everspin Technologies, Inc. Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representa- tion or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or inci- dental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in differ- ent applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each customer ap- plication by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other ap- plication in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Tech- nologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright © Everspin Technologies, Inc. 2018 Home Page: www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85224 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com Filename: MR0D08B_Datasheet_EST370_Rev3.3 032218 HOW TO CONTACT US

Product Information

MR0D08B specifications and overview.

Summary

Dual Supply 128K x 8 MRAM Rev. 3.3, 3/2018

Description